drm/i915: set the DIP port on ibx_write_infoframe

Just like Gen 4, IBX has a "Port Select" field on the DIP register,
but the ports are different.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2 files changed, 17 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ce6e64dd00ff..4a97db25cd34 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1700,6 +1700,7 @@
 #define   VIDEO_DIP_ENABLE              (1 << 31)
 #define   VIDEO_DIP_PORT_B              (1 << 29)
 #define   VIDEO_DIP_PORT_C              (2 << 29)
+#define   VIDEO_DIP_PORT_D              (3 << 29)
 #define   VIDEO_DIP_PORT_MASK           (3 << 29)
 #define   VIDEO_DIP_ENABLE_AVI          (1 << 21)
 #define   VIDEO_DIP_ENABLE_VENDOR       (2 << 21)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 539073ec56bd..9902904de2ce 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -178,10 +178,26 @@ static void ibx_write_infoframe(struct drm_encoder *encoder,
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct drm_crtc *crtc = encoder->crtc;
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
         unsigned i, len = DIP_HEADER_SIZE + frame->len;
         u32 val = I915_READ(reg);
 
+        val &= ~VIDEO_DIP_PORT_MASK;
+        switch (intel_hdmi->sdvox_reg) {
+        case HDMIB:
+                val |= VIDEO_DIP_PORT_B;
+                break;
+        case HDMIC:
+                val |= VIDEO_DIP_PORT_C;
+                break;
+        case HDMID:
+                val |= VIDEO_DIP_PORT_D;
+                break;
+        default:
+                return;
+        }
+
         intel_wait_for_vblank(dev, intel_crtc->pipe);
 
         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */