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authorBen Skeggs <bskeggs@redhat.com>2011-04-07 20:07:34 -0400
committerBen Skeggs <bskeggs@redhat.com>2011-04-19 18:50:37 -0400
commit01d153326ecd81ed77395f1699a30af416cf77ab (patch)
treeef988a2e87ed82d40cc06a752dcdf139bb968ffa /drivers/gpu
parent04eb34a43ce5168e05e2748bd46a62a09289cdde (diff)
drm/nouveau: fix nv30 pcie boards
Wasn't aware they even existed, apparently they do! They're actually AGP chips with a bridge as far as I can tell, which puts them in the same boat as nv40/nv45. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_mem.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_sgdma.c4
2 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 78f467fe30be..5045f8b921d6 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -398,7 +398,7 @@ nouveau_mem_vram_init(struct drm_device *dev)
398 dma_bits = 40; 398 dma_bits = 40;
399 } else 399 } else
400 if (drm_pci_device_is_pcie(dev) && 400 if (drm_pci_device_is_pcie(dev) &&
401 dev_priv->chipset != 0x40 && 401 dev_priv->chipset > 0x40 &&
402 dev_priv->chipset != 0x45) { 402 dev_priv->chipset != 0x45) {
403 if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(39))) 403 if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(39)))
404 dma_bits = 39; 404 dma_bits = 39;
diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
index a33fe4019286..fc292443039e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
@@ -427,7 +427,7 @@ nouveau_sgdma_init(struct drm_device *dev)
427 u32 aper_size, align; 427 u32 aper_size, align;
428 int ret; 428 int ret;
429 429
430 if (dev_priv->card_type >= NV_50 || drm_pci_device_is_pcie(dev)) 430 if (dev_priv->card_type >= NV_40 && drm_pci_device_is_pcie(dev))
431 aper_size = 512 * 1024 * 1024; 431 aper_size = 512 * 1024 * 1024;
432 else 432 else
433 aper_size = 64 * 1024 * 1024; 433 aper_size = 64 * 1024 * 1024;
@@ -457,7 +457,7 @@ nouveau_sgdma_init(struct drm_device *dev)
457 dev_priv->gart_info.func = &nv50_sgdma_backend; 457 dev_priv->gart_info.func = &nv50_sgdma_backend;
458 } else 458 } else
459 if (drm_pci_device_is_pcie(dev) && 459 if (drm_pci_device_is_pcie(dev) &&
460 dev_priv->chipset != 0x40 && dev_priv->chipset != 0x45) { 460 dev_priv->chipset > 0x40 && dev_priv->chipset != 0x45) {
461 if (nv44_graph_class(dev)) { 461 if (nv44_graph_class(dev)) {
462 dev_priv->gart_info.func = &nv44_sgdma_backend; 462 dev_priv->gart_info.func = &nv44_sgdma_backend;
463 align = 512 * 1024; 463 align = 512 * 1024;