aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu
diff options
context:
space:
mode:
authorAlex Deucher <alexander.deucher@amd.com>2014-09-23 09:37:37 -0400
committerAlex Deucher <alexander.deucher@amd.com>2014-10-01 09:00:05 -0400
commit186b1b2ba2a0684e3d2d3703427a993a3b35b16d (patch)
tree84c204617242ed519f5841e0456cf53af428b8da /drivers/gpu
parent7bf05cc1628679756495f15c69cecc1fd31e7c78 (diff)
drm/radeon/dpm: drop clk/voltage dependency filters for SI
Not sure this was ever necessary for SI, was just done to be on the safe side. bug: https://bugs.freedesktop.org/show_bug.cgi?id=69721 Reviewed-by: Alexandre Demers <alexandre.f.demers@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/si_dpm.c24
1 files changed, 0 insertions, 24 deletions
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index 70e61ffeace2..9e4d5d7d348f 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -2916,7 +2916,6 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2916 bool disable_sclk_switching = false; 2916 bool disable_sclk_switching = false;
2917 u32 mclk, sclk; 2917 u32 mclk, sclk;
2918 u16 vddc, vddci; 2918 u16 vddc, vddci;
2919 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2920 int i; 2919 int i;
2921 2920
2922 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2921 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
@@ -2950,29 +2949,6 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2950 } 2949 }
2951 } 2950 }
2952 2951
2953 /* limit clocks to max supported clocks based on voltage dependency tables */
2954 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2955 &max_sclk_vddc);
2956 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2957 &max_mclk_vddci);
2958 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2959 &max_mclk_vddc);
2960
2961 for (i = 0; i < ps->performance_level_count; i++) {
2962 if (max_sclk_vddc) {
2963 if (ps->performance_levels[i].sclk > max_sclk_vddc)
2964 ps->performance_levels[i].sclk = max_sclk_vddc;
2965 }
2966 if (max_mclk_vddci) {
2967 if (ps->performance_levels[i].mclk > max_mclk_vddci)
2968 ps->performance_levels[i].mclk = max_mclk_vddci;
2969 }
2970 if (max_mclk_vddc) {
2971 if (ps->performance_levels[i].mclk > max_mclk_vddc)
2972 ps->performance_levels[i].mclk = max_mclk_vddc;
2973 }
2974 }
2975
2976 /* XXX validate the min clocks required for display */ 2952 /* XXX validate the min clocks required for display */
2977 2953
2978 if (disable_mclk_switching) { 2954 if (disable_mclk_switching) {