diff options
author | Francisco Jerez <currojerez@riseup.net> | 2009-12-26 08:39:46 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2010-01-10 23:41:12 -0500 |
commit | ea911a1cf4f9c5bef18ff399ee2e2ec77792b650 (patch) | |
tree | 5a1540f12b8cfa90b761a4aca37b9a1e898c372a /drivers/gpu | |
parent | a5027ccd3c1abe190d2b84a2d7e40d5f099e48a7 (diff) |
drm/nv04: Context switching fixes.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/nouveau/nv04_graph.c | 152 |
1 files changed, 78 insertions, 74 deletions
diff --git a/drivers/gpu/drm/nouveau/nv04_graph.c b/drivers/gpu/drm/nouveau/nv04_graph.c index 82c77f9d4695..98f3b40318d4 100644 --- a/drivers/gpu/drm/nouveau/nv04_graph.c +++ b/drivers/gpu/drm/nouveau/nv04_graph.c | |||
@@ -28,6 +28,10 @@ | |||
28 | #include "nouveau_drv.h" | 28 | #include "nouveau_drv.h" |
29 | 29 | ||
30 | static uint32_t nv04_graph_ctx_regs[] = { | 30 | static uint32_t nv04_graph_ctx_regs[] = { |
31 | 0x0040053c, | ||
32 | 0x00400544, | ||
33 | 0x00400540, | ||
34 | 0x00400548, | ||
31 | NV04_PGRAPH_CTX_SWITCH1, | 35 | NV04_PGRAPH_CTX_SWITCH1, |
32 | NV04_PGRAPH_CTX_SWITCH2, | 36 | NV04_PGRAPH_CTX_SWITCH2, |
33 | NV04_PGRAPH_CTX_SWITCH3, | 37 | NV04_PGRAPH_CTX_SWITCH3, |
@@ -102,69 +106,69 @@ static uint32_t nv04_graph_ctx_regs[] = { | |||
102 | NV04_PGRAPH_PATT_COLOR0, | 106 | NV04_PGRAPH_PATT_COLOR0, |
103 | NV04_PGRAPH_PATT_COLOR1, | 107 | NV04_PGRAPH_PATT_COLOR1, |
104 | NV04_PGRAPH_PATT_COLORRAM+0x00, | 108 | NV04_PGRAPH_PATT_COLORRAM+0x00, |
105 | NV04_PGRAPH_PATT_COLORRAM+0x01, | ||
106 | NV04_PGRAPH_PATT_COLORRAM+0x02, | ||
107 | NV04_PGRAPH_PATT_COLORRAM+0x03, | ||
108 | NV04_PGRAPH_PATT_COLORRAM+0x04, | 109 | NV04_PGRAPH_PATT_COLORRAM+0x04, |
109 | NV04_PGRAPH_PATT_COLORRAM+0x05, | ||
110 | NV04_PGRAPH_PATT_COLORRAM+0x06, | ||
111 | NV04_PGRAPH_PATT_COLORRAM+0x07, | ||
112 | NV04_PGRAPH_PATT_COLORRAM+0x08, | 110 | NV04_PGRAPH_PATT_COLORRAM+0x08, |
113 | NV04_PGRAPH_PATT_COLORRAM+0x09, | 111 | NV04_PGRAPH_PATT_COLORRAM+0x0c, |
114 | NV04_PGRAPH_PATT_COLORRAM+0x0A, | ||
115 | NV04_PGRAPH_PATT_COLORRAM+0x0B, | ||
116 | NV04_PGRAPH_PATT_COLORRAM+0x0C, | ||
117 | NV04_PGRAPH_PATT_COLORRAM+0x0D, | ||
118 | NV04_PGRAPH_PATT_COLORRAM+0x0E, | ||
119 | NV04_PGRAPH_PATT_COLORRAM+0x0F, | ||
120 | NV04_PGRAPH_PATT_COLORRAM+0x10, | 112 | NV04_PGRAPH_PATT_COLORRAM+0x10, |
121 | NV04_PGRAPH_PATT_COLORRAM+0x11, | ||
122 | NV04_PGRAPH_PATT_COLORRAM+0x12, | ||
123 | NV04_PGRAPH_PATT_COLORRAM+0x13, | ||
124 | NV04_PGRAPH_PATT_COLORRAM+0x14, | 113 | NV04_PGRAPH_PATT_COLORRAM+0x14, |
125 | NV04_PGRAPH_PATT_COLORRAM+0x15, | ||
126 | NV04_PGRAPH_PATT_COLORRAM+0x16, | ||
127 | NV04_PGRAPH_PATT_COLORRAM+0x17, | ||
128 | NV04_PGRAPH_PATT_COLORRAM+0x18, | 114 | NV04_PGRAPH_PATT_COLORRAM+0x18, |
129 | NV04_PGRAPH_PATT_COLORRAM+0x19, | 115 | NV04_PGRAPH_PATT_COLORRAM+0x1c, |
130 | NV04_PGRAPH_PATT_COLORRAM+0x1A, | ||
131 | NV04_PGRAPH_PATT_COLORRAM+0x1B, | ||
132 | NV04_PGRAPH_PATT_COLORRAM+0x1C, | ||
133 | NV04_PGRAPH_PATT_COLORRAM+0x1D, | ||
134 | NV04_PGRAPH_PATT_COLORRAM+0x1E, | ||
135 | NV04_PGRAPH_PATT_COLORRAM+0x1F, | ||
136 | NV04_PGRAPH_PATT_COLORRAM+0x20, | 116 | NV04_PGRAPH_PATT_COLORRAM+0x20, |
137 | NV04_PGRAPH_PATT_COLORRAM+0x21, | ||
138 | NV04_PGRAPH_PATT_COLORRAM+0x22, | ||
139 | NV04_PGRAPH_PATT_COLORRAM+0x23, | ||
140 | NV04_PGRAPH_PATT_COLORRAM+0x24, | 117 | NV04_PGRAPH_PATT_COLORRAM+0x24, |
141 | NV04_PGRAPH_PATT_COLORRAM+0x25, | ||
142 | NV04_PGRAPH_PATT_COLORRAM+0x26, | ||
143 | NV04_PGRAPH_PATT_COLORRAM+0x27, | ||
144 | NV04_PGRAPH_PATT_COLORRAM+0x28, | 118 | NV04_PGRAPH_PATT_COLORRAM+0x28, |
145 | NV04_PGRAPH_PATT_COLORRAM+0x29, | 119 | NV04_PGRAPH_PATT_COLORRAM+0x2c, |
146 | NV04_PGRAPH_PATT_COLORRAM+0x2A, | ||
147 | NV04_PGRAPH_PATT_COLORRAM+0x2B, | ||
148 | NV04_PGRAPH_PATT_COLORRAM+0x2C, | ||
149 | NV04_PGRAPH_PATT_COLORRAM+0x2D, | ||
150 | NV04_PGRAPH_PATT_COLORRAM+0x2E, | ||
151 | NV04_PGRAPH_PATT_COLORRAM+0x2F, | ||
152 | NV04_PGRAPH_PATT_COLORRAM+0x30, | 120 | NV04_PGRAPH_PATT_COLORRAM+0x30, |
153 | NV04_PGRAPH_PATT_COLORRAM+0x31, | ||
154 | NV04_PGRAPH_PATT_COLORRAM+0x32, | ||
155 | NV04_PGRAPH_PATT_COLORRAM+0x33, | ||
156 | NV04_PGRAPH_PATT_COLORRAM+0x34, | 121 | NV04_PGRAPH_PATT_COLORRAM+0x34, |
157 | NV04_PGRAPH_PATT_COLORRAM+0x35, | ||
158 | NV04_PGRAPH_PATT_COLORRAM+0x36, | ||
159 | NV04_PGRAPH_PATT_COLORRAM+0x37, | ||
160 | NV04_PGRAPH_PATT_COLORRAM+0x38, | 122 | NV04_PGRAPH_PATT_COLORRAM+0x38, |
161 | NV04_PGRAPH_PATT_COLORRAM+0x39, | 123 | NV04_PGRAPH_PATT_COLORRAM+0x3c, |
162 | NV04_PGRAPH_PATT_COLORRAM+0x3A, | 124 | NV04_PGRAPH_PATT_COLORRAM+0x40, |
163 | NV04_PGRAPH_PATT_COLORRAM+0x3B, | 125 | NV04_PGRAPH_PATT_COLORRAM+0x44, |
164 | NV04_PGRAPH_PATT_COLORRAM+0x3C, | 126 | NV04_PGRAPH_PATT_COLORRAM+0x48, |
165 | NV04_PGRAPH_PATT_COLORRAM+0x3D, | 127 | NV04_PGRAPH_PATT_COLORRAM+0x4c, |
166 | NV04_PGRAPH_PATT_COLORRAM+0x3E, | 128 | NV04_PGRAPH_PATT_COLORRAM+0x50, |
167 | NV04_PGRAPH_PATT_COLORRAM+0x3F, | 129 | NV04_PGRAPH_PATT_COLORRAM+0x54, |
130 | NV04_PGRAPH_PATT_COLORRAM+0x58, | ||
131 | NV04_PGRAPH_PATT_COLORRAM+0x5c, | ||
132 | NV04_PGRAPH_PATT_COLORRAM+0x60, | ||
133 | NV04_PGRAPH_PATT_COLORRAM+0x64, | ||
134 | NV04_PGRAPH_PATT_COLORRAM+0x68, | ||
135 | NV04_PGRAPH_PATT_COLORRAM+0x6c, | ||
136 | NV04_PGRAPH_PATT_COLORRAM+0x70, | ||
137 | NV04_PGRAPH_PATT_COLORRAM+0x74, | ||
138 | NV04_PGRAPH_PATT_COLORRAM+0x78, | ||
139 | NV04_PGRAPH_PATT_COLORRAM+0x7c, | ||
140 | NV04_PGRAPH_PATT_COLORRAM+0x80, | ||
141 | NV04_PGRAPH_PATT_COLORRAM+0x84, | ||
142 | NV04_PGRAPH_PATT_COLORRAM+0x88, | ||
143 | NV04_PGRAPH_PATT_COLORRAM+0x8c, | ||
144 | NV04_PGRAPH_PATT_COLORRAM+0x90, | ||
145 | NV04_PGRAPH_PATT_COLORRAM+0x94, | ||
146 | NV04_PGRAPH_PATT_COLORRAM+0x98, | ||
147 | NV04_PGRAPH_PATT_COLORRAM+0x9c, | ||
148 | NV04_PGRAPH_PATT_COLORRAM+0xa0, | ||
149 | NV04_PGRAPH_PATT_COLORRAM+0xa4, | ||
150 | NV04_PGRAPH_PATT_COLORRAM+0xa8, | ||
151 | NV04_PGRAPH_PATT_COLORRAM+0xac, | ||
152 | NV04_PGRAPH_PATT_COLORRAM+0xb0, | ||
153 | NV04_PGRAPH_PATT_COLORRAM+0xb4, | ||
154 | NV04_PGRAPH_PATT_COLORRAM+0xb8, | ||
155 | NV04_PGRAPH_PATT_COLORRAM+0xbc, | ||
156 | NV04_PGRAPH_PATT_COLORRAM+0xc0, | ||
157 | NV04_PGRAPH_PATT_COLORRAM+0xc4, | ||
158 | NV04_PGRAPH_PATT_COLORRAM+0xc8, | ||
159 | NV04_PGRAPH_PATT_COLORRAM+0xcc, | ||
160 | NV04_PGRAPH_PATT_COLORRAM+0xd0, | ||
161 | NV04_PGRAPH_PATT_COLORRAM+0xd4, | ||
162 | NV04_PGRAPH_PATT_COLORRAM+0xd8, | ||
163 | NV04_PGRAPH_PATT_COLORRAM+0xdc, | ||
164 | NV04_PGRAPH_PATT_COLORRAM+0xe0, | ||
165 | NV04_PGRAPH_PATT_COLORRAM+0xe4, | ||
166 | NV04_PGRAPH_PATT_COLORRAM+0xe8, | ||
167 | NV04_PGRAPH_PATT_COLORRAM+0xec, | ||
168 | NV04_PGRAPH_PATT_COLORRAM+0xf0, | ||
169 | NV04_PGRAPH_PATT_COLORRAM+0xf4, | ||
170 | NV04_PGRAPH_PATT_COLORRAM+0xf8, | ||
171 | NV04_PGRAPH_PATT_COLORRAM+0xfc, | ||
168 | NV04_PGRAPH_PATTERN, | 172 | NV04_PGRAPH_PATTERN, |
169 | 0x0040080c, | 173 | 0x0040080c, |
170 | NV04_PGRAPH_PATTERN_SHAPE, | 174 | NV04_PGRAPH_PATTERN_SHAPE, |
@@ -247,14 +251,6 @@ static uint32_t nv04_graph_ctx_regs[] = { | |||
247 | 0x004004f8, | 251 | 0x004004f8, |
248 | 0x0040047c, | 252 | 0x0040047c, |
249 | 0x004004fc, | 253 | 0x004004fc, |
250 | 0x0040053c, | ||
251 | 0x00400544, | ||
252 | 0x00400540, | ||
253 | 0x00400548, | ||
254 | 0x00400560, | ||
255 | 0x00400568, | ||
256 | 0x00400564, | ||
257 | 0x0040056c, | ||
258 | 0x00400534, | 254 | 0x00400534, |
259 | 0x00400538, | 255 | 0x00400538, |
260 | 0x00400514, | 256 | 0x00400514, |
@@ -341,9 +337,8 @@ static uint32_t nv04_graph_ctx_regs[] = { | |||
341 | 0x00400500, | 337 | 0x00400500, |
342 | 0x00400504, | 338 | 0x00400504, |
343 | NV04_PGRAPH_VALID1, | 339 | NV04_PGRAPH_VALID1, |
344 | NV04_PGRAPH_VALID2 | 340 | NV04_PGRAPH_VALID2, |
345 | 341 | NV04_PGRAPH_DEBUG_3 | |
346 | |||
347 | }; | 342 | }; |
348 | 343 | ||
349 | struct graph_state { | 344 | struct graph_state { |
@@ -388,6 +383,18 @@ nv04_graph_context_switch(struct drm_device *dev) | |||
388 | pgraph->fifo_access(dev, true); | 383 | pgraph->fifo_access(dev, true); |
389 | } | 384 | } |
390 | 385 | ||
386 | static uint32_t *ctx_reg(struct graph_state *ctx, uint32_t reg) | ||
387 | { | ||
388 | int i; | ||
389 | |||
390 | for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) { | ||
391 | if (nv04_graph_ctx_regs[i] == reg) | ||
392 | return &ctx->nv04[i]; | ||
393 | } | ||
394 | |||
395 | return NULL; | ||
396 | } | ||
397 | |||
391 | int nv04_graph_create_context(struct nouveau_channel *chan) | 398 | int nv04_graph_create_context(struct nouveau_channel *chan) |
392 | { | 399 | { |
393 | struct graph_state *pgraph_ctx; | 400 | struct graph_state *pgraph_ctx; |
@@ -398,15 +405,8 @@ int nv04_graph_create_context(struct nouveau_channel *chan) | |||
398 | if (pgraph_ctx == NULL) | 405 | if (pgraph_ctx == NULL) |
399 | return -ENOMEM; | 406 | return -ENOMEM; |
400 | 407 | ||
401 | /* dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; */ | 408 | *ctx_reg(pgraph_ctx, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31; |
402 | pgraph_ctx->nv04[0] = 0x0001ffff; | 409 | |
403 | /* is it really needed ??? */ | ||
404 | #if 0 | ||
405 | dev_priv->fifos[channel].pgraph_ctx[1] = | ||
406 | nv_rd32(dev, NV_PGRAPH_DEBUG_4); | ||
407 | dev_priv->fifos[channel].pgraph_ctx[2] = | ||
408 | nv_rd32(dev, 0x004006b0); | ||
409 | #endif | ||
410 | return 0; | 410 | return 0; |
411 | } | 411 | } |
412 | 412 | ||
@@ -429,9 +429,13 @@ int nv04_graph_load_context(struct nouveau_channel *chan) | |||
429 | nv_wr32(dev, nv04_graph_ctx_regs[i], pgraph_ctx->nv04[i]); | 429 | nv_wr32(dev, nv04_graph_ctx_regs[i], pgraph_ctx->nv04[i]); |
430 | 430 | ||
431 | nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10010100); | 431 | nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10010100); |
432 | nv_wr32(dev, NV04_PGRAPH_CTX_USER, chan->id << 24); | 432 | |
433 | tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff; | ||
434 | nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp | chan->id << 24); | ||
435 | |||
433 | tmp = nv_rd32(dev, NV04_PGRAPH_FFINTFC_ST2); | 436 | tmp = nv_rd32(dev, NV04_PGRAPH_FFINTFC_ST2); |
434 | nv_wr32(dev, NV04_PGRAPH_FFINTFC_ST2, tmp & 0x000fffff); | 437 | nv_wr32(dev, NV04_PGRAPH_FFINTFC_ST2, tmp & 0x000fffff); |
438 | |||
435 | return 0; | 439 | return 0; |
436 | } | 440 | } |
437 | 441 | ||
@@ -494,7 +498,7 @@ int nv04_graph_init(struct drm_device *dev) | |||
494 | nv_wr32(dev, NV04_PGRAPH_STATE , 0xFFFFFFFF); | 498 | nv_wr32(dev, NV04_PGRAPH_STATE , 0xFFFFFFFF); |
495 | nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL , 0x10000100); | 499 | nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL , 0x10000100); |
496 | tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff; | 500 | tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff; |
497 | tmp |= dev_priv->engine.fifo.channels << 24; | 501 | tmp |= (dev_priv->engine.fifo.channels - 1) << 24; |
498 | nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp); | 502 | nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp); |
499 | 503 | ||
500 | /* These don't belong here, they're part of a per-channel context */ | 504 | /* These don't belong here, they're part of a per-channel context */ |