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authorJerome Glisse <jglisse@redhat.com>2009-10-01 12:02:11 -0400
committerDave Airlie <airlied@redhat.com>2009-10-01 19:33:46 -0400
commit62a8ea3f7bb61e5f92db0a648b7cc566852c36ec (patch)
tree3ffefdbe940c66591dd4863ccf3a766498bf5100 /drivers/gpu
parentc010f8000a925e08d84d9391e13dd297b9fdc393 (diff)
drm/radeon/kms: Remove old init path as no hw use it anymore
This remove old init path and allow code cleanup, now all hw use the new init path, see top of radeon.h for description of this. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/r100.c1
-rw-r--r--drivers/gpu/drm/radeon/r300.c1
-rw-r--r--drivers/gpu/drm/radeon/r420.c1
-rw-r--r--drivers/gpu/drm/radeon/r520.c1
-rw-r--r--drivers/gpu/drm/radeon/r600.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon.h26
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h138
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c180
-rw-r--r--drivers/gpu/drm/radeon/rs400.c1
-rw-r--r--drivers/gpu/drm/radeon/rs600.c1
-rw-r--r--drivers/gpu/drm/radeon/rs690.c1
-rw-r--r--drivers/gpu/drm/radeon/rv515.c1
-rw-r--r--drivers/gpu/drm/radeon/rv770.c5
13 files changed, 7 insertions, 355 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 0a475617a70f..7bea923b1b29 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -3176,7 +3176,6 @@ int r100_init(struct radeon_device *rdev)
3176{ 3176{
3177 int r; 3177 int r;
3178 3178
3179 rdev->new_init_path = true;
3180 /* Register debugfs file specific to this group of asics */ 3179 /* Register debugfs file specific to this group of asics */
3181 r100_debugfs(rdev); 3180 r100_debugfs(rdev);
3182 /* Disable VGA */ 3181 /* Disable VGA */
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 18c81dc750bc..e08c4a8974ca 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -1275,7 +1275,6 @@ int r300_init(struct radeon_device *rdev)
1275{ 1275{
1276 int r; 1276 int r;
1277 1277
1278 rdev->new_init_path = true;
1279 /* Disable VGA */ 1278 /* Disable VGA */
1280 r100_vga_render_disable(rdev); 1279 r100_vga_render_disable(rdev);
1281 /* Initialize scratch registers */ 1280 /* Initialize scratch registers */
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index c5d3ba47f5df..5c7fe52de30e 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -272,7 +272,6 @@ int r420_init(struct radeon_device *rdev)
272{ 272{
273 int r; 273 int r;
274 274
275 rdev->new_init_path = true;
276 /* Initialize scratch registers */ 275 /* Initialize scratch registers */
277 radeon_scratch_init(rdev); 276 radeon_scratch_init(rdev);
278 /* Initialize surface registers */ 277 /* Initialize surface registers */
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index 0bf13fccdaf2..a58b6fa132eb 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -228,7 +228,6 @@ int r520_init(struct radeon_device *rdev)
228{ 228{
229 int r; 229 int r;
230 230
231 rdev->new_init_path = true;
232 /* Initialize scratch registers */ 231 /* Initialize scratch registers */
233 radeon_scratch_init(rdev); 232 radeon_scratch_init(rdev);
234 /* Initialize surface registers */ 233 /* Initialize surface registers */
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 6b7a40b501c0..17fff7b6e591 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1531,7 +1531,7 @@ int r600_resume(struct radeon_device *rdev)
1531 return r; 1531 return r;
1532 } 1532 }
1533 1533
1534 r = radeon_ib_test(rdev); 1534 r = r600_ib_test(rdev);
1535 if (r) { 1535 if (r) {
1536 DRM_ERROR("radeon: failled testing IB (%d).\n", r); 1536 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1537 return r; 1537 return r;
@@ -1562,7 +1562,6 @@ int r600_init(struct radeon_device *rdev)
1562{ 1562{
1563 int r; 1563 int r;
1564 1564
1565 rdev->new_init_path = true;
1566 r = radeon_dummy_page_init(rdev); 1565 r = radeon_dummy_page_init(rdev);
1567 if (r) 1566 if (r)
1568 return r; 1567 return r;
@@ -1653,7 +1652,7 @@ int r600_init(struct radeon_device *rdev)
1653 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); 1652 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
1654 rdev->accel_working = false; 1653 rdev->accel_working = false;
1655 } 1654 }
1656 r = radeon_ib_test(rdev); 1655 r = r600_ib_test(rdev);
1657 if (r) { 1656 if (r) {
1658 DRM_ERROR("radeon: failled testing IB (%d).\n", r); 1657 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1659 rdev->accel_working = false; 1658 rdev->accel_working = false;
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 2f084e1501d7..902791d2275d 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -590,17 +590,7 @@ struct radeon_asic {
590 void (*fini)(struct radeon_device *rdev); 590 void (*fini)(struct radeon_device *rdev);
591 int (*resume)(struct radeon_device *rdev); 591 int (*resume)(struct radeon_device *rdev);
592 int (*suspend)(struct radeon_device *rdev); 592 int (*suspend)(struct radeon_device *rdev);
593 void (*errata)(struct radeon_device *rdev);
594 void (*vram_info)(struct radeon_device *rdev);
595 int (*gpu_reset)(struct radeon_device *rdev); 593 int (*gpu_reset)(struct radeon_device *rdev);
596 int (*mc_init)(struct radeon_device *rdev);
597 void (*mc_fini)(struct radeon_device *rdev);
598 int (*wb_init)(struct radeon_device *rdev);
599 void (*wb_fini)(struct radeon_device *rdev);
600 int (*gart_init)(struct radeon_device *rdev);
601 void (*gart_fini)(struct radeon_device *rdev);
602 int (*gart_enable)(struct radeon_device *rdev);
603 void (*gart_disable)(struct radeon_device *rdev);
604 void (*gart_tlb_flush)(struct radeon_device *rdev); 594 void (*gart_tlb_flush)(struct radeon_device *rdev);
605 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); 595 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
606 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); 596 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
@@ -610,7 +600,6 @@ struct radeon_asic {
610 void (*ring_start)(struct radeon_device *rdev); 600 void (*ring_start)(struct radeon_device *rdev);
611 int (*ring_test)(struct radeon_device *rdev); 601 int (*ring_test)(struct radeon_device *rdev);
612 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 602 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
613 int (*ib_test)(struct radeon_device *rdev);
614 int (*irq_set)(struct radeon_device *rdev); 603 int (*irq_set)(struct radeon_device *rdev);
615 int (*irq_process)(struct radeon_device *rdev); 604 int (*irq_process)(struct radeon_device *rdev);
616 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 605 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
@@ -788,7 +777,6 @@ struct radeon_device {
788 bool shutdown; 777 bool shutdown;
789 bool suspend; 778 bool suspend;
790 bool need_dma32; 779 bool need_dma32;
791 bool new_init_path;
792 bool accel_working; 780 bool accel_working;
793 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 781 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
794 const struct firmware *me_fw; /* all family ME firmware */ 782 const struct firmware *me_fw; /* all family ME firmware */
@@ -948,27 +936,13 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
948#define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 936#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
949#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 937#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
950#define radeon_cs_parse(p) rdev->asic->cs_parse((p)) 938#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
951#define radeon_errata(rdev) (rdev)->asic->errata((rdev))
952#define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
953#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) 939#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
954#define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
955#define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
956#define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
957#define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
958#define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev))
959#define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev))
960#define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
961#define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
962#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) 940#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
963#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) 941#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
964#define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
965#define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
966#define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
967#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) 942#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
968#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) 943#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
969#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) 944#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
970#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) 945#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
971#define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev))
972#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) 946#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
973#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) 947#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
974#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) 948#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 7bc86a6aa5d6..d38f99632827 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -71,7 +71,6 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
71int r100_clear_surface_reg(struct radeon_device *rdev, int reg); 71int r100_clear_surface_reg(struct radeon_device *rdev, int reg);
72void r100_bandwidth_update(struct radeon_device *rdev); 72void r100_bandwidth_update(struct radeon_device *rdev);
73void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 73void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
74int r100_ib_test(struct radeon_device *rdev);
75int r100_ring_test(struct radeon_device *rdev); 74int r100_ring_test(struct radeon_device *rdev);
76 75
77static struct radeon_asic r100_asic = { 76static struct radeon_asic r100_asic = {
@@ -79,27 +78,13 @@ static struct radeon_asic r100_asic = {
79 .fini = &r100_fini, 78 .fini = &r100_fini,
80 .suspend = &r100_suspend, 79 .suspend = &r100_suspend,
81 .resume = &r100_resume, 80 .resume = &r100_resume,
82 .errata = NULL,
83 .vram_info = NULL,
84 .gpu_reset = &r100_gpu_reset, 81 .gpu_reset = &r100_gpu_reset,
85 .mc_init = NULL,
86 .mc_fini = NULL,
87 .wb_init = NULL,
88 .wb_fini = NULL,
89 .gart_init = NULL,
90 .gart_fini = NULL,
91 .gart_enable = NULL,
92 .gart_disable = NULL,
93 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 82 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
94 .gart_set_page = &r100_pci_gart_set_page, 83 .gart_set_page = &r100_pci_gart_set_page,
95 .cp_init = NULL,
96 .cp_fini = NULL,
97 .cp_disable = NULL,
98 .cp_commit = &r100_cp_commit, 84 .cp_commit = &r100_cp_commit,
99 .ring_start = &r100_ring_start, 85 .ring_start = &r100_ring_start,
100 .ring_test = &r100_ring_test, 86 .ring_test = &r100_ring_test,
101 .ring_ib_execute = &r100_ring_ib_execute, 87 .ring_ib_execute = &r100_ring_ib_execute,
102 .ib_test = NULL,
103 .irq_set = &r100_irq_set, 88 .irq_set = &r100_irq_set,
104 .irq_process = &r100_irq_process, 89 .irq_process = &r100_irq_process,
105 .get_vblank_counter = &r100_get_vblank_counter, 90 .get_vblank_counter = &r100_get_vblank_counter,
@@ -145,27 +130,13 @@ static struct radeon_asic r300_asic = {
145 .fini = &r300_fini, 130 .fini = &r300_fini,
146 .suspend = &r300_suspend, 131 .suspend = &r300_suspend,
147 .resume = &r300_resume, 132 .resume = &r300_resume,
148 .errata = NULL,
149 .vram_info = NULL,
150 .gpu_reset = &r300_gpu_reset, 133 .gpu_reset = &r300_gpu_reset,
151 .mc_init = NULL,
152 .mc_fini = NULL,
153 .wb_init = NULL,
154 .wb_fini = NULL,
155 .gart_init = NULL,
156 .gart_fini = NULL,
157 .gart_enable = NULL,
158 .gart_disable = NULL,
159 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 134 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
160 .gart_set_page = &r100_pci_gart_set_page, 135 .gart_set_page = &r100_pci_gart_set_page,
161 .cp_init = NULL,
162 .cp_fini = NULL,
163 .cp_disable = NULL,
164 .cp_commit = &r100_cp_commit, 136 .cp_commit = &r100_cp_commit,
165 .ring_start = &r300_ring_start, 137 .ring_start = &r300_ring_start,
166 .ring_test = &r100_ring_test, 138 .ring_test = &r100_ring_test,
167 .ring_ib_execute = &r100_ring_ib_execute, 139 .ring_ib_execute = &r100_ring_ib_execute,
168 .ib_test = NULL,
169 .irq_set = &r100_irq_set, 140 .irq_set = &r100_irq_set,
170 .irq_process = &r100_irq_process, 141 .irq_process = &r100_irq_process,
171 .get_vblank_counter = &r100_get_vblank_counter, 142 .get_vblank_counter = &r100_get_vblank_counter,
@@ -195,25 +166,13 @@ static struct radeon_asic r420_asic = {
195 .fini = &r420_fini, 166 .fini = &r420_fini,
196 .suspend = &r420_suspend, 167 .suspend = &r420_suspend,
197 .resume = &r420_resume, 168 .resume = &r420_resume,
198 .errata = NULL,
199 .vram_info = NULL,
200 .gpu_reset = &r300_gpu_reset, 169 .gpu_reset = &r300_gpu_reset,
201 .mc_init = NULL,
202 .mc_fini = NULL,
203 .wb_init = NULL,
204 .wb_fini = NULL,
205 .gart_enable = NULL,
206 .gart_disable = NULL,
207 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 170 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
208 .gart_set_page = &rv370_pcie_gart_set_page, 171 .gart_set_page = &rv370_pcie_gart_set_page,
209 .cp_init = NULL,
210 .cp_fini = NULL,
211 .cp_disable = NULL,
212 .cp_commit = &r100_cp_commit, 172 .cp_commit = &r100_cp_commit,
213 .ring_start = &r300_ring_start, 173 .ring_start = &r300_ring_start,
214 .ring_test = &r100_ring_test, 174 .ring_test = &r100_ring_test,
215 .ring_ib_execute = &r100_ring_ib_execute, 175 .ring_ib_execute = &r100_ring_ib_execute,
216 .ib_test = NULL,
217 .irq_set = &r100_irq_set, 176 .irq_set = &r100_irq_set,
218 .irq_process = &r100_irq_process, 177 .irq_process = &r100_irq_process,
219 .get_vblank_counter = &r100_get_vblank_counter, 178 .get_vblank_counter = &r100_get_vblank_counter,
@@ -248,27 +207,13 @@ static struct radeon_asic rs400_asic = {
248 .fini = &rs400_fini, 207 .fini = &rs400_fini,
249 .suspend = &rs400_suspend, 208 .suspend = &rs400_suspend,
250 .resume = &rs400_resume, 209 .resume = &rs400_resume,
251 .errata = NULL,
252 .vram_info = NULL,
253 .gpu_reset = &r300_gpu_reset, 210 .gpu_reset = &r300_gpu_reset,
254 .mc_init = NULL,
255 .mc_fini = NULL,
256 .wb_init = NULL,
257 .wb_fini = NULL,
258 .gart_init = NULL,
259 .gart_fini = NULL,
260 .gart_enable = NULL,
261 .gart_disable = NULL,
262 .gart_tlb_flush = &rs400_gart_tlb_flush, 211 .gart_tlb_flush = &rs400_gart_tlb_flush,
263 .gart_set_page = &rs400_gart_set_page, 212 .gart_set_page = &rs400_gart_set_page,
264 .cp_init = NULL,
265 .cp_fini = NULL,
266 .cp_disable = NULL,
267 .cp_commit = &r100_cp_commit, 213 .cp_commit = &r100_cp_commit,
268 .ring_start = &r300_ring_start, 214 .ring_start = &r300_ring_start,
269 .ring_test = &r100_ring_test, 215 .ring_test = &r100_ring_test,
270 .ring_ib_execute = &r100_ring_ib_execute, 216 .ring_ib_execute = &r100_ring_ib_execute,
271 .ib_test = NULL,
272 .irq_set = &r100_irq_set, 217 .irq_set = &r100_irq_set,
273 .irq_process = &r100_irq_process, 218 .irq_process = &r100_irq_process,
274 .get_vblank_counter = &r100_get_vblank_counter, 219 .get_vblank_counter = &r100_get_vblank_counter,
@@ -307,27 +252,13 @@ static struct radeon_asic rs600_asic = {
307 .fini = &rs600_fini, 252 .fini = &rs600_fini,
308 .suspend = &rs600_suspend, 253 .suspend = &rs600_suspend,
309 .resume = &rs600_resume, 254 .resume = &rs600_resume,
310 .errata = NULL,
311 .vram_info = NULL,
312 .gpu_reset = &r300_gpu_reset, 255 .gpu_reset = &r300_gpu_reset,
313 .mc_init = NULL,
314 .mc_fini = NULL,
315 .wb_init = NULL,
316 .wb_fini = NULL,
317 .gart_init = NULL,
318 .gart_fini = NULL,
319 .gart_enable = NULL,
320 .gart_disable = NULL,
321 .gart_tlb_flush = &rs600_gart_tlb_flush, 256 .gart_tlb_flush = &rs600_gart_tlb_flush,
322 .gart_set_page = &rs600_gart_set_page, 257 .gart_set_page = &rs600_gart_set_page,
323 .cp_init = NULL,
324 .cp_fini = NULL,
325 .cp_disable = NULL,
326 .cp_commit = &r100_cp_commit, 258 .cp_commit = &r100_cp_commit,
327 .ring_start = &r300_ring_start, 259 .ring_start = &r300_ring_start,
328 .ring_test = &r100_ring_test, 260 .ring_test = &r100_ring_test,
329 .ring_ib_execute = &r100_ring_ib_execute, 261 .ring_ib_execute = &r100_ring_ib_execute,
330 .ib_test = NULL,
331 .irq_set = &rs600_irq_set, 262 .irq_set = &rs600_irq_set,
332 .irq_process = &rs600_irq_process, 263 .irq_process = &rs600_irq_process,
333 .get_vblank_counter = &rs600_get_vblank_counter, 264 .get_vblank_counter = &rs600_get_vblank_counter,
@@ -359,27 +290,13 @@ static struct radeon_asic rs690_asic = {
359 .fini = &rs690_fini, 290 .fini = &rs690_fini,
360 .suspend = &rs690_suspend, 291 .suspend = &rs690_suspend,
361 .resume = &rs690_resume, 292 .resume = &rs690_resume,
362 .errata = NULL,
363 .vram_info = NULL,
364 .gpu_reset = &r300_gpu_reset, 293 .gpu_reset = &r300_gpu_reset,
365 .mc_init = NULL,
366 .mc_fini = NULL,
367 .wb_init = NULL,
368 .wb_fini = NULL,
369 .gart_init = NULL,
370 .gart_fini = NULL,
371 .gart_enable = NULL,
372 .gart_disable = NULL,
373 .gart_tlb_flush = &rs400_gart_tlb_flush, 294 .gart_tlb_flush = &rs400_gart_tlb_flush,
374 .gart_set_page = &rs400_gart_set_page, 295 .gart_set_page = &rs400_gart_set_page,
375 .cp_init = NULL,
376 .cp_fini = NULL,
377 .cp_disable = NULL,
378 .cp_commit = &r100_cp_commit, 296 .cp_commit = &r100_cp_commit,
379 .ring_start = &r300_ring_start, 297 .ring_start = &r300_ring_start,
380 .ring_test = &r100_ring_test, 298 .ring_test = &r100_ring_test,
381 .ring_ib_execute = &r100_ring_ib_execute, 299 .ring_ib_execute = &r100_ring_ib_execute,
382 .ib_test = NULL,
383 .irq_set = &rs600_irq_set, 300 .irq_set = &rs600_irq_set,
384 .irq_process = &rs600_irq_process, 301 .irq_process = &rs600_irq_process,
385 .get_vblank_counter = &rs600_get_vblank_counter, 302 .get_vblank_counter = &rs600_get_vblank_counter,
@@ -417,27 +334,13 @@ static struct radeon_asic rv515_asic = {
417 .fini = &rv515_fini, 334 .fini = &rv515_fini,
418 .suspend = &rv515_suspend, 335 .suspend = &rv515_suspend,
419 .resume = &rv515_resume, 336 .resume = &rv515_resume,
420 .errata = NULL,
421 .vram_info = NULL,
422 .gpu_reset = &rv515_gpu_reset, 337 .gpu_reset = &rv515_gpu_reset,
423 .mc_init = NULL,
424 .mc_fini = NULL,
425 .wb_init = NULL,
426 .wb_fini = NULL,
427 .gart_init = &rv370_pcie_gart_init,
428 .gart_fini = &rv370_pcie_gart_fini,
429 .gart_enable = NULL,
430 .gart_disable = NULL,
431 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 338 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
432 .gart_set_page = &rv370_pcie_gart_set_page, 339 .gart_set_page = &rv370_pcie_gart_set_page,
433 .cp_init = NULL,
434 .cp_fini = NULL,
435 .cp_disable = NULL,
436 .cp_commit = &r100_cp_commit, 340 .cp_commit = &r100_cp_commit,
437 .ring_start = &rv515_ring_start, 341 .ring_start = &rv515_ring_start,
438 .ring_test = &r100_ring_test, 342 .ring_test = &r100_ring_test,
439 .ring_ib_execute = &r100_ring_ib_execute, 343 .ring_ib_execute = &r100_ring_ib_execute,
440 .ib_test = NULL,
441 .irq_set = &rs600_irq_set, 344 .irq_set = &rs600_irq_set,
442 .irq_process = &rs600_irq_process, 345 .irq_process = &rs600_irq_process,
443 .get_vblank_counter = &rs600_get_vblank_counter, 346 .get_vblank_counter = &rs600_get_vblank_counter,
@@ -466,27 +369,13 @@ static struct radeon_asic r520_asic = {
466 .fini = &rv515_fini, 369 .fini = &rv515_fini,
467 .suspend = &rv515_suspend, 370 .suspend = &rv515_suspend,
468 .resume = &r520_resume, 371 .resume = &r520_resume,
469 .errata = NULL,
470 .vram_info = NULL,
471 .gpu_reset = &rv515_gpu_reset, 372 .gpu_reset = &rv515_gpu_reset,
472 .mc_init = NULL,
473 .mc_fini = NULL,
474 .wb_init = NULL,
475 .wb_fini = NULL,
476 .gart_init = NULL,
477 .gart_fini = NULL,
478 .gart_enable = NULL,
479 .gart_disable = NULL,
480 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 373 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
481 .gart_set_page = &rv370_pcie_gart_set_page, 374 .gart_set_page = &rv370_pcie_gart_set_page,
482 .cp_init = NULL,
483 .cp_fini = NULL,
484 .cp_disable = NULL,
485 .cp_commit = &r100_cp_commit, 375 .cp_commit = &r100_cp_commit,
486 .ring_start = &rv515_ring_start, 376 .ring_start = &rv515_ring_start,
487 .ring_test = &r100_ring_test, 377 .ring_test = &r100_ring_test,
488 .ring_ib_execute = &r100_ring_ib_execute, 378 .ring_ib_execute = &r100_ring_ib_execute,
489 .ib_test = NULL,
490 .irq_set = &rs600_irq_set, 379 .irq_set = &rs600_irq_set,
491 .irq_process = &rs600_irq_process, 380 .irq_process = &rs600_irq_process,
492 .get_vblank_counter = &rs600_get_vblank_counter, 381 .get_vblank_counter = &rs600_get_vblank_counter,
@@ -533,36 +422,22 @@ int r600_set_surface_reg(struct radeon_device *rdev, int reg,
533 uint32_t offset, uint32_t obj_size); 422 uint32_t offset, uint32_t obj_size);
534int r600_clear_surface_reg(struct radeon_device *rdev, int reg); 423int r600_clear_surface_reg(struct radeon_device *rdev, int reg);
535void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 424void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
536int r600_ib_test(struct radeon_device *rdev);
537int r600_ring_test(struct radeon_device *rdev); 425int r600_ring_test(struct radeon_device *rdev);
538int r600_copy_blit(struct radeon_device *rdev, 426int r600_copy_blit(struct radeon_device *rdev,
539 uint64_t src_offset, uint64_t dst_offset, 427 uint64_t src_offset, uint64_t dst_offset,
540 unsigned num_pages, struct radeon_fence *fence); 428 unsigned num_pages, struct radeon_fence *fence);
541 429
542static struct radeon_asic r600_asic = { 430static struct radeon_asic r600_asic = {
543 .errata = NULL,
544 .init = &r600_init, 431 .init = &r600_init,
545 .fini = &r600_fini, 432 .fini = &r600_fini,
546 .suspend = &r600_suspend, 433 .suspend = &r600_suspend,
547 .resume = &r600_resume, 434 .resume = &r600_resume,
548 .cp_commit = &r600_cp_commit, 435 .cp_commit = &r600_cp_commit,
549 .vram_info = NULL,
550 .gpu_reset = &r600_gpu_reset, 436 .gpu_reset = &r600_gpu_reset,
551 .mc_init = NULL,
552 .mc_fini = NULL,
553 .wb_init = &r600_wb_init,
554 .wb_fini = &r600_wb_fini,
555 .gart_enable = NULL,
556 .gart_disable = NULL,
557 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 437 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
558 .gart_set_page = &rs600_gart_set_page, 438 .gart_set_page = &rs600_gart_set_page,
559 .cp_init = NULL,
560 .cp_fini = NULL,
561 .cp_disable = NULL,
562 .ring_start = NULL,
563 .ring_test = &r600_ring_test, 439 .ring_test = &r600_ring_test,
564 .ring_ib_execute = &r600_ring_ib_execute, 440 .ring_ib_execute = &r600_ring_ib_execute,
565 .ib_test = &r600_ib_test,
566 .irq_set = &r600_irq_set, 441 .irq_set = &r600_irq_set,
567 .irq_process = &r600_irq_process, 442 .irq_process = &r600_irq_process,
568 .fence_ring_emit = &r600_fence_ring_emit, 443 .fence_ring_emit = &r600_fence_ring_emit,
@@ -589,29 +464,16 @@ int rv770_resume(struct radeon_device *rdev);
589int rv770_gpu_reset(struct radeon_device *rdev); 464int rv770_gpu_reset(struct radeon_device *rdev);
590 465
591static struct radeon_asic rv770_asic = { 466static struct radeon_asic rv770_asic = {
592 .errata = NULL,
593 .init = &rv770_init, 467 .init = &rv770_init,
594 .fini = &rv770_fini, 468 .fini = &rv770_fini,
595 .suspend = &rv770_suspend, 469 .suspend = &rv770_suspend,
596 .resume = &rv770_resume, 470 .resume = &rv770_resume,
597 .cp_commit = &r600_cp_commit, 471 .cp_commit = &r600_cp_commit,
598 .vram_info = NULL,
599 .gpu_reset = &rv770_gpu_reset, 472 .gpu_reset = &rv770_gpu_reset,
600 .mc_init = NULL,
601 .mc_fini = NULL,
602 .wb_init = &r600_wb_init,
603 .wb_fini = &r600_wb_fini,
604 .gart_enable = NULL,
605 .gart_disable = NULL,
606 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 473 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
607 .gart_set_page = &rs600_gart_set_page, 474 .gart_set_page = &rs600_gart_set_page,
608 .cp_init = NULL,
609 .cp_fini = NULL,
610 .cp_disable = NULL,
611 .ring_start = NULL,
612 .ring_test = &r600_ring_test, 475 .ring_test = &r600_ring_test,
613 .ring_ib_execute = &r600_ring_ib_execute, 476 .ring_ib_execute = &r600_ring_ib_execute,
614 .ib_test = &r600_ib_test,
615 .irq_set = &r600_irq_set, 477 .irq_set = &r600_irq_set,
616 .irq_process = &r600_irq_process, 478 .irq_process = &r600_irq_process,
617 .fence_ring_emit = &r600_fence_ring_emit, 479 .fence_ring_emit = &r600_fence_ring_emit,
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index a6733cff1fb8..2d07ccc03c43 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -321,10 +321,6 @@ int radeon_asic_init(struct radeon_device *rdev)
321 case CHIP_RV380: 321 case CHIP_RV380:
322 rdev->asic = &r300_asic; 322 rdev->asic = &r300_asic;
323 if (rdev->flags & RADEON_IS_PCIE) { 323 if (rdev->flags & RADEON_IS_PCIE) {
324 rdev->asic->gart_init = &rv370_pcie_gart_init;
325 rdev->asic->gart_fini = &rv370_pcie_gart_fini;
326 rdev->asic->gart_enable = &rv370_pcie_gart_enable;
327 rdev->asic->gart_disable = &rv370_pcie_gart_disable;
328 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; 324 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
329 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; 325 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
330 } 326 }
@@ -529,19 +525,11 @@ int radeon_device_init(struct radeon_device *rdev,
529 rdev->family == CHIP_R423) { 525 rdev->family == CHIP_R423) {
530 DRM_INFO("Forcing AGP to PCIE mode\n"); 526 DRM_INFO("Forcing AGP to PCIE mode\n");
531 rdev->flags |= RADEON_IS_PCIE; 527 rdev->flags |= RADEON_IS_PCIE;
532 rdev->asic->gart_init = &rv370_pcie_gart_init;
533 rdev->asic->gart_fini = &rv370_pcie_gart_fini;
534 rdev->asic->gart_enable = &rv370_pcie_gart_enable;
535 rdev->asic->gart_disable = &rv370_pcie_gart_disable;
536 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; 528 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
537 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; 529 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
538 } else { 530 } else {
539 DRM_INFO("Forcing AGP to PCI mode\n"); 531 DRM_INFO("Forcing AGP to PCI mode\n");
540 rdev->flags |= RADEON_IS_PCI; 532 rdev->flags |= RADEON_IS_PCI;
541 rdev->asic->gart_init = &r100_pci_gart_init;
542 rdev->asic->gart_fini = &r100_pci_gart_fini;
543 rdev->asic->gart_enable = &r100_pci_gart_enable;
544 rdev->asic->gart_disable = &r100_pci_gart_disable;
545 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; 533 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
546 rdev->asic->gart_set_page = &r100_pci_gart_set_page; 534 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
547 } 535 }
@@ -576,105 +564,10 @@ int radeon_device_init(struct radeon_device *rdev,
576 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); 564 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
577 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); 565 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
578 566
579 rdev->new_init_path = false;
580 r = radeon_init(rdev); 567 r = radeon_init(rdev);
581 if (r) { 568 if (r) {
582 return r; 569 return r;
583 } 570 }
584 if (!rdev->new_init_path) {
585 /* Setup errata flags */
586 radeon_errata(rdev);
587 /* Initialize scratch registers */
588 radeon_scratch_init(rdev);
589 /* Initialize surface registers */
590 radeon_surface_init(rdev);
591
592 /* TODO: disable VGA need to use VGA request */
593 /* BIOS*/
594 if (!radeon_get_bios(rdev)) {
595 if (ASIC_IS_AVIVO(rdev))
596 return -EINVAL;
597 }
598 if (rdev->is_atom_bios) {
599 r = radeon_atombios_init(rdev);
600 if (r) {
601 return r;
602 }
603 } else {
604 r = radeon_combios_init(rdev);
605 if (r) {
606 return r;
607 }
608 }
609 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
610 if (radeon_gpu_reset(rdev)) {
611 /* FIXME: what do we want to do here ? */
612 }
613 /* check if cards are posted or not */
614 if (!radeon_card_posted(rdev) && rdev->bios) {
615 DRM_INFO("GPU not posted. posting now...\n");
616 if (rdev->is_atom_bios) {
617 atom_asic_init(rdev->mode_info.atom_context);
618 } else {
619 radeon_combios_asic_init(rdev->ddev);
620 }
621 }
622 /* Get clock & vram information */
623 radeon_get_clock_info(rdev->ddev);
624 radeon_vram_info(rdev);
625 /* Initialize clocks */
626 r = radeon_clocks_init(rdev);
627 if (r) {
628 return r;
629 }
630
631 /* Initialize memory controller (also test AGP) */
632 r = radeon_mc_init(rdev);
633 if (r) {
634 return r;
635 }
636 /* Fence driver */
637 r = radeon_fence_driver_init(rdev);
638 if (r) {
639 return r;
640 }
641 r = radeon_irq_kms_init(rdev);
642 if (r) {
643 return r;
644 }
645 /* Memory manager */
646 r = radeon_object_init(rdev);
647 if (r) {
648 return r;
649 }
650 r = radeon_gpu_gart_init(rdev);
651 if (r)
652 return r;
653 /* Initialize GART (initialize after TTM so we can allocate
654 * memory through TTM but finalize after TTM) */
655 r = radeon_gart_enable(rdev);
656 if (r)
657 return 0;
658 r = radeon_gem_init(rdev);
659 if (r)
660 return 0;
661
662 /* 1M ring buffer */
663 r = radeon_cp_init(rdev, 1024 * 1024);
664 if (r)
665 return 0;
666 r = radeon_wb_init(rdev);
667 if (r)
668 DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
669 r = radeon_ib_pool_init(rdev);
670 if (r)
671 return 0;
672 r = radeon_ib_test(rdev);
673 if (r)
674 return 0;
675 rdev->accel_working = true;
676 }
677 DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
678 if (radeon_testing) { 571 if (radeon_testing) {
679 radeon_test_moves(rdev); 572 radeon_test_moves(rdev);
680 } 573 }
@@ -689,30 +582,7 @@ void radeon_device_fini(struct radeon_device *rdev)
689 DRM_INFO("radeon: finishing device.\n"); 582 DRM_INFO("radeon: finishing device.\n");
690 rdev->shutdown = true; 583 rdev->shutdown = true;
691 /* Order matter so becarefull if you rearrange anythings */ 584 /* Order matter so becarefull if you rearrange anythings */
692 if (!rdev->new_init_path) { 585 radeon_fini(rdev);
693 radeon_ib_pool_fini(rdev);
694 radeon_cp_fini(rdev);
695 radeon_wb_fini(rdev);
696 radeon_gpu_gart_fini(rdev);
697 radeon_gem_fini(rdev);
698 radeon_mc_fini(rdev);
699#if __OS_HAS_AGP
700 radeon_agp_fini(rdev);
701#endif
702 radeon_irq_kms_fini(rdev);
703 radeon_fence_driver_fini(rdev);
704 radeon_clocks_fini(rdev);
705 radeon_object_fini(rdev);
706 if (rdev->is_atom_bios) {
707 radeon_atombios_fini(rdev);
708 } else {
709 radeon_combios_fini(rdev);
710 }
711 kfree(rdev->bios);
712 rdev->bios = NULL;
713 } else {
714 radeon_fini(rdev);
715 }
716 iounmap(rdev->rmmio); 586 iounmap(rdev->rmmio);
717 rdev->rmmio = NULL; 587 rdev->rmmio = NULL;
718} 588}
@@ -752,14 +622,7 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
752 622
753 radeon_save_bios_scratch_regs(rdev); 623 radeon_save_bios_scratch_regs(rdev);
754 624
755 if (!rdev->new_init_path) { 625 radeon_suspend(rdev);
756 radeon_cp_disable(rdev);
757 radeon_gart_disable(rdev);
758 rdev->irq.sw_int = false;
759 radeon_irq_set(rdev);
760 } else {
761 radeon_suspend(rdev);
762 }
763 /* evict remaining vram memory */ 626 /* evict remaining vram memory */
764 radeon_object_evict_vram(rdev); 627 radeon_object_evict_vram(rdev);
765 628
@@ -778,7 +641,6 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
778int radeon_resume_kms(struct drm_device *dev) 641int radeon_resume_kms(struct drm_device *dev)
779{ 642{
780 struct radeon_device *rdev = dev->dev_private; 643 struct radeon_device *rdev = dev->dev_private;
781 int r;
782 644
783 acquire_console_sem(); 645 acquire_console_sem();
784 pci_set_power_state(dev->pdev, PCI_D0); 646 pci_set_power_state(dev->pdev, PCI_D0);
@@ -788,43 +650,7 @@ int radeon_resume_kms(struct drm_device *dev)
788 return -1; 650 return -1;
789 } 651 }
790 pci_set_master(dev->pdev); 652 pci_set_master(dev->pdev);
791 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 653 radeon_resume(rdev);
792 if (!rdev->new_init_path) {
793 if (radeon_gpu_reset(rdev)) {
794 /* FIXME: what do we want to do here ? */
795 }
796 /* post card */
797 if (rdev->is_atom_bios) {
798 atom_asic_init(rdev->mode_info.atom_context);
799 } else {
800 radeon_combios_asic_init(rdev->ddev);
801 }
802 /* Initialize clocks */
803 r = radeon_clocks_init(rdev);
804 if (r) {
805 release_console_sem();
806 return r;
807 }
808 /* Enable IRQ */
809 rdev->irq.sw_int = true;
810 radeon_irq_set(rdev);
811 /* Initialize GPU Memory Controller */
812 r = radeon_mc_init(rdev);
813 if (r) {
814 goto out;
815 }
816 r = radeon_gart_enable(rdev);
817 if (r) {
818 goto out;
819 }
820 r = radeon_cp_init(rdev, rdev->cp.ring_size);
821 if (r) {
822 goto out;
823 }
824 } else {
825 radeon_resume(rdev);
826 }
827out:
828 radeon_restore_bios_scratch_regs(rdev); 654 radeon_restore_bios_scratch_regs(rdev);
829 fb_set_suspend(rdev->fbdev_info, 0); 655 fb_set_suspend(rdev->fbdev_info, 0);
830 release_console_sem(); 656 release_console_sem();
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index 8b67605dbf3d..a769c296f6a6 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -460,7 +460,6 @@ int rs400_init(struct radeon_device *rdev)
460{ 460{
461 int r; 461 int r;
462 462
463 rdev->new_init_path = true;
464 /* Disable VGA */ 463 /* Disable VGA */
465 r100_vga_render_disable(rdev); 464 r100_vga_render_disable(rdev);
466 /* Initialize scratch registers */ 465 /* Initialize scratch registers */
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 9e4fdc173557..fbe0b87c4794 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -428,7 +428,6 @@ int rs600_init(struct radeon_device *rdev)
428{ 428{
429 int r; 429 int r;
430 430
431 rdev->new_init_path = true;
432 /* Disable VGA */ 431 /* Disable VGA */
433 rv515_vga_render_disable(rdev); 432 rv515_vga_render_disable(rdev);
434 /* Initialize scratch registers */ 433 /* Initialize scratch registers */
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 0028db51ae75..c3cd2f689ef0 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -672,7 +672,6 @@ int rs690_init(struct radeon_device *rdev)
672{ 672{
673 int r; 673 int r;
674 674
675 rdev->new_init_path = true;
676 /* Disable VGA */ 675 /* Disable VGA */
677 rv515_vga_render_disable(rdev); 676 rv515_vga_render_disable(rdev);
678 /* Initialize scratch registers */ 677 /* Initialize scratch registers */
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index e53b5ca7a253..07e50ac62a33 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -553,7 +553,6 @@ int rv515_init(struct radeon_device *rdev)
553{ 553{
554 int r; 554 int r;
555 555
556 rdev->new_init_path = true;
557 /* Initialize scratch registers */ 556 /* Initialize scratch registers */
558 radeon_scratch_init(rdev); 557 radeon_scratch_init(rdev);
559 /* Initialize surface registers */ 558 /* Initialize surface registers */
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index e0b97d161397..867d04bc4d39 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -915,7 +915,7 @@ int rv770_resume(struct radeon_device *rdev)
915 return r; 915 return r;
916 } 916 }
917 917
918 r = radeon_ib_test(rdev); 918 r = r600_ib_test(rdev);
919 if (r) { 919 if (r) {
920 DRM_ERROR("radeon: failled testing IB (%d).\n", r); 920 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
921 return r; 921 return r;
@@ -946,7 +946,6 @@ int rv770_init(struct radeon_device *rdev)
946{ 946{
947 int r; 947 int r;
948 948
949 rdev->new_init_path = true;
950 r = radeon_dummy_page_init(rdev); 949 r = radeon_dummy_page_init(rdev);
951 if (r) 950 if (r)
952 return r; 951 return r;
@@ -1034,7 +1033,7 @@ int rv770_init(struct radeon_device *rdev)
1034 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); 1033 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
1035 rdev->accel_working = false; 1034 rdev->accel_working = false;
1036 } 1035 }
1037 r = radeon_ib_test(rdev); 1036 r = r600_ib_test(rdev);
1038 if (r) { 1037 if (r) {
1039 DRM_ERROR("radeon: failled testing IB (%d).\n", r); 1038 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1040 rdev->accel_working = false; 1039 rdev->accel_working = false;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-01 14:56:09 -0500