diff options
author | Andrew Lutomirski <luto@mit.edu> | 2009-11-08 13:49:51 -0500 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2009-12-08 09:32:51 -0500 |
commit | 7e8b60faea972604c315634cff62d44803731ea9 (patch) | |
tree | a9c6fb0426fd6eac03e974b4c3242218d5996f80 /drivers/gpu | |
parent | 5618ca6abc2d6f475b258badc017a5254cf43d1b (diff) |
drm/i915: restore render clock gating on resume
Rather than restoring just a few clock gating registers on resume,
just reinitialize the whole thing.
Signed-off-by: Andy Lutomirski <luto@mit.edu>
[anholt: Fixed up for RC6 support landed since the patch was written]
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_suspend.c | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 35 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_drv.h | 1 |
4 files changed, 22 insertions, 23 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e28d6c9a0ae9..1d6171087298 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -381,8 +381,6 @@ typedef struct drm_i915_private { | |||
381 | u32 saveFDI_RXA_IMR; | 381 | u32 saveFDI_RXA_IMR; |
382 | u32 saveFDI_RXB_IMR; | 382 | u32 saveFDI_RXB_IMR; |
383 | u32 saveCACHE_MODE_0; | 383 | u32 saveCACHE_MODE_0; |
384 | u32 saveD_STATE; | ||
385 | u32 saveDSPCLK_GATE_D; | ||
386 | u32 saveMI_ARB_STATE; | 384 | u32 saveMI_ARB_STATE; |
387 | u32 saveSWF0[16]; | 385 | u32 saveSWF0[16]; |
388 | u32 saveSWF1[16]; | 386 | u32 saveSWF1[16]; |
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 402a7eb2922c..00f6d97c7cc5 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c | |||
@@ -722,10 +722,6 @@ int i915_save_state(struct drm_device *dev) | |||
722 | dev_priv->saveIMR = I915_READ(IMR); | 722 | dev_priv->saveIMR = I915_READ(IMR); |
723 | } | 723 | } |
724 | 724 | ||
725 | /* Clock gating state */ | ||
726 | dev_priv->saveD_STATE = I915_READ(D_STATE); | ||
727 | dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); /* Not sure about this */ | ||
728 | |||
729 | /* Cache mode state */ | 725 | /* Cache mode state */ |
730 | dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); | 726 | dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); |
731 | 727 | ||
@@ -800,8 +796,7 @@ int i915_restore_state(struct drm_device *dev) | |||
800 | } | 796 | } |
801 | 797 | ||
802 | /* Clock gating state */ | 798 | /* Clock gating state */ |
803 | I915_WRITE (D_STATE, dev_priv->saveD_STATE); | 799 | intel_init_clock_gating(dev); |
804 | I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D); | ||
805 | 800 | ||
806 | /* Cache mode state */ | 801 | /* Cache mode state */ |
807 | I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); | 802 | I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 902cc5386f19..279dc96e3eb2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -4584,28 +4584,33 @@ void intel_init_clock_gating(struct drm_device *dev) | |||
4584 | struct drm_i915_gem_object *obj_priv; | 4584 | struct drm_i915_gem_object *obj_priv; |
4585 | int ret; | 4585 | int ret; |
4586 | 4586 | ||
4587 | pwrctx = drm_gem_object_alloc(dev, 4096); | 4587 | if (dev_priv->pwrctx) { |
4588 | if (!pwrctx) { | 4588 | obj_priv = dev_priv->pwrctx->driver_private; |
4589 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); | 4589 | } else { |
4590 | goto out; | 4590 | pwrctx = drm_gem_object_alloc(dev, 4096); |
4591 | } | 4591 | if (!pwrctx) { |
4592 | DRM_DEBUG("failed to alloc power context, " | ||
4593 | "RC6 disabled\n"); | ||
4594 | goto out; | ||
4595 | } | ||
4592 | 4596 | ||
4593 | ret = i915_gem_object_pin(pwrctx, 4096); | 4597 | ret = i915_gem_object_pin(pwrctx, 4096); |
4594 | if (ret) { | 4598 | if (ret) { |
4595 | DRM_ERROR("failed to pin power context: %d\n", ret); | 4599 | DRM_ERROR("failed to pin power context: %d\n", |
4596 | drm_gem_object_unreference(pwrctx); | 4600 | ret); |
4597 | goto out; | 4601 | drm_gem_object_unreference(pwrctx); |
4598 | } | 4602 | goto out; |
4603 | } | ||
4599 | 4604 | ||
4600 | i915_gem_object_set_to_gtt_domain(pwrctx, 1); | 4605 | i915_gem_object_set_to_gtt_domain(pwrctx, 1); |
4601 | 4606 | ||
4602 | obj_priv = pwrctx->driver_private; | 4607 | dev_priv->pwrctx = pwrctx; |
4608 | obj_priv = pwrctx->driver_private; | ||
4609 | } | ||
4603 | 4610 | ||
4604 | I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN); | 4611 | I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN); |
4605 | I915_WRITE(MCHBAR_RENDER_STANDBY, | 4612 | I915_WRITE(MCHBAR_RENDER_STANDBY, |
4606 | I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT); | 4613 | I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT); |
4607 | |||
4608 | dev_priv->pwrctx = pwrctx; | ||
4609 | } | 4614 | } |
4610 | 4615 | ||
4611 | out: | 4616 | out: |
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 9ffa31e13eb3..a51573da1ff6 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h | |||
@@ -208,6 +208,7 @@ extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |||
208 | u16 blue, int regno); | 208 | u16 blue, int regno); |
209 | extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, | 209 | extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
210 | u16 *blue, int regno); | 210 | u16 *blue, int regno); |
211 | extern void intel_init_clock_gating(struct drm_device *dev); | ||
211 | 212 | ||
212 | extern int intel_framebuffer_create(struct drm_device *dev, | 213 | extern int intel_framebuffer_create(struct drm_device *dev, |
213 | struct drm_mode_fb_cmd *mode_cmd, | 214 | struct drm_mode_fb_cmd *mode_cmd, |