diff options
author | Zhenyu Wang <zhenyu.z.wang@intel.com> | 2009-03-24 02:02:41 -0400 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2009-04-01 18:22:03 -0400 |
commit | 171a9e960ec820765e3b8e9dd1e3d8d81233d459 (patch) | |
tree | fdb5606e8842639d40426731802ec74dcbeb4ef1 /drivers/gpu | |
parent | 33b5296120da157c90f40fab0ae498799ee29ca1 (diff) |
drm/i915: Fix error in SDVO DTD and modeline convert
This brings fix commit 62c0c2f5549a from 2D driver.
Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/i915/intel_sdvo.c | 25 |
1 files changed, 4 insertions, 21 deletions
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index fbf18cbd2d82..31cd9b835aa4 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c | |||
@@ -684,7 +684,7 @@ static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, | |||
684 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | | 684 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | |
685 | ((v_blank_len >> 8) & 0xf); | 685 | ((v_blank_len >> 8) & 0xf); |
686 | 686 | ||
687 | dtd->part2.h_sync_off = h_sync_offset; | 687 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
688 | dtd->part2.h_sync_width = h_sync_len & 0xff; | 688 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
689 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | | 689 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | |
690 | (v_sync_len & 0xf); | 690 | (v_sync_len & 0xf); |
@@ -706,27 +706,10 @@ static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, | |||
706 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, | 706 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, |
707 | struct intel_sdvo_dtd *dtd) | 707 | struct intel_sdvo_dtd *dtd) |
708 | { | 708 | { |
709 | uint16_t width, height; | ||
710 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; | ||
711 | uint16_t h_sync_offset, v_sync_offset; | ||
712 | |||
713 | width = mode->crtc_hdisplay; | ||
714 | height = mode->crtc_vdisplay; | ||
715 | |||
716 | /* do some mode translations */ | ||
717 | h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start; | ||
718 | h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; | ||
719 | |||
720 | v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start; | ||
721 | v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; | ||
722 | |||
723 | h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start; | ||
724 | v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start; | ||
725 | |||
726 | mode->hdisplay = dtd->part1.h_active; | 709 | mode->hdisplay = dtd->part1.h_active; |
727 | mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; | 710 | mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; |
728 | mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off; | 711 | mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off; |
729 | mode->hsync_start += (dtd->part2.sync_off_width_high & 0xa0) << 2; | 712 | mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; |
730 | mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; | 713 | mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; |
731 | mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; | 714 | mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; |
732 | mode->htotal = mode->hdisplay + dtd->part1.h_blank; | 715 | mode->htotal = mode->hdisplay + dtd->part1.h_blank; |
@@ -736,7 +719,7 @@ static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, | |||
736 | mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; | 719 | mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; |
737 | mode->vsync_start = mode->vdisplay; | 720 | mode->vsync_start = mode->vdisplay; |
738 | mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; | 721 | mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; |
739 | mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0a) << 2; | 722 | mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; |
740 | mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0; | 723 | mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0; |
741 | mode->vsync_end = mode->vsync_start + | 724 | mode->vsync_end = mode->vsync_start + |
742 | (dtd->part2.v_sync_off_width & 0xf); | 725 | (dtd->part2.v_sync_off_width & 0xf); |
@@ -746,7 +729,7 @@ static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, | |||
746 | 729 | ||
747 | mode->clock = dtd->part1.clock * 10; | 730 | mode->clock = dtd->part1.clock * 10; |
748 | 731 | ||
749 | mode->flags &= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); | 732 | mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); |
750 | if (dtd->part2.dtd_flags & 0x2) | 733 | if (dtd->part2.dtd_flags & 0x2) |
751 | mode->flags |= DRM_MODE_FLAG_PHSYNC; | 734 | mode->flags |= DRM_MODE_FLAG_PHSYNC; |
752 | if (dtd->part2.dtd_flags & 0x4) | 735 | if (dtd->part2.dtd_flags & 0x4) |