drm/i915: pch_irq_handler -> {ibx, cpt}_irq_handler

Cougar/Panther Point redefine the bits in SDEIIR pretty completely.
This function is just debugging, but if we're debugging we probably want
to be told accurate things instead of lies.

I'm told Lynx Point changes this yet more, but I have no idea how...

Note from Eugeni's review:

"For the record and for future enabling efforts, for LPT, bits 28-31
and 1-14 are gone since CPT/PPT (e.g., those must be zero). And there
is the bit 15 as a new addition, but we are not using it yet and
probably won't be using in foreseeable future."

Signed-off-by: Adam Jackson <ajax@redhat.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35103
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2 files changed, 67 insertions, 6 deletions

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1417660a93ec..b1fe0edda955 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -510,7 +510,7 @@ out:
         return ret;
 }
 
-static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
+static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
 {
         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
         int pipe;
@@ -550,6 +550,35 @@ static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 }
 
+static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
+{
+        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+        int pipe;
+
+        if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
+                DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
+                                 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
+                                 SDE_AUDIO_POWER_SHIFT_CPT);
+
+        if (pch_iir & SDE_AUX_MASK_CPT)
+                DRM_DEBUG_DRIVER("AUX channel interrupt\n");
+
+        if (pch_iir & SDE_GMBUS_CPT)
+                DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
+
+        if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
+                DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
+
+        if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
+                DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
+
+        if (pch_iir & SDE_FDI_MASK_CPT)
+                for_each_pipe(pipe)
+                        DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
+                                         pipe_name(pipe),
+                                         I915_READ(FDI_RX_IIR(pipe)));
+}
+
 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
 {
         struct drm_device *dev = (struct drm_device *) arg;
@@ -591,7 +620,7 @@ static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
 
                         if (pch_iir & SDE_HOTPLUG_MASK_CPT)
                                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
-                        pch_irq_handler(dev, pch_iir);
+                        cpt_irq_handler(dev, pch_iir);
 
                         /* clear PCH hotplug event before clear CPU irq */
                         I915_WRITE(SDEIIR, pch_iir);
@@ -684,7 +713,10 @@ static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
         if (de_iir & DE_PCH_EVENT) {
                 if (pch_iir & hotplug_mask)
                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
-                pch_irq_handler(dev, pch_iir);
+                if (HAS_PCH_CPT(dev))
+                        cpt_irq_handler(dev, pch_iir);
+                else
+                        ibx_irq_handler(dev, pch_iir);
         }
 
         if (de_iir & DE_PCU_EVENT) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 76bc2756d7c4..48d5e8e051cf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3321,7 +3321,7 @@
 
 /* PCH */
 
-/* south display engine interrupt */
+/* south display engine interrupt: IBX */
 #define SDE_AUDIO_POWER_D       (1 << 27)
 #define SDE_AUDIO_POWER_C       (1 << 26)
 #define SDE_AUDIO_POWER_B       (1 << 25)
@@ -3357,15 +3357,44 @@
 #define SDE_TRANSA_CRC_ERR      (1 << 1)
 #define SDE_TRANSA_FIFO_UNDER   (1 << 0)
 #define SDE_TRANS_MASK          (0x3f)
-/* CPT */
-#define SDE_CRT_HOTPLUG_CPT     (1 << 19)
+
+/* south display engine interrupt: CPT/PPT */
+#define SDE_AUDIO_POWER_D_CPT   (1 << 31)
+#define SDE_AUDIO_POWER_C_CPT   (1 << 30)
+#define SDE_AUDIO_POWER_B_CPT   (1 << 29)
+#define SDE_AUDIO_POWER_SHIFT_CPT   29
+#define SDE_AUDIO_POWER_MASK_CPT    (7 << 29)
+#define SDE_AUXD_CPT            (1 << 27)
+#define SDE_AUXC_CPT            (1 << 26)
+#define SDE_AUXB_CPT            (1 << 25)
+#define SDE_AUX_MASK_CPT        (7 << 25)
 #define SDE_PORTD_HOTPLUG_CPT   (1 << 23)
 #define SDE_PORTC_HOTPLUG_CPT   (1 << 22)
 #define SDE_PORTB_HOTPLUG_CPT   (1 << 21)
+#define SDE_CRT_HOTPLUG_CPT     (1 << 19)
 #define SDE_HOTPLUG_MASK_CPT    (SDE_CRT_HOTPLUG_CPT |          \
                                  SDE_PORTD_HOTPLUG_CPT |        \
                                  SDE_PORTC_HOTPLUG_CPT |        \
                                  SDE_PORTB_HOTPLUG_CPT)
+#define SDE_GMBUS_CPT           (1 << 17)
+#define SDE_AUDIO_CP_REQ_C_CPT  (1 << 10)
+#define SDE_AUDIO_CP_CHG_C_CPT  (1 << 9)
+#define SDE_FDI_RXC_CPT         (1 << 8)
+#define SDE_AUDIO_CP_REQ_B_CPT  (1 << 6)
+#define SDE_AUDIO_CP_CHG_B_CPT  (1 << 5)
+#define SDE_FDI_RXB_CPT         (1 << 4)
+#define SDE_AUDIO_CP_REQ_A_CPT  (1 << 2)
+#define SDE_AUDIO_CP_CHG_A_CPT  (1 << 1)
+#define SDE_FDI_RXA_CPT         (1 << 0)
+#define SDE_AUDIO_CP_REQ_CPT    (SDE_AUDIO_CP_REQ_C_CPT | \
+                                 SDE_AUDIO_CP_REQ_B_CPT | \
+                                 SDE_AUDIO_CP_REQ_A_CPT)
+#define SDE_AUDIO_CP_CHG_CPT    (SDE_AUDIO_CP_CHG_C_CPT | \
+                                 SDE_AUDIO_CP_CHG_B_CPT | \
+                                 SDE_AUDIO_CP_CHG_A_CPT)
+#define SDE_FDI_MASK_CPT        (SDE_FDI_RXC_CPT | \
+                                 SDE_FDI_RXB_CPT | \
+                                 SDE_FDI_RXA_CPT)
 
 #define SDEISR  0xc4000
 #define SDEIMR  0xc4004