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authorBen Skeggs <bskeggs@redhat.com>2013-07-03 23:49:47 -0400
committerBen Skeggs <bskeggs@redhat.com>2013-07-04 23:44:25 -0400
commitf8adeb82a931c780900f8133aeeea6f0b5154573 (patch)
treede5e5110dfa407d89c25e518a9deb5b63962e5d7 /drivers/gpu
parent8f6fe26745d39299d43d79dd7ba9838517624c3f (diff)
drm/nvc0-/gr: remove hardcoding of UNK count/mask in GPCCS ucode
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc29
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h65
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h65
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h65
4 files changed, 129 insertions, 95 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
index 32832720e420..b9dba107e78f 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
@@ -42,8 +42,8 @@ tpc_count: .b32 0
42tpc_mask: .b32 0 42tpc_mask: .b32 0
43 43
44#if NV_PGRAPH_GPCX_UNK__SIZE > 0 44#if NV_PGRAPH_GPCX_UNK__SIZE > 0
45unk_count: .b32 1 45unk_count: .b32 0
46unk_mask: .b32 1 46unk_mask: .b32 0
47#endif 47#endif
48 48
49cmd_queue: queue_init 49cmd_queue: queue_init
@@ -115,6 +115,31 @@ init:
115 iord $r2 I[$r1 + 0x000] // MYINDEX 115 iord $r2 I[$r1 + 0x000] // MYINDEX
116 st b32 D[$r0 + #gpc_id] $r2 116 st b32 D[$r0 + #gpc_id] $r2
117 117
118#if NV_PGRAPH_GPCX_UNK__SIZE > 0
119 // figure out which, and how many, UNKs are actually present
120 mov $r14 0x0c30
121 sethi $r14 0x500000
122 clear b32 $r2
123 clear b32 $r3
124 clear b32 $r4
125 init_unk_loop:
126 call #nv_rd32
127 cmp b32 $r15 0
128 bra z #init_unk_next
129 mov $r15 1
130 shl b32 $r15 $r2
131 or $r4 $r15
132 add b32 $r3 1
133 init_unk_next:
134 add b32 $r2 1
135 add b32 $r14 4
136 cmp b32 $r2 NV_PGRAPH_GPCX_UNK__SIZE
137 bra ne #init_unk_loop
138 init_unk_done:
139 st b32 D[$r0 + #unk_count] $r3
140 st b32 D[$r0 + #unk_mask] $r4
141#endif
142
118 // initialise context base, and size tracking 143 // initialise context base, and size tracking
119 mov $r2 0x800 144 mov $r2 0x800
120 shl b32 $r2 6 145 shl b32 $r2 6
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h
index 95d13a1dbb0a..66d034faedd3 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h
@@ -16,9 +16,9 @@ uint32_t nvd7_grgpc_data[] = {
16/* 0x0018: tpc_mask */ 16/* 0x0018: tpc_mask */
17 0x00000000, 17 0x00000000,
18/* 0x001c: unk_count */ 18/* 0x001c: unk_count */
19 0x00000001, 19 0x00000000,
20/* 0x0020: unk_mask */ 20/* 0x0020: unk_mask */
21 0x00000001, 21 0x00000000,
22/* 0x0024: cmd_queue */ 22/* 0x0024: cmd_queue */
23 0x00000000, 23 0x00000000,
24 0x00000000, 24 0x00000000,
@@ -271,7 +271,7 @@ uint32_t nvd7_grgpc_code[] = {
271 0xf10004fe, 271 0xf10004fe,
272 0xf0120017, 272 0xf0120017,
273 0x12d00227, 273 0x12d00227,
274 0x2317f100, 274 0x5717f100,
275 0x0010fe04, 275 0x0010fe04,
276 0x040017f1, 276 0x040017f1,
277 0xf0c010d0, 277 0xf0c010d0,
@@ -286,7 +286,23 @@ uint32_t nvd7_grgpc_code[] = {
286 0x06038005, 286 0x06038005,
287 0x040010b7, 287 0x040010b7,
288 0x800012cf, 288 0x800012cf,
289 0x27f10402, 289 0xe7f10402,
290 0xe3f00c30,
291 0xbd24bd50,
292/* 0x035f: init_unk_loop */
293 0xf444bd34,
294 0xf6b06821,
295 0x0f0bf400,
296 0xbb01f7f0,
297 0x4ffd04f2,
298 0x0130b605,
299/* 0x0374: init_unk_next */
300 0xb60120b6,
301 0x26b004e0,
302 0xe21bf401,
303/* 0x0380: init_unk_done */
304 0x80070380,
305 0x27f10804,
290 0x24b60800, 306 0x24b60800,
291 0x4022cf06, 307 0x4022cf06,
292 0x47f134bd, 308 0x47f134bd,
@@ -323,7 +339,7 @@ uint32_t nvd7_grgpc_code[] = {
323 0x10b74013, 339 0x10b74013,
324 0x24bd0800, 340 0x24bd0800,
325 0xd01f29f0, 341 0xd01f29f0,
326/* 0x03e6: main */ 342/* 0x041a: main */
327 0x31f40012, 343 0x31f40012,
328 0x0028f400, 344 0x0028f400,
329 0xf424d7f0, 345 0xf424d7f0,
@@ -335,12 +351,12 @@ uint32_t nvd7_grgpc_code[] = {
335 0xe4b60412, 351 0xe4b60412,
336 0x051efd01, 352 0x051efd01,
337 0xf50018fe, 353 0xf50018fe,
338 0xf404a821, 354 0xf404dc21,
339/* 0x0416: main_not_ctx_xfer */ 355/* 0x044a: main_not_ctx_xfer */
340 0xef94d30e, 356 0xef94d30e,
341 0x01f5f010, 357 0x01f5f010,
342 0x02ec21f5, 358 0x02ec21f5,
343/* 0x0423: ih */ 359/* 0x0457: ih */
344 0xf9c60ef4, 360 0xf9c60ef4,
345 0x0188fe80, 361 0x0188fe80,
346 0x90f980f9, 362 0x90f980f9,
@@ -355,7 +371,7 @@ uint32_t nvd7_grgpc_code[] = {
355 0xb70421f4, 371 0xb70421f4,
356 0xf00400b0, 372 0xf00400b0,
357 0xbed001e7, 373 0xbed001e7,
358/* 0x0459: ih_no_fifo */ 374/* 0x048d: ih_no_fifo */
359 0x400ad000, 375 0x400ad000,
360 0xe0fcf0fc, 376 0xe0fcf0fc,
361 0xb0fcd0fc, 377 0xb0fcd0fc,
@@ -363,28 +379,28 @@ uint32_t nvd7_grgpc_code[] = {
363 0x88fe80fc, 379 0x88fe80fc,
364 0xf480fc00, 380 0xf480fc00,
365 0x01f80032, 381 0x01f80032,
366/* 0x0474: hub_barrier_done */ 382/* 0x04a8: hub_barrier_done */
367 0x9801f7f0, 383 0x9801f7f0,
368 0xfebb040e, 384 0xfebb040e,
369 0x18e7f104, 385 0x18e7f104,
370 0x40e3f094, 386 0x40e3f094,
371 0xf88d21f4, 387 0xf88d21f4,
372/* 0x0489: ctx_redswitch */ 388/* 0x04bd: ctx_redswitch */
373 0x14e7f100, 389 0x14e7f100,
374 0x06e4b606, 390 0x06e4b606,
375 0xd020f7f0, 391 0xd020f7f0,
376 0xf7f000ef, 392 0xf7f000ef,
377/* 0x0499: ctx_redswitch_delay */ 393/* 0x04cd: ctx_redswitch_delay */
378 0x01f2b608, 394 0x01f2b608,
379 0xf1fd1bf4, 395 0xf1fd1bf4,
380 0xd00a20f7, 396 0xd00a20f7,
381 0x00f800ef, 397 0x00f800ef,
382/* 0x04a8: ctx_xfer */ 398/* 0x04dc: ctx_xfer */
383 0x0a0417f1, 399 0x0a0417f1,
384 0xd00614b6, 400 0xd00614b6,
385 0x11f4001f, 401 0x11f4001f,
386 0x8921f507, 402 0xbd21f507,
387/* 0x04b9: ctx_xfer_not_load */ 403/* 0x04ed: ctx_xfer_not_load */
388 0xfc17f104, 404 0xfc17f104,
389 0x0213f04a, 405 0x0213f04a,
390 0xd00c27f0, 406 0xd00c27f0,
@@ -424,13 +440,13 @@ uint32_t nvd7_grgpc_code[] = {
424 0x21f5015c, 440 0x21f5015c,
425 0x01f40207, 441 0x01f40207,
426 0x1412f406, 442 0x1412f406,
427/* 0x0554: ctx_xfer_post */ 443/* 0x0588: ctx_xfer_post */
428 0x4afc17f1, 444 0x4afc17f1,
429 0xf00213f0, 445 0xf00213f0,
430 0x12d00d27, 446 0x12d00d27,
431 0x0721f500, 447 0x0721f500,
432/* 0x0565: ctx_xfer_done */ 448/* 0x0599: ctx_xfer_done */
433 0x7421f502, 449 0xa821f502,
434 0x0000f804, 450 0x0000f804,
435 0x00000000, 451 0x00000000,
436 0x00000000, 452 0x00000000,
@@ -456,17 +472,4 @@ uint32_t nvd7_grgpc_code[] = {
456 0x00000000, 472 0x00000000,
457 0x00000000, 473 0x00000000,
458 0x00000000, 474 0x00000000,
459 0x00000000,
460 0x00000000,
461 0x00000000,
462 0x00000000,
463 0x00000000,
464 0x00000000,
465 0x00000000,
466 0x00000000,
467 0x00000000,
468 0x00000000,
469 0x00000000,
470 0x00000000,
471 0x00000000,
472}; 475};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
index dc26c2822e9f..dc9c7784aeca 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
@@ -16,9 +16,9 @@ uint32_t nve0_grgpc_data[] = {
16/* 0x0018: tpc_mask */ 16/* 0x0018: tpc_mask */
17 0x00000000, 17 0x00000000,
18/* 0x001c: unk_count */ 18/* 0x001c: unk_count */
19 0x00000001, 19 0x00000000,
20/* 0x0020: unk_mask */ 20/* 0x0020: unk_mask */
21 0x00000001, 21 0x00000000,
22/* 0x0024: cmd_queue */ 22/* 0x0024: cmd_queue */
23 0x00000000, 23 0x00000000,
24 0x00000000, 24 0x00000000,
@@ -271,7 +271,7 @@ uint32_t nve0_grgpc_code[] = {
271 0xf10004fe, 271 0xf10004fe,
272 0xf0120017, 272 0xf0120017,
273 0x12d00227, 273 0x12d00227,
274 0x2317f100, 274 0x5717f100,
275 0x0010fe04, 275 0x0010fe04,
276 0x040017f1, 276 0x040017f1,
277 0xf0c010d0, 277 0xf0c010d0,
@@ -286,7 +286,23 @@ uint32_t nve0_grgpc_code[] = {
286 0x06038005, 286 0x06038005,
287 0x040010b7, 287 0x040010b7,
288 0x800012cf, 288 0x800012cf,
289 0x27f10402, 289 0xe7f10402,
290 0xe3f00c30,
291 0xbd24bd50,
292/* 0x035f: init_unk_loop */
293 0xf444bd34,
294 0xf6b06821,
295 0x0f0bf400,
296 0xbb01f7f0,
297 0x4ffd04f2,
298 0x0130b605,
299/* 0x0374: init_unk_next */
300 0xb60120b6,
301 0x26b004e0,
302 0xe21bf401,
303/* 0x0380: init_unk_done */
304 0x80070380,
305 0x27f10804,
290 0x24b60800, 306 0x24b60800,
291 0x4022cf06, 307 0x4022cf06,
292 0x47f134bd, 308 0x47f134bd,
@@ -323,7 +339,7 @@ uint32_t nve0_grgpc_code[] = {
323 0x10b74013, 339 0x10b74013,
324 0x24bd0800, 340 0x24bd0800,
325 0xd01f29f0, 341 0xd01f29f0,
326/* 0x03e6: main */ 342/* 0x041a: main */
327 0x31f40012, 343 0x31f40012,
328 0x0028f400, 344 0x0028f400,
329 0xf424d7f0, 345 0xf424d7f0,
@@ -335,12 +351,12 @@ uint32_t nve0_grgpc_code[] = {
335 0xe4b60412, 351 0xe4b60412,
336 0x051efd01, 352 0x051efd01,
337 0xf50018fe, 353 0xf50018fe,
338 0xf404a821, 354 0xf404dc21,
339/* 0x0416: main_not_ctx_xfer */ 355/* 0x044a: main_not_ctx_xfer */
340 0xef94d30e, 356 0xef94d30e,
341 0x01f5f010, 357 0x01f5f010,
342 0x02ec21f5, 358 0x02ec21f5,
343/* 0x0423: ih */ 359/* 0x0457: ih */
344 0xf9c60ef4, 360 0xf9c60ef4,
345 0x0188fe80, 361 0x0188fe80,
346 0x90f980f9, 362 0x90f980f9,
@@ -355,7 +371,7 @@ uint32_t nve0_grgpc_code[] = {
355 0xb70421f4, 371 0xb70421f4,
356 0xf00400b0, 372 0xf00400b0,
357 0xbed001e7, 373 0xbed001e7,
358/* 0x0459: ih_no_fifo */ 374/* 0x048d: ih_no_fifo */
359 0x400ad000, 375 0x400ad000,
360 0xe0fcf0fc, 376 0xe0fcf0fc,
361 0xb0fcd0fc, 377 0xb0fcd0fc,
@@ -363,28 +379,28 @@ uint32_t nve0_grgpc_code[] = {
363 0x88fe80fc, 379 0x88fe80fc,
364 0xf480fc00, 380 0xf480fc00,
365 0x01f80032, 381 0x01f80032,
366/* 0x0474: hub_barrier_done */ 382/* 0x04a8: hub_barrier_done */
367 0x9801f7f0, 383 0x9801f7f0,
368 0xfebb040e, 384 0xfebb040e,
369 0x18e7f104, 385 0x18e7f104,
370 0x40e3f094, 386 0x40e3f094,
371 0xf88d21f4, 387 0xf88d21f4,
372/* 0x0489: ctx_redswitch */ 388/* 0x04bd: ctx_redswitch */
373 0x14e7f100, 389 0x14e7f100,
374 0x06e4b606, 390 0x06e4b606,
375 0xd020f7f0, 391 0xd020f7f0,
376 0xf7f000ef, 392 0xf7f000ef,
377/* 0x0499: ctx_redswitch_delay */ 393/* 0x04cd: ctx_redswitch_delay */
378 0x01f2b608, 394 0x01f2b608,
379 0xf1fd1bf4, 395 0xf1fd1bf4,
380 0xd00a20f7, 396 0xd00a20f7,
381 0x00f800ef, 397 0x00f800ef,
382/* 0x04a8: ctx_xfer */ 398/* 0x04dc: ctx_xfer */
383 0x0a0417f1, 399 0x0a0417f1,
384 0xd00614b6, 400 0xd00614b6,
385 0x11f4001f, 401 0x11f4001f,
386 0x8921f507, 402 0xbd21f507,
387/* 0x04b9: ctx_xfer_not_load */ 403/* 0x04ed: ctx_xfer_not_load */
388 0xfc17f104, 404 0xfc17f104,
389 0x0213f04a, 405 0x0213f04a,
390 0xd00c27f0, 406 0xd00c27f0,
@@ -424,13 +440,13 @@ uint32_t nve0_grgpc_code[] = {
424 0x21f5015c, 440 0x21f5015c,
425 0x01f40207, 441 0x01f40207,
426 0x1412f406, 442 0x1412f406,
427/* 0x0554: ctx_xfer_post */ 443/* 0x0588: ctx_xfer_post */
428 0x4afc17f1, 444 0x4afc17f1,
429 0xf00213f0, 445 0xf00213f0,
430 0x12d00d27, 446 0x12d00d27,
431 0x0721f500, 447 0x0721f500,
432/* 0x0565: ctx_xfer_done */ 448/* 0x0599: ctx_xfer_done */
433 0x7421f502, 449 0xa821f502,
434 0x0000f804, 450 0x0000f804,
435 0x00000000, 451 0x00000000,
436 0x00000000, 452 0x00000000,
@@ -456,17 +472,4 @@ uint32_t nve0_grgpc_code[] = {
456 0x00000000, 472 0x00000000,
457 0x00000000, 473 0x00000000,
458 0x00000000, 474 0x00000000,
459 0x00000000,
460 0x00000000,
461 0x00000000,
462 0x00000000,
463 0x00000000,
464 0x00000000,
465 0x00000000,
466 0x00000000,
467 0x00000000,
468 0x00000000,
469 0x00000000,
470 0x00000000,
471 0x00000000,
472}; 475};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h
index ecf9a5fb8557..cbbed6aa080b 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h
@@ -16,9 +16,9 @@ uint32_t nvf0_grgpc_data[] = {
16/* 0x0018: tpc_mask */ 16/* 0x0018: tpc_mask */
17 0x00000000, 17 0x00000000,
18/* 0x001c: unk_count */ 18/* 0x001c: unk_count */
19 0x00000001, 19 0x00000000,
20/* 0x0020: unk_mask */ 20/* 0x0020: unk_mask */
21 0x00000001, 21 0x00000000,
22/* 0x0024: cmd_queue */ 22/* 0x0024: cmd_queue */
23 0x00000000, 23 0x00000000,
24 0x00000000, 24 0x00000000,
@@ -271,7 +271,7 @@ uint32_t nvf0_grgpc_code[] = {
271 0xf10004fe, 271 0xf10004fe,
272 0xf0120017, 272 0xf0120017,
273 0x12d00227, 273 0x12d00227,
274 0x2317f100, 274 0x5717f100,
275 0x0010fe04, 275 0x0010fe04,
276 0x040017f1, 276 0x040017f1,
277 0xf0c010d0, 277 0xf0c010d0,
@@ -286,7 +286,23 @@ uint32_t nvf0_grgpc_code[] = {
286 0x06038005, 286 0x06038005,
287 0x040010b7, 287 0x040010b7,
288 0x800012cf, 288 0x800012cf,
289 0x27f10402, 289 0xe7f10402,
290 0xe3f00c30,
291 0xbd24bd50,
292/* 0x035f: init_unk_loop */
293 0xf444bd34,
294 0xf6b06821,
295 0x0f0bf400,
296 0xbb01f7f0,
297 0x4ffd04f2,
298 0x0130b605,
299/* 0x0374: init_unk_next */
300 0xb60120b6,
301 0x26b004e0,
302 0xe21bf402,
303/* 0x0380: init_unk_done */
304 0x80070380,
305 0x27f10804,
290 0x24b60800, 306 0x24b60800,
291 0x4022cf06, 307 0x4022cf06,
292 0x47f134bd, 308 0x47f134bd,
@@ -323,7 +339,7 @@ uint32_t nvf0_grgpc_code[] = {
323 0x10b74013, 339 0x10b74013,
324 0x24bd0800, 340 0x24bd0800,
325 0xd01f29f0, 341 0xd01f29f0,
326/* 0x03e6: main */ 342/* 0x041a: main */
327 0x31f40012, 343 0x31f40012,
328 0x0028f400, 344 0x0028f400,
329 0xf424d7f0, 345 0xf424d7f0,
@@ -335,12 +351,12 @@ uint32_t nvf0_grgpc_code[] = {
335 0xe4b60412, 351 0xe4b60412,
336 0x051efd01, 352 0x051efd01,
337 0xf50018fe, 353 0xf50018fe,
338 0xf404a821, 354 0xf404dc21,
339/* 0x0416: main_not_ctx_xfer */ 355/* 0x044a: main_not_ctx_xfer */
340 0xef94d30e, 356 0xef94d30e,
341 0x01f5f010, 357 0x01f5f010,
342 0x02ec21f5, 358 0x02ec21f5,
343/* 0x0423: ih */ 359/* 0x0457: ih */
344 0xf9c60ef4, 360 0xf9c60ef4,
345 0x0188fe80, 361 0x0188fe80,
346 0x90f980f9, 362 0x90f980f9,
@@ -355,7 +371,7 @@ uint32_t nvf0_grgpc_code[] = {
355 0xb70421f4, 371 0xb70421f4,
356 0xf00400b0, 372 0xf00400b0,
357 0xbed001e7, 373 0xbed001e7,
358/* 0x0459: ih_no_fifo */ 374/* 0x048d: ih_no_fifo */
359 0x400ad000, 375 0x400ad000,
360 0xe0fcf0fc, 376 0xe0fcf0fc,
361 0xb0fcd0fc, 377 0xb0fcd0fc,
@@ -363,28 +379,28 @@ uint32_t nvf0_grgpc_code[] = {
363 0x88fe80fc, 379 0x88fe80fc,
364 0xf480fc00, 380 0xf480fc00,
365 0x01f80032, 381 0x01f80032,
366/* 0x0474: hub_barrier_done */ 382/* 0x04a8: hub_barrier_done */
367 0x9801f7f0, 383 0x9801f7f0,
368 0xfebb040e, 384 0xfebb040e,
369 0x18e7f104, 385 0x18e7f104,
370 0x40e3f094, 386 0x40e3f094,
371 0xf88d21f4, 387 0xf88d21f4,
372/* 0x0489: ctx_redswitch */ 388/* 0x04bd: ctx_redswitch */
373 0x14e7f100, 389 0x14e7f100,
374 0x06e4b606, 390 0x06e4b606,
375 0xd020f7f0, 391 0xd020f7f0,
376 0xf7f000ef, 392 0xf7f000ef,
377/* 0x0499: ctx_redswitch_delay */ 393/* 0x04cd: ctx_redswitch_delay */
378 0x01f2b608, 394 0x01f2b608,
379 0xf1fd1bf4, 395 0xf1fd1bf4,
380 0xd00a20f7, 396 0xd00a20f7,
381 0x00f800ef, 397 0x00f800ef,
382/* 0x04a8: ctx_xfer */ 398/* 0x04dc: ctx_xfer */
383 0x0a0417f1, 399 0x0a0417f1,
384 0xd00614b6, 400 0xd00614b6,
385 0x11f4001f, 401 0x11f4001f,
386 0x8921f507, 402 0xbd21f507,
387/* 0x04b9: ctx_xfer_not_load */ 403/* 0x04ed: ctx_xfer_not_load */
388 0xfc17f104, 404 0xfc17f104,
389 0x0213f04a, 405 0x0213f04a,
390 0xd00c27f0, 406 0xd00c27f0,
@@ -424,13 +440,13 @@ uint32_t nvf0_grgpc_code[] = {
424 0x21f5015c, 440 0x21f5015c,
425 0x01f40207, 441 0x01f40207,
426 0x1412f406, 442 0x1412f406,
427/* 0x0554: ctx_xfer_post */ 443/* 0x0588: ctx_xfer_post */
428 0x4afc17f1, 444 0x4afc17f1,
429 0xf00213f0, 445 0xf00213f0,
430 0x12d00d27, 446 0x12d00d27,
431 0x0721f500, 447 0x0721f500,
432/* 0x0565: ctx_xfer_done */ 448/* 0x0599: ctx_xfer_done */
433 0x7421f502, 449 0xa821f502,
434 0x0000f804, 450 0x0000f804,
435 0x00000000, 451 0x00000000,
436 0x00000000, 452 0x00000000,
@@ -456,17 +472,4 @@ uint32_t nvf0_grgpc_code[] = {
456 0x00000000, 472 0x00000000,
457 0x00000000, 473 0x00000000,
458 0x00000000, 474 0x00000000,
459 0x00000000,
460 0x00000000,
461 0x00000000,
462 0x00000000,
463 0x00000000,
464 0x00000000,
465 0x00000000,
466 0x00000000,
467 0x00000000,
468 0x00000000,
469 0x00000000,
470 0x00000000,
471 0x00000000,
472}; 475};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 21:26:54 -0500