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authorBen Skeggs <bskeggs@redhat.com>2013-06-30 20:54:27 -0400
committerBen Skeggs <bskeggs@redhat.com>2013-07-04 23:42:51 -0400
commitc03ff9e8fa5fc0186158b99a89f613325ff352cf (patch)
tree7b2daac7bacc5caa7c96b6218c379a227ff45d01 /drivers/gpu
parent30f4e0870d1726f31aa59804337cfd5e0a3f2ec7 (diff)
drm/nvc0-/gr: pull out a group of separately context-switched gpc regs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c47
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c9
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c33
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c36
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c33
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h6
6 files changed, 68 insertions, 96 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
index a09ee65b0f99..087295db9707 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
@@ -749,7 +749,7 @@ nvc0_grctx_init_rop[] = {
749}; 749};
750 750
751struct nvc0_graph_init 751struct nvc0_graph_init
752nvc0_grctx_init_gpc[] = { 752nvc0_grctx_init_gpc_0[] = {
753 { 0x418380, 1, 0x04, 0x00000016 }, 753 { 0x418380, 1, 0x04, 0x00000016 },
754 { 0x418400, 1, 0x04, 0x38004e00 }, 754 { 0x418400, 1, 0x04, 0x38004e00 },
755 { 0x418404, 1, 0x04, 0x71e0ffff }, 755 { 0x418404, 1, 0x04, 0x71e0ffff },
@@ -779,6 +779,26 @@ nvc0_grctx_init_gpc[] = {
779 { 0x418924, 1, 0x04, 0x00000000 }, 779 { 0x418924, 1, 0x04, 0x00000000 },
780 { 0x418928, 1, 0x04, 0x00ffff00 }, 780 { 0x418928, 1, 0x04, 0x00ffff00 },
781 { 0x41892c, 1, 0x04, 0x0000ff00 }, 781 { 0x41892c, 1, 0x04, 0x0000ff00 },
782 { 0x418b00, 1, 0x04, 0x00000000 },
783 { 0x418b08, 1, 0x04, 0x0a418820 },
784 { 0x418b0c, 1, 0x04, 0x062080e6 },
785 { 0x418b10, 1, 0x04, 0x020398a4 },
786 { 0x418b14, 1, 0x04, 0x0e629062 },
787 { 0x418b18, 1, 0x04, 0x0a418820 },
788 { 0x418b1c, 1, 0x04, 0x000000e6 },
789 { 0x418bb8, 1, 0x04, 0x00000103 },
790 { 0x418c08, 1, 0x04, 0x00000001 },
791 { 0x418c10, 8, 0x04, 0x00000000 },
792 { 0x418c80, 1, 0x04, 0x20200004 },
793 { 0x418c8c, 1, 0x04, 0x00000001 },
794 { 0x419000, 1, 0x04, 0x00000780 },
795 { 0x419004, 2, 0x04, 0x00000000 },
796 { 0x419014, 1, 0x04, 0x00000004 },
797 {}
798};
799
800struct nvc0_graph_init
801nvc0_grctx_init_gpc_1[] = {
782 { 0x418a00, 3, 0x04, 0x00000000 }, 802 { 0x418a00, 3, 0x04, 0x00000000 },
783 { 0x418a0c, 1, 0x04, 0x00010000 }, 803 { 0x418a0c, 1, 0x04, 0x00010000 },
784 { 0x418a10, 3, 0x04, 0x00000000 }, 804 { 0x418a10, 3, 0x04, 0x00000000 },
@@ -803,21 +823,6 @@ nvc0_grctx_init_gpc[] = {
803 { 0x418ae0, 3, 0x04, 0x00000000 }, 823 { 0x418ae0, 3, 0x04, 0x00000000 },
804 { 0x418aec, 1, 0x04, 0x00010000 }, 824 { 0x418aec, 1, 0x04, 0x00010000 },
805 { 0x418af0, 3, 0x04, 0x00000000 }, 825 { 0x418af0, 3, 0x04, 0x00000000 },
806 { 0x418b00, 1, 0x04, 0x00000000 },
807 { 0x418b08, 1, 0x04, 0x0a418820 },
808 { 0x418b0c, 1, 0x04, 0x062080e6 },
809 { 0x418b10, 1, 0x04, 0x020398a4 },
810 { 0x418b14, 1, 0x04, 0x0e629062 },
811 { 0x418b18, 1, 0x04, 0x0a418820 },
812 { 0x418b1c, 1, 0x04, 0x000000e6 },
813 { 0x418bb8, 1, 0x04, 0x00000103 },
814 { 0x418c08, 1, 0x04, 0x00000001 },
815 { 0x418c10, 8, 0x04, 0x00000000 },
816 { 0x418c80, 1, 0x04, 0x20200004 },
817 { 0x418c8c, 1, 0x04, 0x00000001 },
818 { 0x419000, 1, 0x04, 0x00000780 },
819 { 0x419004, 2, 0x04, 0x00000000 },
820 { 0x419014, 1, 0x04, 0x00000004 },
821 {} 826 {}
822}; 827};
823 828
@@ -1044,7 +1049,8 @@ nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
1044 1049
1045 for (i = 0; oclass->mmio[i]; i++) 1050 for (i = 0; oclass->mmio[i]; i++)
1046 nvc0_graph_mmio(priv, oclass->mmio[i]); 1051 nvc0_graph_mmio(priv, oclass->mmio[i]);
1047 nvc0_graph_mmio(priv, oclass->gpc); 1052 for (i = 0; oclass->gpc[i]; i++)
1053 nvc0_graph_mmio(priv, oclass->gpc[i]);
1048 nvc0_graph_mmio(priv, oclass->tpc); 1054 nvc0_graph_mmio(priv, oclass->tpc);
1049 1055
1050 nv_wr32(priv, 0x404154, 0x00000000); 1056 nv_wr32(priv, 0x404154, 0x00000000);
@@ -1188,6 +1194,13 @@ nvc0_grctx_init_mmio[] = {
1188 NULL 1194 NULL
1189}; 1195};
1190 1196
1197struct nvc0_graph_init *
1198nvc0_grctx_init_gpc[] = {
1199 nvc0_grctx_init_gpc_0,
1200 nvc0_grctx_init_gpc_1,
1201 NULL
1202};
1203
1191struct nvc0_graph_init 1204struct nvc0_graph_init
1192nvc0_grctx_init_mthd_magic[] = { 1205nvc0_grctx_init_mthd_magic[] = {
1193 { 0x3410, 1, 0x04, 0x00000000 }, 1206 { 0x3410, 1, 0x04, 0x00000000 },
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c
index 75047154b74d..09e17f9eb508 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c
@@ -601,7 +601,7 @@ nvc1_grctx_init_rop[] = {
601}; 601};
602 602
603static struct nvc0_graph_init 603static struct nvc0_graph_init
604nvc1_grctx_init_gpc[] = { 604nvc1_grctx_init_gpc_0[] = {
605 { 0x418380, 1, 0x04, 0x00000016 }, 605 { 0x418380, 1, 0x04, 0x00000016 },
606 { 0x418400, 1, 0x04, 0x38004e00 }, 606 { 0x418400, 1, 0x04, 0x38004e00 },
607 { 0x418404, 1, 0x04, 0x71e0ffff }, 607 { 0x418404, 1, 0x04, 0x71e0ffff },
@@ -772,6 +772,13 @@ nvc1_grctx_init_mmio[] = {
772 NULL 772 NULL
773}; 773};
774 774
775struct nvc0_graph_init *
776nvc1_grctx_init_gpc[] = {
777 nvc1_grctx_init_gpc_0,
778 nvc0_grctx_init_gpc_1,
779 NULL
780};
781
775static struct nvc0_graph_mthd 782static struct nvc0_graph_mthd
776nvc1_grctx_init_mthd[] = { 783nvc1_grctx_init_mthd[] = {
777 { 0x9097, nvc1_grctx_init_9097, }, 784 { 0x9097, nvc1_grctx_init_9097, },
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c
index 4be543e411cd..e4f1a8c6f68c 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c
@@ -358,7 +358,7 @@ nvd9_grctx_init_rop[] = {
358}; 358};
359 359
360static struct nvc0_graph_init 360static struct nvc0_graph_init
361nvd9_grctx_init_gpc[] = { 361nvd9_grctx_init_gpc_0[] = {
362 { 0x418380, 1, 0x04, 0x00000016 }, 362 { 0x418380, 1, 0x04, 0x00000016 },
363 { 0x418400, 1, 0x04, 0x38004e00 }, 363 { 0x418400, 1, 0x04, 0x38004e00 },
364 { 0x418404, 1, 0x04, 0x71e0ffff }, 364 { 0x418404, 1, 0x04, 0x71e0ffff },
@@ -385,30 +385,6 @@ nvd9_grctx_init_gpc[] = {
385 { 0x418924, 1, 0x04, 0x00000000 }, 385 { 0x418924, 1, 0x04, 0x00000000 },
386 { 0x418928, 1, 0x04, 0x00ffff00 }, 386 { 0x418928, 1, 0x04, 0x00ffff00 },
387 { 0x41892c, 1, 0x04, 0x0000ff00 }, 387 { 0x41892c, 1, 0x04, 0x0000ff00 },
388 { 0x418a00, 3, 0x04, 0x00000000 },
389 { 0x418a0c, 1, 0x04, 0x00010000 },
390 { 0x418a10, 3, 0x04, 0x00000000 },
391 { 0x418a20, 3, 0x04, 0x00000000 },
392 { 0x418a2c, 1, 0x04, 0x00010000 },
393 { 0x418a30, 3, 0x04, 0x00000000 },
394 { 0x418a40, 3, 0x04, 0x00000000 },
395 { 0x418a4c, 1, 0x04, 0x00010000 },
396 { 0x418a50, 3, 0x04, 0x00000000 },
397 { 0x418a60, 3, 0x04, 0x00000000 },
398 { 0x418a6c, 1, 0x04, 0x00010000 },
399 { 0x418a70, 3, 0x04, 0x00000000 },
400 { 0x418a80, 3, 0x04, 0x00000000 },
401 { 0x418a8c, 1, 0x04, 0x00010000 },
402 { 0x418a90, 3, 0x04, 0x00000000 },
403 { 0x418aa0, 3, 0x04, 0x00000000 },
404 { 0x418aac, 1, 0x04, 0x00010000 },
405 { 0x418ab0, 3, 0x04, 0x00000000 },
406 { 0x418ac0, 3, 0x04, 0x00000000 },
407 { 0x418acc, 1, 0x04, 0x00010000 },
408 { 0x418ad0, 3, 0x04, 0x00000000 },
409 { 0x418ae0, 3, 0x04, 0x00000000 },
410 { 0x418aec, 1, 0x04, 0x00010000 },
411 { 0x418af0, 3, 0x04, 0x00000000 },
412 { 0x418b00, 1, 0x04, 0x00000006 }, 388 { 0x418b00, 1, 0x04, 0x00000006 },
413 { 0x418b08, 1, 0x04, 0x0a418820 }, 389 { 0x418b08, 1, 0x04, 0x0a418820 },
414 { 0x418b0c, 1, 0x04, 0x062080e6 }, 390 { 0x418b0c, 1, 0x04, 0x062080e6 },
@@ -492,6 +468,13 @@ nvd9_grctx_init_mmio[] = {
492 nvd9_grctx_init_rop, 468 nvd9_grctx_init_rop,
493}; 469};
494 470
471struct nvc0_graph_init *
472nvd9_grctx_init_gpc[] = {
473 nvd9_grctx_init_gpc_0,
474 nvc0_grctx_init_gpc_1,
475 NULL
476};
477
495struct nvc0_graph_init 478struct nvc0_graph_init
496nvd9_grctx_init_mthd_magic[] = { 479nvd9_grctx_init_mthd_magic[] = {
497 { 0x3410, 1, 0x04, 0x80002006 }, 480 { 0x3410, 1, 0x04, 0x80002006 },
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
index 4f6041490986..1c68fb11b889 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
@@ -699,7 +699,7 @@ nve4_grctx_init_rop[] = {
699}; 699};
700 700
701static struct nvc0_graph_init 701static struct nvc0_graph_init
702nve4_grctx_init_gpc[] = { 702nve4_grctx_init_gpc_0[] = {
703 { 0x418380, 1, 0x04, 0x00000016 }, 703 { 0x418380, 1, 0x04, 0x00000016 },
704 { 0x418400, 1, 0x04, 0x38004e00 }, 704 { 0x418400, 1, 0x04, 0x38004e00 },
705 { 0x418404, 1, 0x04, 0x71e0ffff }, 705 { 0x418404, 1, 0x04, 0x71e0ffff },
@@ -726,30 +726,6 @@ nve4_grctx_init_gpc[] = {
726 { 0x418924, 1, 0x04, 0x00000000 }, 726 { 0x418924, 1, 0x04, 0x00000000 },
727 { 0x418928, 1, 0x04, 0x00ffff00 }, 727 { 0x418928, 1, 0x04, 0x00ffff00 },
728 { 0x41892c, 1, 0x04, 0x0000ff00 }, 728 { 0x41892c, 1, 0x04, 0x0000ff00 },
729 { 0x418a00, 3, 0x04, 0x00000000 },
730 { 0x418a0c, 1, 0x04, 0x00010000 },
731 { 0x418a10, 3, 0x04, 0x00000000 },
732 { 0x418a20, 3, 0x04, 0x00000000 },
733 { 0x418a2c, 1, 0x04, 0x00010000 },
734 { 0x418a30, 3, 0x04, 0x00000000 },
735 { 0x418a40, 3, 0x04, 0x00000000 },
736 { 0x418a4c, 1, 0x04, 0x00010000 },
737 { 0x418a50, 3, 0x04, 0x00000000 },
738 { 0x418a60, 3, 0x04, 0x00000000 },
739 { 0x418a6c, 1, 0x04, 0x00010000 },
740 { 0x418a70, 3, 0x04, 0x00000000 },
741 { 0x418a80, 3, 0x04, 0x00000000 },
742 { 0x418a8c, 1, 0x04, 0x00010000 },
743 { 0x418a90, 3, 0x04, 0x00000000 },
744 { 0x418aa0, 3, 0x04, 0x00000000 },
745 { 0x418aac, 1, 0x04, 0x00010000 },
746 { 0x418ab0, 3, 0x04, 0x00000000 },
747 { 0x418ac0, 3, 0x04, 0x00000000 },
748 { 0x418acc, 1, 0x04, 0x00010000 },
749 { 0x418ad0, 3, 0x04, 0x00000000 },
750 { 0x418ae0, 3, 0x04, 0x00000000 },
751 { 0x418aec, 1, 0x04, 0x00010000 },
752 { 0x418af0, 3, 0x04, 0x00000000 },
753 { 0x418b00, 1, 0x04, 0x00000006 }, 729 { 0x418b00, 1, 0x04, 0x00000006 },
754 { 0x418b08, 1, 0x04, 0x0a418820 }, 730 { 0x418b08, 1, 0x04, 0x0a418820 },
755 { 0x418b0c, 1, 0x04, 0x062080e6 }, 731 { 0x418b0c, 1, 0x04, 0x062080e6 },
@@ -937,7 +913,8 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
937 913
938 for (i = 0; oclass->mmio[i]; i++) 914 for (i = 0; oclass->mmio[i]; i++)
939 nvc0_graph_mmio(priv, oclass->mmio[i]); 915 nvc0_graph_mmio(priv, oclass->mmio[i]);
940 nvc0_graph_mmio(priv, oclass->gpc); 916 for (i = 0; oclass->gpc[i]; i++)
917 nvc0_graph_mmio(priv, oclass->gpc[i]);
941 nvc0_graph_mmio(priv, oclass->tpc); 918 nvc0_graph_mmio(priv, oclass->tpc);
942 919
943 nv_wr32(priv, 0x404154, 0x00000000); 920 nv_wr32(priv, 0x404154, 0x00000000);
@@ -1004,6 +981,13 @@ nve4_grctx_init_mmio[] = {
1004 NULL 981 NULL
1005}; 982};
1006 983
984struct nvc0_graph_init *
985nve4_grctx_init_gpc[] = {
986 nve4_grctx_init_gpc_0,
987 nvc0_grctx_init_gpc_1,
988 NULL
989};
990
1007static struct nvc0_graph_mthd 991static struct nvc0_graph_mthd
1008nve4_grctx_init_mthd[] = { 992nve4_grctx_init_mthd[] = {
1009 { 0xa097, nve4_grctx_init_a097, }, 993 { 0xa097, nve4_grctx_init_a097, },
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
index 8aae1f3415f5..a692389cd9cf 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
@@ -104,7 +104,7 @@ nvf0_grctx_init_unk88xx[] = {
104}; 104};
105 105
106static struct nvc0_graph_init 106static struct nvc0_graph_init
107nvf0_grctx_init_gpc[] = { 107nvf0_grctx_init_gpc_0[] = {
108 { 0x418380, 1, 0x04, 0x00000016 }, 108 { 0x418380, 1, 0x04, 0x00000016 },
109 { 0x418400, 1, 0x04, 0x38004e00 }, 109 { 0x418400, 1, 0x04, 0x38004e00 },
110 { 0x418404, 1, 0x04, 0x71e0ffff }, 110 { 0x418404, 1, 0x04, 0x71e0ffff },
@@ -133,30 +133,6 @@ nvf0_grctx_init_gpc[] = {
133 { 0x418924, 1, 0x04, 0x00000000 }, 133 { 0x418924, 1, 0x04, 0x00000000 },
134 { 0x418928, 1, 0x04, 0x00ffff00 }, 134 { 0x418928, 1, 0x04, 0x00ffff00 },
135 { 0x41892c, 1, 0x04, 0x0000ff00 }, 135 { 0x41892c, 1, 0x04, 0x0000ff00 },
136 { 0x418a00, 3, 0x04, 0x00000000 },
137 { 0x418a0c, 1, 0x04, 0x00010000 },
138 { 0x418a10, 3, 0x04, 0x00000000 },
139 { 0x418a20, 3, 0x04, 0x00000000 },
140 { 0x418a2c, 1, 0x04, 0x00010000 },
141 { 0x418a30, 3, 0x04, 0x00000000 },
142 { 0x418a40, 3, 0x04, 0x00000000 },
143 { 0x418a4c, 1, 0x04, 0x00010000 },
144 { 0x418a50, 3, 0x04, 0x00000000 },
145 { 0x418a60, 3, 0x04, 0x00000000 },
146 { 0x418a6c, 1, 0x04, 0x00010000 },
147 { 0x418a70, 3, 0x04, 0x00000000 },
148 { 0x418a80, 3, 0x04, 0x00000000 },
149 { 0x418a8c, 1, 0x04, 0x00010000 },
150 { 0x418a90, 3, 0x04, 0x00000000 },
151 { 0x418aa0, 3, 0x04, 0x00000000 },
152 { 0x418aac, 1, 0x04, 0x00010000 },
153 { 0x418ab0, 3, 0x04, 0x00000000 },
154 { 0x418ac0, 3, 0x04, 0x00000000 },
155 { 0x418acc, 1, 0x04, 0x00010000 },
156 { 0x418ad0, 3, 0x04, 0x00000000 },
157 { 0x418ae0, 3, 0x04, 0x00000000 },
158 { 0x418aec, 1, 0x04, 0x00010000 },
159 { 0x418af0, 3, 0x04, 0x00000000 },
160 { 0x418b00, 1, 0x04, 0x00000006 }, 136 { 0x418b00, 1, 0x04, 0x00000006 },
161 { 0x418b08, 1, 0x04, 0x0a418820 }, 137 { 0x418b08, 1, 0x04, 0x0a418820 },
162 { 0x418b0c, 1, 0x04, 0x062080e6 }, 138 { 0x418b0c, 1, 0x04, 0x062080e6 },
@@ -259,6 +235,13 @@ nvf0_grctx_init_mmio[] = {
259 NULL 235 NULL
260}; 236};
261 237
238struct nvc0_graph_init *
239nvf0_grctx_init_gpc[] = {
240 nvf0_grctx_init_gpc_0,
241 nvc0_grctx_init_gpc_1,
242 NULL
243};
244
262static struct nvc0_graph_mthd 245static struct nvc0_graph_mthd
263nvf0_grctx_init_mthd[] = { 246nvf0_grctx_init_mthd[] = {
264 { 0xa197, nvc1_grctx_init_9097, }, 247 { 0xa197, nvc1_grctx_init_9097, },
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
index f7d0df7c84ad..52d70ba5ffb5 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
@@ -152,7 +152,7 @@ struct nvc0_grctx_oclass {
152 void (*mods)(struct nvc0_graph_priv *, struct nvc0_grctx *); 152 void (*mods)(struct nvc0_graph_priv *, struct nvc0_grctx *);
153 /* mmio context data */ 153 /* mmio context data */
154 struct nvc0_graph_init **mmio; 154 struct nvc0_graph_init **mmio;
155 struct nvc0_graph_init *gpc; 155 struct nvc0_graph_init **gpc;
156 struct nvc0_graph_init *tpc; 156 struct nvc0_graph_init *tpc;
157 /* indirect context data, generated with icmds/mthds */ 157 /* indirect context data, generated with icmds/mthds */
158 struct nvc0_graph_init *icmd; 158 struct nvc0_graph_init *icmd;
@@ -223,7 +223,9 @@ extern struct nvc0_graph_init nvc0_grctx_init_unk60xx[];
223extern struct nvc0_graph_init nvc0_grctx_init_unk64xx[]; 223extern struct nvc0_graph_init nvc0_grctx_init_unk64xx[];
224extern struct nvc0_graph_init nvc0_grctx_init_unk78xx[]; 224extern struct nvc0_graph_init nvc0_grctx_init_unk78xx[];
225extern struct nvc0_graph_init nvc0_grctx_init_unk80xx[]; 225extern struct nvc0_graph_init nvc0_grctx_init_unk80xx[];
226extern struct nvc0_graph_init nvc0_grctx_init_gpc[]; 226extern struct nvc0_graph_init nvc0_grctx_init_gpc_0[];
227extern struct nvc0_graph_init nvc0_grctx_init_gpc_1[];
228extern struct nvc0_graph_init *nvc0_grctx_init_gpc[];
227extern struct nvc0_graph_init nvc0_grctx_init_tpc[]; 229extern struct nvc0_graph_init nvc0_grctx_init_tpc[];
228extern struct nvc0_graph_init nvc0_grctx_init_icmd[]; 230extern struct nvc0_graph_init nvc0_grctx_init_icmd[];
229extern struct nvc0_graph_init nvd9_grctx_init_icmd[]; // 231extern struct nvc0_graph_init nvd9_grctx_init_icmd[]; //
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 21:16:43 -0500