drm/i915: Update GEN6_RP_CONTROL definitions

This matches the modern specs more accurately.

This will be used by the following patch to fix the way we display RC
status.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>

2 files changed, 6 insertions, 2 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3ae2c7c00ef2..583e8c7569fa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3502,7 +3502,11 @@
 #define   GEN6_CAGF_MASK                        (0x7f << GEN6_CAGF_SHIFT)
 #define GEN6_RP_CONTROL                         0xA024
 #define   GEN6_RP_MEDIA_TURBO                   (1<<11)
-#define   GEN6_RP_USE_NORMAL_FREQ               (1<<9)
+#define   GEN6_RP_MEDIA_MODE_MASK               (3<<9)
+#define   GEN6_RP_MEDIA_HW_TURBO_MODE           (3<<9)
+#define   GEN6_RP_MEDIA_HW_NORMAL_MODE          (2<<9)
+#define   GEN6_RP_MEDIA_HW_MODE                 (1<<9)
+#define   GEN6_RP_MEDIA_SW_MODE                 (0<<9)
 #define   GEN6_RP_MEDIA_IS_GFX                  (1<<8)
 #define   GEN6_RP_ENABLE                        (1<<7)
 #define   GEN6_RP_UP_IDLE_MIN                   (0x1<<3)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 55a5b4c4edf1..cb21d5bbeccb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8043,7 +8043,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
         I915_WRITE(GEN6_RP_CONTROL,
                    GEN6_RP_MEDIA_TURBO |
-                   GEN6_RP_USE_NORMAL_FREQ |
+                   GEN6_RP_MEDIA_HW_MODE |
                    GEN6_RP_MEDIA_IS_GFX |
                    GEN6_RP_ENABLE |
                    GEN6_RP_UP_BUSY_AVG |