drm/radeon/kms: add radeon_asic struct for SI

Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
author: Alex Deucher <alexander.deucher@amd.com> 2012-03-20 17:18:25 -0400
committer: Dave Airlie <airlied@redhat.com> 2012-03-21 02:55:55 -0400
commit: 02779c082c4a75a845ede36182af148952a9c488 (patch)
tree: f0e429d15bb85a4ec77730cd02ef2f3a42086834 /drivers/gpu
parent: 8d5ef7b1f67a2f8e6594b38a68c1566ed0740ec1 (diff)
2 files changed, 132 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 479c89e0af17..f24e14592790 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -1408,6 +1408,108 @@ static struct radeon_asic cayman_asic = {
        },
 };
+static const struct radeon_vm_funcs si_vm_funcs = {
+        .init = &si_vm_init,
+        .fini = &si_vm_fini,
+        .bind = &si_vm_bind,
+        .unbind = &si_vm_unbind,
+        .tlb_flush = &si_vm_tlb_flush,
+        .page_flags = &cayman_vm_page_flags,
+        .set_page = &cayman_vm_set_page,
+};
+static struct radeon_asic si_asic = {
+        .init = &si_init,
+        .fini = &si_fini,
+        .suspend = &si_suspend,
+        .resume = &si_resume,
+        .gpu_is_lockup = &si_gpu_is_lockup,
+        .asic_reset = &si_asic_reset,
+        .vga_set_state = &r600_vga_set_state,
+        .ioctl_wait_idle = r600_ioctl_wait_idle,
+        .gui_idle = &r600_gui_idle,
+        .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
+        .gart = {
+                .tlb_flush = &si_pcie_gart_tlb_flush,
+                .set_page = &rs600_gart_set_page,
+        },
+        .ring = {
+                [RADEON_RING_TYPE_GFX_INDEX] = {
+                        .ib_execute = &si_ring_ib_execute,
+                        .ib_parse = &si_ib_parse,
+                        .emit_fence = &si_fence_ring_emit,
+                        .emit_semaphore = &r600_semaphore_ring_emit,
+                        .cs_parse = NULL,
+                        .ring_test = &r600_ring_test,
+                        .ib_test = &r600_ib_test,
+                },
+                [CAYMAN_RING_TYPE_CP1_INDEX] = {
+                        .ib_execute = &si_ring_ib_execute,
+                        .ib_parse = &si_ib_parse,
+                        .emit_fence = &si_fence_ring_emit,
+                        .emit_semaphore = &r600_semaphore_ring_emit,
+                        .cs_parse = NULL,
+                        .ring_test = &r600_ring_test,
+                        .ib_test = &r600_ib_test,
+                },
+                [CAYMAN_RING_TYPE_CP2_INDEX] = {
+                        .ib_execute = &si_ring_ib_execute,
+                        .ib_parse = &si_ib_parse,
+                        .emit_fence = &si_fence_ring_emit,
+                        .emit_semaphore = &r600_semaphore_ring_emit,
+                        .cs_parse = NULL,
+                        .ring_test = &r600_ring_test,
+                        .ib_test = &r600_ib_test,
+                }
+        },
+        .irq = {
+                .set = &si_irq_set,
+                .process = &si_irq_process,
+        },
+        .display = {
+                .bandwidth_update = &dce6_bandwidth_update,
+                .get_vblank_counter = &evergreen_get_vblank_counter,
+                .wait_for_vblank = &dce4_wait_for_vblank,
+        },
+        .copy = {
+                .blit = NULL,
+                .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+                .dma = NULL,
+                .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+                .copy = NULL,
+                .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+        },
+        .surface = {
+                .set_reg = r600_set_surface_reg,
+                .clear_reg = r600_clear_surface_reg,
+        },
+        .hpd = {
+                .init = &evergreen_hpd_init,
+                .fini = &evergreen_hpd_fini,
+                .sense = &evergreen_hpd_sense,
+                .set_polarity = &evergreen_hpd_set_polarity,
+        },
+        .pm = {
+                .misc = &evergreen_pm_misc,
+                .prepare = &evergreen_pm_prepare,
+                .finish = &evergreen_pm_finish,
+                .init_profile = &sumo_pm_init_profile,
+                .get_dynpm_state = &r600_pm_get_dynpm_state,
+                .get_engine_clock = &radeon_atom_get_engine_clock,
+                .set_engine_clock = &radeon_atom_set_engine_clock,
+                .get_memory_clock = &radeon_atom_get_memory_clock,
+                .set_memory_clock = &radeon_atom_set_memory_clock,
+                .get_pcie_lanes = NULL,
+                .set_pcie_lanes = NULL,
+                .set_clock_gating = NULL,
+        },
+        .pflip = {
+                .pre_page_flip = &evergreen_pre_page_flip,
+                .page_flip = &evergreen_page_flip,
+                .post_page_flip = &evergreen_post_page_flip,
+        },
+};
 int radeon_asic_init(struct radeon_device *rdev)
 {
        radeon_register_accessor_init(rdev);
@@ -1525,6 +1627,14 @@ int radeon_asic_init(struct radeon_device *rdev)
                rdev->num_crtc = 6;
                rdev->vm_manager.funcs = &cayman_vm_funcs;
                break;
+        case CHIP_TAHITI:
+        case CHIP_PITCAIRN:
+        case CHIP_VERDE:
+                rdev->asic = &si_asic;
+                /* set num crtcs */
+                rdev->num_crtc = 6;
+                rdev->vm_manager.funcs = &si_vm_funcs;
+                break;
        default:
                /* FIXME: not supported yet */
                return -EINVAL;
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 007f0f632a48..3d9f9f1d8f90 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -464,4 +464,26 @@ int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
 /* DCE6 - SI */
 void dce6_bandwidth_update(struct radeon_device *rdev);
+/*
+ * si
+ */
+void si_fence_ring_emit(struct radeon_device *rdev,
+                        struct radeon_fence *fence);
+void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
+int si_init(struct radeon_device *rdev);
+void si_fini(struct radeon_device *rdev);
+int si_suspend(struct radeon_device *rdev);
+int si_resume(struct radeon_device *rdev);
+bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
+int si_asic_reset(struct radeon_device *rdev);
+void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
+int si_irq_set(struct radeon_device *rdev);
+int si_irq_process(struct radeon_device *rdev);
+int si_vm_init(struct radeon_device *rdev);
+void si_vm_fini(struct radeon_device *rdev);
+int si_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id);
+void si_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
+void si_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm);
+int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
 #endif
author	Alex Deucher <alexander.deucher@amd.com>	2012-03-20 17:18:25 -0400
committer	Dave Airlie <airlied@redhat.com>	2012-03-21 02:55:55 -0400
commit	02779c082c4a75a845ede36182af148952a9c488 (patch)
tree	f0e429d15bb85a4ec77730cd02ef2f3a42086834 /drivers/gpu
parent	8d5ef7b1f67a2f8e6594b38a68c1566ed0740ec1 (diff)

diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 479c89e0af17..f24e14592790 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -1408,6 +1408,108 @@ static struct radeon_asic cayman_asic = {
1408	},	1408	},
1409	};	1409	};
1410		1410
		1411	static const struct radeon_vm_funcs si_vm_funcs = {
		1412	.init = &si_vm_init,
		1413	.fini = &si_vm_fini,
		1414	.bind = &si_vm_bind,
		1415	.unbind = &si_vm_unbind,
		1416	.tlb_flush = &si_vm_tlb_flush,
		1417	.page_flags = &cayman_vm_page_flags,
		1418	.set_page = &cayman_vm_set_page,
		1419	};
		1420
		1421	static struct radeon_asic si_asic = {
		1422	.init = &si_init,
		1423	.fini = &si_fini,
		1424	.suspend = &si_suspend,
		1425	.resume = &si_resume,
		1426	.gpu_is_lockup = &si_gpu_is_lockup,
		1427	.asic_reset = &si_asic_reset,
		1428	.vga_set_state = &r600_vga_set_state,
		1429	.ioctl_wait_idle = r600_ioctl_wait_idle,
		1430	.gui_idle = &r600_gui_idle,
		1431	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
		1432	.gart = {
		1433	.tlb_flush = &si_pcie_gart_tlb_flush,
		1434	.set_page = &rs600_gart_set_page,
		1435	},
		1436	.ring = {
		1437	[RADEON_RING_TYPE_GFX_INDEX] = {
		1438	.ib_execute = &si_ring_ib_execute,
		1439	.ib_parse = &si_ib_parse,
		1440	.emit_fence = &si_fence_ring_emit,
		1441	.emit_semaphore = &r600_semaphore_ring_emit,
		1442	.cs_parse = NULL,
		1443	.ring_test = &r600_ring_test,
		1444	.ib_test = &r600_ib_test,
		1445	},
		1446	[CAYMAN_RING_TYPE_CP1_INDEX] = {
		1447	.ib_execute = &si_ring_ib_execute,
		1448	.ib_parse = &si_ib_parse,
		1449	.emit_fence = &si_fence_ring_emit,
		1450	.emit_semaphore = &r600_semaphore_ring_emit,
		1451	.cs_parse = NULL,
		1452	.ring_test = &r600_ring_test,
		1453	.ib_test = &r600_ib_test,
		1454	},
		1455	[CAYMAN_RING_TYPE_CP2_INDEX] = {
		1456	.ib_execute = &si_ring_ib_execute,
		1457	.ib_parse = &si_ib_parse,
		1458	.emit_fence = &si_fence_ring_emit,
		1459	.emit_semaphore = &r600_semaphore_ring_emit,
		1460	.cs_parse = NULL,
		1461	.ring_test = &r600_ring_test,
		1462	.ib_test = &r600_ib_test,
		1463	}
		1464	},
		1465	.irq = {
		1466	.set = &si_irq_set,
		1467	.process = &si_irq_process,
		1468	},
		1469	.display = {
		1470	.bandwidth_update = &dce6_bandwidth_update,
		1471	.get_vblank_counter = &evergreen_get_vblank_counter,
		1472	.wait_for_vblank = &dce4_wait_for_vblank,
		1473	},
		1474	.copy = {
		1475	.blit = NULL,
		1476	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		1477	.dma = NULL,
		1478	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		1479	.copy = NULL,
		1480	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		1481	},
		1482	.surface = {
		1483	.set_reg = r600_set_surface_reg,
		1484	.clear_reg = r600_clear_surface_reg,
		1485	},
		1486	.hpd = {
		1487	.init = &evergreen_hpd_init,
		1488	.fini = &evergreen_hpd_fini,
		1489	.sense = &evergreen_hpd_sense,
		1490	.set_polarity = &evergreen_hpd_set_polarity,
		1491	},
		1492	.pm = {
		1493	.misc = &evergreen_pm_misc,
		1494	.prepare = &evergreen_pm_prepare,
		1495	.finish = &evergreen_pm_finish,
		1496	.init_profile = &sumo_pm_init_profile,
		1497	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1498	.get_engine_clock = &radeon_atom_get_engine_clock,
		1499	.set_engine_clock = &radeon_atom_set_engine_clock,
		1500	.get_memory_clock = &radeon_atom_get_memory_clock,
		1501	.set_memory_clock = &radeon_atom_set_memory_clock,
		1502	.get_pcie_lanes = NULL,
		1503	.set_pcie_lanes = NULL,
		1504	.set_clock_gating = NULL,
		1505	},
		1506	.pflip = {
		1507	.pre_page_flip = &evergreen_pre_page_flip,
		1508	.page_flip = &evergreen_page_flip,
		1509	.post_page_flip = &evergreen_post_page_flip,
		1510	},
		1511	};
		1512
1411	int radeon_asic_init(struct radeon_device *rdev)	1513	int radeon_asic_init(struct radeon_device *rdev)
1412	{	1514	{
1413	radeon_register_accessor_init(rdev);	1515	radeon_register_accessor_init(rdev);
@@ -1525,6 +1627,14 @@ int radeon_asic_init(struct radeon_device *rdev)
1525	rdev->num_crtc = 6;	1627	rdev->num_crtc = 6;
1526	rdev->vm_manager.funcs = &cayman_vm_funcs;	1628	rdev->vm_manager.funcs = &cayman_vm_funcs;
1527	break;	1629	break;
		1630	case CHIP_TAHITI:
		1631	case CHIP_PITCAIRN:
		1632	case CHIP_VERDE:
		1633	rdev->asic = &si_asic;
		1634	/* set num crtcs */
		1635	rdev->num_crtc = 6;
		1636	rdev->vm_manager.funcs = &si_vm_funcs;
		1637	break;
1528	default:	1638	default:
1529	/* FIXME: not supported yet */	1639	/* FIXME: not supported yet */
1530	return -EINVAL;	1640	return -EINVAL;


diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 007f0f632a48..3d9f9f1d8f90 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -464,4 +464,26 @@ int evergreen_ib_parse(struct radeon_device rdev, struct radeon_ib ib);
464	/* DCE6 - SI */	464	/* DCE6 - SI */
465	void dce6_bandwidth_update(struct radeon_device *rdev);	465	void dce6_bandwidth_update(struct radeon_device *rdev);
466		466
		467	/*
		468	* si
		469	*/
		470	void si_fence_ring_emit(struct radeon_device *rdev,
		471	struct radeon_fence *fence);
		472	void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
		473	int si_init(struct radeon_device *rdev);
		474	void si_fini(struct radeon_device *rdev);
		475	int si_suspend(struct radeon_device *rdev);
		476	int si_resume(struct radeon_device *rdev);
		477	bool si_gpu_is_lockup(struct radeon_device rdev, struct radeon_ring cp);
		478	int si_asic_reset(struct radeon_device *rdev);
		479	void si_ring_ib_execute(struct radeon_device rdev, struct radeon_ib ib);
		480	int si_irq_set(struct radeon_device *rdev);
		481	int si_irq_process(struct radeon_device *rdev);
		482	int si_vm_init(struct radeon_device *rdev);
		483	void si_vm_fini(struct radeon_device *rdev);
		484	int si_vm_bind(struct radeon_device rdev, struct radeon_vm vm, int id);
		485	void si_vm_unbind(struct radeon_device rdev, struct radeon_vm vm);
		486	void si_vm_tlb_flush(struct radeon_device rdev, struct radeon_vm vm);
		487	int si_ib_parse(struct radeon_device rdev, struct radeon_ib ib);
		488
467	#endif	489	#endif