diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2011-02-16 21:17:04 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2011-02-16 22:55:47 -0500 |
commit | 9f4283f49f0a96a64c5a45fe56f0f8c942885eef (patch) | |
tree | 014b8efe01702cd00ded766dd0b2a5daa15fa36c /drivers/gpu | |
parent | 16e4b8a6e44b8c736c37af370afaa428c3239fb6 (diff) |
drm/radeon/kms: add missing frac fb div flag for dce4+
The fixed ref/post dividers are set by the AdjustPll table
rather than the ss info table on dce4+. Make sure we enable
the fractional feedback dividers when using a fixed post
or ref divider on them as well.
Fixes:
https://bugzilla.kernel.org/show_bug.cgi?id=29272
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Cc: stable@kernel.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/radeon/atombios_crtc.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 095bc507fb16..a4e5e53e0a62 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c | |||
@@ -557,9 +557,9 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, | |||
557 | 557 | ||
558 | /* use recommended ref_div for ss */ | 558 | /* use recommended ref_div for ss */ |
559 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | 559 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
560 | pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; | ||
561 | if (ss_enabled) { | 560 | if (ss_enabled) { |
562 | if (ss->refdiv) { | 561 | if (ss->refdiv) { |
562 | pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; | ||
563 | pll->flags |= RADEON_PLL_USE_REF_DIV; | 563 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
564 | pll->reference_div = ss->refdiv; | 564 | pll->reference_div = ss->refdiv; |
565 | if (ASIC_IS_AVIVO(rdev)) | 565 | if (ASIC_IS_AVIVO(rdev)) |
@@ -662,10 +662,12 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, | |||
662 | index, (uint32_t *)&args); | 662 | index, (uint32_t *)&args); |
663 | adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; | 663 | adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; |
664 | if (args.v3.sOutput.ucRefDiv) { | 664 | if (args.v3.sOutput.ucRefDiv) { |
665 | pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; | ||
665 | pll->flags |= RADEON_PLL_USE_REF_DIV; | 666 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
666 | pll->reference_div = args.v3.sOutput.ucRefDiv; | 667 | pll->reference_div = args.v3.sOutput.ucRefDiv; |
667 | } | 668 | } |
668 | if (args.v3.sOutput.ucPostDiv) { | 669 | if (args.v3.sOutput.ucPostDiv) { |
670 | pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; | ||
669 | pll->flags |= RADEON_PLL_USE_POST_DIV; | 671 | pll->flags |= RADEON_PLL_USE_POST_DIV; |
670 | pll->post_div = args.v3.sOutput.ucPostDiv; | 672 | pll->post_div = args.v3.sOutput.ucPostDiv; |
671 | } | 673 | } |