aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu
diff options
context:
space:
mode:
authorAlex Deucher <alexdeucher@gmail.com>2010-07-27 11:20:54 -0400
committerDave Airlie <airlied@redhat.com>2010-08-01 20:07:39 -0400
commit43a7d2d104f26700c0cc070e5a317a51cd1b46c1 (patch)
treef57d220f6d74cc9ce9263e92bfd9da08d7ccc945 /drivers/gpu
parentd0623a3e74610aff0b984d68bbc027a7e511e686 (diff)
drm/radeon: group r6xx/r7xx newly sequential blit state
group state that is emitted sequentially into fewer packets. This saves a number of dwords. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_shaders.c238
1 files changed, 35 insertions, 203 deletions
diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.c b/drivers/gpu/drm/radeon/r600_blit_shaders.c
index 9a0c947b342c..762b81cb6bd3 100644
--- a/drivers/gpu/drm/radeon/r600_blit_shaders.c
+++ b/drivers/gpu/drm/radeon/r600_blit_shaders.c
@@ -109,22 +109,13 @@ const u32 r6xx_default_state[] =
109 0x00000351, 109 0x00000351,
110 0x0000aa00, /* DB_ALPHA_TO_MASK */ 110 0x0000aa00, /* DB_ALPHA_TO_MASK */
111 111
112 0xc0036900, 112 0xc00f6900,
113 0x00000100, 113 0x00000100,
114 0x00000800, /* VGT_MAX_VTX_INDX */ 114 0x00000800, /* VGT_MAX_VTX_INDX */
115 0x00000000, /* VGT_MIN_VTX_INDX */ 115 0x00000000, /* VGT_MIN_VTX_INDX */
116 0x00000000, /* VGT_INDX_OFFSET */ 116 0x00000000, /* VGT_INDX_OFFSET */
117
118 0xc0016900,
119 0x00000103,
120 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ 117 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
121
122 0xc0016900,
123 0x00000104,
124 0x00000000, /* SX_ALPHA_TEST_CONTROL */ 118 0x00000000, /* SX_ALPHA_TEST_CONTROL */
125
126 0xc0076900,
127 0x00000105,
128 0x00000000, /* CB_BLEND_RED */ 119 0x00000000, /* CB_BLEND_RED */
129 0x00000000, 120 0x00000000,
130 0x00000000, 121 0x00000000,
@@ -132,16 +123,19 @@ const u32 r6xx_default_state[] =
132 0x00000000, /* CB_FOG_RED */ 123 0x00000000, /* CB_FOG_RED */
133 0x00000000, 124 0x00000000,
134 0x00000000, 125 0x00000000,
135
136 0xc0026900,
137 0x0000010c,
138 0x00000000, /* DB_STENCILREFMASK */ 126 0x00000000, /* DB_STENCILREFMASK */
139 0x00000000, /* DB_STENCILREFMASK_BF */ 127 0x00000000, /* DB_STENCILREFMASK_BF */
140
141 0xc0016900,
142 0x0000010e,
143 0x00000000, /* SX_ALPHA_REF */ 128 0x00000000, /* SX_ALPHA_REF */
144 129
130 0xc0066900,
131 0x0000010f,
132 0x00000000, /* PA_CL_VPORT_XSCALE */
133 0x00000000,
134 0x00000000,
135 0x00000000,
136 0x00000000,
137 0x00000000,
138
145 0xc0046900, 139 0xc0046900,
146 0x0000030c, 140 0x0000030c,
147 0x01000000, /* CB_CLRCMP_CNTL */ 141 0x01000000, /* CB_CLRCMP_CNTL */
@@ -240,41 +234,20 @@ const u32 r6xx_default_state[] =
240 0x00000000, 234 0x00000000,
241 0x3f800000, 235 0x3f800000,
242 236
243 0xc0016900, 237 0xc0026900,
244 0x00000292, 238 0x00000292,
245 0x00000000, /* PA_SC_MPASS_PS_CNTL */ 239 0x00000000, /* PA_SC_MPASS_PS_CNTL */
246
247 0xc0016900,
248 0x00000293,
249 0x00004010, /* PA_SC_MODE_CNTL */ 240 0x00004010, /* PA_SC_MODE_CNTL */
250 241
251 0xc0066900, 242 0xc0096900,
252 0x0000010f,
253 0x00000000, /* PA_CL_VPORT_0_XSCALE */
254 0x00000000,
255 0x00000000,
256 0x00000000,
257 0x00000000,
258 0x00000000,
259
260 0xc0026900,
261 0x00000300, 243 0x00000300,
262 0x00000000, /* PA_SC_LINE_CNTL */ 244 0x00000000, /* PA_SC_LINE_CNTL */
263 0x00000000, /* PA_SC_AA_CONFIG */ 245 0x00000000, /* PA_SC_AA_CONFIG */
264
265 0xc0016900,
266 0x00000302,
267 0x0000002d, /* PA_SU_VTX_CNTL */ 246 0x0000002d, /* PA_SU_VTX_CNTL */
268
269 0xc0046900,
270 0x00000303,
271 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ 247 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
272 0x3f800000, 248 0x3f800000,
273 0x3f800000, 249 0x3f800000,
274 0x3f800000, 250 0x3f800000,
275
276 0xc0026900,
277 0x00000307,
278 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */ 251 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
279 0x00000000, 252 0x00000000,
280 253
@@ -282,28 +255,13 @@ const u32 r6xx_default_state[] =
282 0x00000312, 255 0x00000312,
283 0xffffffff, /* PA_SC_AA_MASK */ 256 0xffffffff, /* PA_SC_AA_MASK */
284 257
285 0xc0016900, 258 0xc0066900,
286 0x0000037e, 259 0x0000037e,
287 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ 260 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
288
289 0xc0016900,
290 0x0000037f,
291 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */ 261 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
292
293 0xc0016900,
294 0x00000380,
295 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */ 262 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
296
297 0xc0016900,
298 0x00000381,
299 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */ 263 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
300
301 0xc0016900,
302 0x00000382,
303 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */ 264 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
304
305 0xc0016900,
306 0x00000383,
307 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */ 265 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
308 266
309 0xc0046900, 267 0xc0046900,
@@ -330,29 +288,14 @@ const u32 r6xx_default_state[] =
330 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ 288 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
331 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */ 289 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
332 290
333 0xc0026900, 291 0xc0116900,
334 0x00000280, 292 0x00000280,
335 0x00000000, /* PA_SU_POINT_SIZE */ 293 0x00000000, /* PA_SU_POINT_SIZE */
336 0x00000000, /* PA_SU_POINT_MINMAX */ 294 0x00000000, /* PA_SU_POINT_MINMAX */
337
338 0xc0016900,
339 0x00000282,
340 0x00000008, /* PA_SU_LINE_CNTL */ 295 0x00000008, /* PA_SU_LINE_CNTL */
341
342 0xc0016900,
343 0x00000283,
344 0x00000000, /* PA_SC_LINE_STIPPLE */ 296 0x00000000, /* PA_SC_LINE_STIPPLE */
345
346 0xc0016900,
347 0x00000284,
348 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ 297 0x00000000, /* VGT_OUTPUT_PATH_CNTL */
349
350 0xc0016900,
351 0x00000285,
352 0x00000000, /* VGT_HOS_CNTL */ 298 0x00000000, /* VGT_HOS_CNTL */
353
354 0xc00a6900,
355 0x00000286,
356 0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */ 299 0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
357 0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */ 300 0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
358 0x00000000, /* VGT_HOS_REUSE_DEPTH */ 301 0x00000000, /* VGT_HOS_REUSE_DEPTH */
@@ -363,9 +306,6 @@ const u32 r6xx_default_state[] =
363 0x00000000, /* VGT_GROUP_VECT_1_CNTL */ 306 0x00000000, /* VGT_GROUP_VECT_1_CNTL */
364 0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */ 307 0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
365 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */ 308 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
366
367 0xc0016900,
368 0x00000290,
369 0x00000000, /* VGT_GS_MODE */ 309 0x00000000, /* VGT_GS_MODE */
370 310
371 0xc0016900, 311 0xc0016900,
@@ -386,37 +326,19 @@ const u32 r6xx_default_state[] =
386 0x000002c8, 326 0x000002c8,
387 0x00000000, /* VGT_STRMOUT_BUFFER_EN */ 327 0x00000000, /* VGT_STRMOUT_BUFFER_EN */
388 328
389 0xc0016900, 329 0xc0076900,
390 0x00000202, 330 0x00000202,
391 0x00cc0000, /* CB_COLOR_CONTROL */ 331 0x00cc0000, /* CB_COLOR_CONTROL */
392
393 0xc0016900,
394 0x00000203,
395 0x00000210, /* DB_SHADER_CNTL */ 332 0x00000210, /* DB_SHADER_CNTL */
396
397 0xc0016900,
398 0x00000204,
399 0x00010000, /* PA_CL_CLIP_CNTL */ 333 0x00010000, /* PA_CL_CLIP_CNTL */
400
401 0xc0016900,
402 0x00000205,
403 0x00000244, /* PA_SU_SC_MODE_CNTL */ 334 0x00000244, /* PA_SU_SC_MODE_CNTL */
404
405 0xc0016900,
406 0x00000206,
407 0x00000100, /* PA_CL_VTE_CNTL */ 335 0x00000100, /* PA_CL_VTE_CNTL */
408
409 0xc0026900,
410 0x00000207,
411 0x00000000, /* PA_CL_VS_OUT_CNTL */ 336 0x00000000, /* PA_CL_VS_OUT_CNTL */
412 0x00000000, /* PA_CL_NANINF_CNTL */ 337 0x00000000, /* PA_CL_NANINF_CNTL */
413 338
414 0xc0016900, 339 0xc0026900,
415 0x0000008e, 340 0x0000008e,
416 0x0000000f, /* CB_TARGET_MASK */ 341 0x0000000f, /* CB_TARGET_MASK */
417
418 0xc0016900,
419 0x0000008f,
420 0x0000000f, /* CB_SHADER_MASK */ 342 0x0000000f, /* CB_SHADER_MASK */
421 343
422 0xc0016900, 344 0xc0016900,
@@ -431,21 +353,12 @@ const u32 r6xx_default_state[] =
431 0x00000191, 353 0x00000191,
432 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */ 354 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
433 355
434 0xc0016900, 356 0xc0056900,
435 0x000001b1, 357 0x000001b1,
436 0x00000000, /* SPI_VS_OUT_CONFIG */ 358 0x00000000, /* SPI_VS_OUT_CONFIG */
437
438 0xc0016900,
439 0x000001b2,
440 0x00000000, /* SPI_THREAD_GROUPING */ 359 0x00000000, /* SPI_THREAD_GROUPING */
441
442 0xc0026900,
443 0x000001b3,
444 0x00000001, /* SPI_PS_IN_CONTROL_0 */ 360 0x00000001, /* SPI_PS_IN_CONTROL_0 */
445 0x00000000, /* SPI_PS_IN_CONTROL_1 */ 361 0x00000000, /* SPI_PS_IN_CONTROL_1 */
446
447 0xc0016900,
448 0x000001b5,
449 0x00000000, /* SPI_INTERP_CONTROL_0 */ 362 0x00000000, /* SPI_INTERP_CONTROL_0 */
450 363
451 0xc0036e00, /* SET_SAMPLER */ 364 0xc0036e00, /* SET_SAMPLER */
@@ -524,36 +437,33 @@ const u32 r7xx_default_state[] =
524 0x00000351, 437 0x00000351,
525 0x0000aa00, /* DB_ALPHA_TO_MASK */ 438 0x0000aa00, /* DB_ALPHA_TO_MASK */
526 439
527 0xc0036900, 440 0xc0096900,
528 0x00000100, 441 0x00000100,
529 0x00000800, /* VGT_MAX_VTX_INDX */ 442 0x00000800, /* VGT_MAX_VTX_INDX */
530 0x00000000, /* VGT_MIN_VTX_INDX */ 443 0x00000000, /* VGT_MIN_VTX_INDX */
531 0x00000000, /* VGT_INDX_OFFSET */ 444 0x00000000, /* VGT_INDX_OFFSET */
532
533 0xc0016900,
534 0x00000103,
535 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ 445 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
536
537 0xc0016900,
538 0x00000104,
539 0x00000000, /* SX_ALPHA_TEST_CONTROL */ 446 0x00000000, /* SX_ALPHA_TEST_CONTROL */
540
541 0xc0046900,
542 0x00000105,
543 0x00000000, /* CB_BLEND_RED */ 447 0x00000000, /* CB_BLEND_RED */
544 0x00000000, 448 0x00000000,
545 0x00000000, 449 0x00000000,
546 0x00000000, 450 0x00000000,
547 451
548 0xc0026900, 452 0xc0036900,
549 0x0000010c, 453 0x0000010c,
550 0x00000000, /* DB_STENCILREFMASK */ 454 0x00000000, /* DB_STENCILREFMASK */
551 0x00000000, /* DB_STENCILREFMASK_BF */ 455 0x00000000, /* DB_STENCILREFMASK_BF */
552
553 0xc0016900,
554 0x0000010e,
555 0x00000000, /* SX_ALPHA_REF */ 456 0x00000000, /* SX_ALPHA_REF */
556 457
458 0xc0066900,
459 0x0000010f,
460 0x00000000, /* PA_CL_VPORT_XSCALE */
461 0x00000000,
462 0x00000000,
463 0x00000000,
464 0x00000000,
465 0x00000000,
466
557 0xc0046900, 467 0xc0046900,
558 0x0000030c, /* CB_CLRCMP_CNTL */ 468 0x0000030c, /* CB_CLRCMP_CNTL */
559 0x01000000, 469 0x01000000,
@@ -645,41 +555,20 @@ const u32 r7xx_default_state[] =
645 0x00000000, 555 0x00000000,
646 0x3f800000, 556 0x3f800000,
647 557
648 0xc0016900, 558 0xc0026900,
649 0x00000292, 559 0x00000292,
650 0x00000000, /* PA_SC_MPASS_PS_CNTL */ 560 0x00000000, /* PA_SC_MPASS_PS_CNTL */
651
652 0xc0016900,
653 0x00000293,
654 0x00514000, /* PA_SC_MODE_CNTL */ 561 0x00514000, /* PA_SC_MODE_CNTL */
655 562
656 0xc0066900, 563 0xc0096900,
657 0x0000010f,
658 0x00000000, /* PA_CL_VPORT_0_XSCALE */
659 0x00000000,
660 0x00000000,
661 0x00000000,
662 0x00000000,
663 0x00000000,
664
665 0xc0026900,
666 0x00000300, 564 0x00000300,
667 0x00000000, /* PA_SC_LINE_CNTL */ 565 0x00000000, /* PA_SC_LINE_CNTL */
668 0x00000000, /* PA_SC_AA_CONFIG */ 566 0x00000000, /* PA_SC_AA_CONFIG */
669
670 0xc0016900,
671 0x00000302,
672 0x0000002d, /* PA_SU_VTX_CNTL */ 567 0x0000002d, /* PA_SU_VTX_CNTL */
673
674 0xc0046900,
675 0x00000303,
676 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ 568 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
677 0x3f800000, 569 0x3f800000,
678 0x3f800000, 570 0x3f800000,
679 0x3f800000, 571 0x3f800000,
680
681 0xc0026900,
682 0x00000307,
683 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */ 572 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
684 0x00000000, 573 0x00000000,
685 574
@@ -687,28 +576,13 @@ const u32 r7xx_default_state[] =
687 0x00000312, 576 0x00000312,
688 0xffffffff, /* PA_SC_AA_MASK */ 577 0xffffffff, /* PA_SC_AA_MASK */
689 578
690 0xc0016900, 579 0xc0066900,
691 0x0000037e, 580 0x0000037e,
692 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ 581 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
693
694 0xc0016900,
695 0x0000037f,
696 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */ 582 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
697
698 0xc0016900,
699 0x00000380,
700 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */ 583 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
701
702 0xc0016900,
703 0x00000381,
704 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */ 584 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
705
706 0xc0016900,
707 0x00000382,
708 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */ 585 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
709
710 0xc0016900,
711 0x00000383,
712 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */ 586 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
713 587
714 0xc0046900, 588 0xc0046900,
@@ -735,25 +609,13 @@ const u32 r7xx_default_state[] =
735 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ 609 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
736 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */ 610 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
737 611
738 0xc0026900, 612 0xc0116900,
739 0x00000280, 613 0x00000280,
740 0x00000000, /* PA_SU_POINT_SIZE */ 614 0x00000000, /* PA_SU_POINT_SIZE */
741 0x00000000, /* PA_SU_POINT_MINMAX */ 615 0x00000000, /* PA_SU_POINT_MINMAX */
742
743 0xc0016900,
744 0x00000282,
745 0x00000008, /* PA_SU_LINE_CNTL */ 616 0x00000008, /* PA_SU_LINE_CNTL */
746
747 0xc0016900,
748 0x00000283,
749 0x00000000, /* PA_SC_LINE_STIPPLE */ 617 0x00000000, /* PA_SC_LINE_STIPPLE */
750
751 0xc0016900,
752 0x00000284,
753 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ 618 0x00000000, /* VGT_OUTPUT_PATH_CNTL */
754
755 0xc00b6900,
756 0x00000285,
757 0x00000000, /* VGT_HOS_CNTL */ 619 0x00000000, /* VGT_HOS_CNTL */
758 0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */ 620 0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
759 0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */ 621 0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
@@ -765,9 +627,6 @@ const u32 r7xx_default_state[] =
765 0x00000000, /* VGT_GROUP_VECT_1_CNTL */ 627 0x00000000, /* VGT_GROUP_VECT_1_CNTL */
766 0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */ 628 0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
767 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */ 629 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
768
769 0xc0016900,
770 0x00000290,
771 0x00000000, /* VGT_GS_MODE */ 630 0x00000000, /* VGT_GS_MODE */
772 631
773 0xc0016900, 632 0xc0016900,
@@ -788,37 +647,19 @@ const u32 r7xx_default_state[] =
788 0x000002c8, 647 0x000002c8,
789 0x00000000, /* VGT_STRMOUT_BUFFER_EN */ 648 0x00000000, /* VGT_STRMOUT_BUFFER_EN */
790 649
791 0xc0016900, 650 0xc0076900,
792 0x00000202, 651 0x00000202,
793 0x00cc0000, /* CB_COLOR_CONTROL */ 652 0x00cc0000, /* CB_COLOR_CONTROL */
794
795 0xc0016900,
796 0x00000203,
797 0x00000210, /* DB_SHADER_CNTL */ 653 0x00000210, /* DB_SHADER_CNTL */
798
799 0xc0016900,
800 0x00000204,
801 0x00010000, /* PA_CL_CLIP_CNTL */ 654 0x00010000, /* PA_CL_CLIP_CNTL */
802
803 0xc0016900,
804 0x00000205,
805 0x00000244, /* PA_SU_SC_MODE_CNTL */ 655 0x00000244, /* PA_SU_SC_MODE_CNTL */
806
807 0xc0016900,
808 0x00000206,
809 0x00000100, /* PA_CL_VTE_CNTL */ 656 0x00000100, /* PA_CL_VTE_CNTL */
810
811 0xc0026900,
812 0x00000207,
813 0x00000000, /* PA_CL_VS_OUT_CNTL */ 657 0x00000000, /* PA_CL_VS_OUT_CNTL */
814 0x00000000, /* PA_CL_NANINF_CNTL */ 658 0x00000000, /* PA_CL_NANINF_CNTL */
815 659
816 0xc0016900, 660 0xc0026900,
817 0x0000008e, 661 0x0000008e,
818 0x0000000f, /* CB_TARGET_MASK */ 662 0x0000000f, /* CB_TARGET_MASK */
819
820 0xc0016900,
821 0x0000008f,
822 0x0000000f, /* CB_SHADER_MASK */ 663 0x0000000f, /* CB_SHADER_MASK */
823 664
824 0xc0016900, 665 0xc0016900,
@@ -833,21 +674,12 @@ const u32 r7xx_default_state[] =
833 0x00000191, 674 0x00000191,
834 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */ 675 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
835 676
836 0xc0016900, 677 0xc0056900,
837 0x000001b1, 678 0x000001b1,
838 0x00000000, /* SPI_VS_OUT_CONFIG */ 679 0x00000000, /* SPI_VS_OUT_CONFIG */
839
840 0xc0016900,
841 0x000001b2,
842 0x00000001, /* SPI_THREAD_GROUPING */ 680 0x00000001, /* SPI_THREAD_GROUPING */
843
844 0xc0026900,
845 0x000001b3,
846 0x00000001, /* SPI_PS_IN_CONTROL_0 */ 681 0x00000001, /* SPI_PS_IN_CONTROL_0 */
847 0x00000000, /* SPI_PS_IN_CONTROL_1 */ 682 0x00000000, /* SPI_PS_IN_CONTROL_1 */
848
849 0xc0016900,
850 0x000001b5,
851 0x00000000, /* SPI_INTERP_CONTROL_0 */ 683 0x00000000, /* SPI_INTERP_CONTROL_0 */
852 684
853 0xc0036e00, /* SET_SAMPLER */ 685 0xc0036e00, /* SET_SAMPLER */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 11:05:24 -0500