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authorAlex Deucher <alexdeucher@gmail.com>2008-10-16 03:12:02 -0400
committerDave Airlie <airlied@linux.ie>2008-10-17 17:10:54 -0400
commitf0738e92403466d45cfb5008da668260c77fff4b (patch)
tree0f519b135932eda1fe37541e51099c419a8398af /drivers/gpu
parentb612eda98e4b4bae4c98a863f039bc89425f9039 (diff)
drm/radeon: add support for RS740 IGP chipsets.
This adds support for the HS2100 IGP chipset. Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/radeon_cp.c24
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.h4
2 files changed, 19 insertions, 9 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index 6157cd4bb436..e6e0c2933efd 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -71,7 +71,8 @@ static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
71 71
72static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 72static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
73{ 73{
74 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) 74 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
75 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
75 return RS690_READ_MCIND(dev_priv, addr); 76 return RS690_READ_MCIND(dev_priv, addr);
76 else 77 else
77 return RS480_READ_MCIND(dev_priv, addr); 78 return RS480_READ_MCIND(dev_priv, addr);
@@ -82,7 +83,8 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
82 83
83 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 84 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
84 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); 85 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
85 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) 86 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
87 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
86 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); 88 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
87 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 89 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
88 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); 90 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
@@ -94,7 +96,8 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
94{ 96{
95 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 97 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
96 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); 98 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
97 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) 99 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
100 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
98 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); 101 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
99 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 102 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
100 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); 103 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
@@ -106,7 +109,8 @@ static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_lo
106{ 109{
107 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 110 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
108 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); 111 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
109 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) 112 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
113 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
110 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); 114 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
111 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 115 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
112 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); 116 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
@@ -122,7 +126,8 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
122 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) { 126 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
123 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo); 127 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
124 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi); 128 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
125 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { 129 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
130 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
126 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo); 131 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
127 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi); 132 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
128 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) { 133 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
@@ -364,8 +369,9 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
364 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 369 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
365 R420_cp_microcode[i][0]); 370 R420_cp_microcode[i][0]);
366 } 371 }
367 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { 372 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
368 DRM_INFO("Loading RS690 Microcode\n"); 373 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
374 DRM_INFO("Loading RS690/RS740 Microcode\n");
369 for (i = 0; i < 256; i++) { 375 for (i = 0; i < 256; i++) {
370 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 376 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
371 RS690_cp_microcode[i][1]); 377 RS690_cp_microcode[i][1]);
@@ -720,7 +726,8 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
720 dev_priv->gart_size); 726 dev_priv->gart_size);
721 727
722 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL); 728 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
723 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) 729 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
730 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
724 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN | 731 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
725 RS690_BLOCK_GFX_D3_EN)); 732 RS690_BLOCK_GFX_D3_EN));
726 else 733 else
@@ -813,6 +820,7 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
813 u32 tmp; 820 u32 tmp;
814 821
815 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 822 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
823 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
816 (dev_priv->flags & RADEON_IS_IGPGART)) { 824 (dev_priv->flags & RADEON_IS_IGPGART)) {
817 radeon_set_igpgart(dev_priv, on); 825 radeon_set_igpgart(dev_priv, on);
818 return; 826 return;
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index d7e9c6cc6a1a..9d752bc0602b 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -125,6 +125,7 @@ enum radeon_family {
125 CHIP_RV410, 125 CHIP_RV410,
126 CHIP_RS480, 126 CHIP_RS480,
127 CHIP_RS690, 127 CHIP_RS690,
128 CHIP_RS740,
128 CHIP_RV515, 129 CHIP_RV515,
129 CHIP_R520, 130 CHIP_R520,
130 CHIP_RV530, 131 CHIP_RV530,
@@ -1207,7 +1208,8 @@ do { \
1207 1208
1208#define IGP_WRITE_MCIND(addr, val) \ 1209#define IGP_WRITE_MCIND(addr, val) \
1209do { \ 1210do { \
1210 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \ 1211 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \
1212 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \
1211 RS690_WRITE_MCIND(addr, val); \ 1213 RS690_WRITE_MCIND(addr, val); \
1212 else \ 1214 else \
1213 RS480_WRITE_MCIND(addr, val); \ 1215 RS480_WRITE_MCIND(addr, val); \