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authorIngo Molnar <mingo@elte.hu>2008-11-20 03:02:39 -0500
committerIngo Molnar <mingo@elte.hu>2008-11-20 03:02:39 -0500
commitfbc2a06056c9aa3cb8c44bf1cfeb1d260e229e5c (patch)
treefeb2a1c13ad3dff5a8c7ab3c0265e8eca7a0c5a3 /drivers/gpu
parenta3d732f93785da17e0137210deadb4616f5536fc (diff)
parentee2f6cc7f9ea2542ad46070ed62ba7aa04d08871 (diff)
Merge branch 'linus' into x86/uv
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/drm_drv.c10
-rw-r--r--drivers/gpu/drm/drm_fops.c2
-rw-r--r--drivers/gpu/drm/drm_irq.c80
-rw-r--r--drivers/gpu/drm/drm_lock.c9
-rw-r--r--drivers/gpu/drm/drm_stub.c1
-rw-r--r--drivers/gpu/drm/i915/Makefile3
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c17
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h31
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c204
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c383
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h3
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_cp.c30
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.h14
14 files changed, 192 insertions, 604 deletions
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 96f416afc3f6..3ab1e9cc4692 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -266,11 +266,19 @@ int drm_init(struct drm_driver *driver)
266 for (i = 0; driver->pci_driver.id_table[i].vendor != 0; i++) { 266 for (i = 0; driver->pci_driver.id_table[i].vendor != 0; i++) {
267 pid = (struct pci_device_id *)&driver->pci_driver.id_table[i]; 267 pid = (struct pci_device_id *)&driver->pci_driver.id_table[i];
268 268
269 /* Loop around setting up a DRM device for each PCI device
270 * matching our ID and device class. If we had the internal
271 * function that pci_get_subsys and pci_get_class used, we'd
272 * be able to just pass pid in instead of doing a two-stage
273 * thing.
274 */
269 pdev = NULL; 275 pdev = NULL;
270 /* pass back in pdev to account for multiple identical cards */
271 while ((pdev = 276 while ((pdev =
272 pci_get_subsys(pid->vendor, pid->device, pid->subvendor, 277 pci_get_subsys(pid->vendor, pid->device, pid->subvendor,
273 pid->subdevice, pdev)) != NULL) { 278 pid->subdevice, pdev)) != NULL) {
279 if ((pdev->class & pid->class_mask) != pid->class)
280 continue;
281
274 /* stealth mode requires a manual probe */ 282 /* stealth mode requires a manual probe */
275 pci_dev_get(pdev); 283 pci_dev_get(pdev);
276 drm_get_dev(pdev, pid, driver); 284 drm_get_dev(pdev, pid, driver);
diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
index 0d46627663b1..78eeed5caaff 100644
--- a/drivers/gpu/drm/drm_fops.c
+++ b/drivers/gpu/drm/drm_fops.c
@@ -406,8 +406,6 @@ int drm_release(struct inode *inode, struct file *filp)
406 if (dev->driver->driver_features & DRIVER_GEM) 406 if (dev->driver->driver_features & DRIVER_GEM)
407 drm_gem_release(dev, file_priv); 407 drm_gem_release(dev, file_priv);
408 408
409 drm_fasync(-1, filp, 0);
410
411 mutex_lock(&dev->ctxlist_mutex); 409 mutex_lock(&dev->ctxlist_mutex);
412 if (!list_empty(&dev->ctxlist)) { 410 if (!list_empty(&dev->ctxlist)) {
413 struct drm_ctx_list *pos, *n; 411 struct drm_ctx_list *pos, *n;
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index 212a94f715b2..15c8dabc3e97 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -280,8 +280,6 @@ int drm_irq_uninstall(struct drm_device * dev)
280 280
281 drm_vblank_cleanup(dev); 281 drm_vblank_cleanup(dev);
282 282
283 dev->locked_tasklet_func = NULL;
284
285 return 0; 283 return 0;
286} 284}
287EXPORT_SYMBOL(drm_irq_uninstall); 285EXPORT_SYMBOL(drm_irq_uninstall);
@@ -699,81 +697,3 @@ void drm_handle_vblank(struct drm_device *dev, int crtc)
699 drm_vbl_send_signals(dev, crtc); 697 drm_vbl_send_signals(dev, crtc);
700} 698}
701EXPORT_SYMBOL(drm_handle_vblank); 699EXPORT_SYMBOL(drm_handle_vblank);
702
703/**
704 * Tasklet wrapper function.
705 *
706 * \param data DRM device in disguise.
707 *
708 * Attempts to grab the HW lock and calls the driver callback on success. On
709 * failure, leave the lock marked as contended so the callback can be called
710 * from drm_unlock().
711 */
712static void drm_locked_tasklet_func(unsigned long data)
713{
714 struct drm_device *dev = (struct drm_device *)data;
715 unsigned long irqflags;
716 void (*tasklet_func)(struct drm_device *);
717
718 spin_lock_irqsave(&dev->tasklet_lock, irqflags);
719 tasklet_func = dev->locked_tasklet_func;
720 spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
721
722 if (!tasklet_func ||
723 !drm_lock_take(&dev->lock,
724 DRM_KERNEL_CONTEXT)) {
725 return;
726 }
727
728 dev->lock.lock_time = jiffies;
729 atomic_inc(&dev->counts[_DRM_STAT_LOCKS]);
730
731 spin_lock_irqsave(&dev->tasklet_lock, irqflags);
732 tasklet_func = dev->locked_tasklet_func;
733 dev->locked_tasklet_func = NULL;
734 spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
735
736 if (tasklet_func != NULL)
737 tasklet_func(dev);
738
739 drm_lock_free(&dev->lock,
740 DRM_KERNEL_CONTEXT);
741}
742
743/**
744 * Schedule a tasklet to call back a driver hook with the HW lock held.
745 *
746 * \param dev DRM device.
747 * \param func Driver callback.
748 *
749 * This is intended for triggering actions that require the HW lock from an
750 * interrupt handler. The lock will be grabbed ASAP after the interrupt handler
751 * completes. Note that the callback may be called from interrupt or process
752 * context, it must not make any assumptions about this. Also, the HW lock will
753 * be held with the kernel context or any client context.
754 */
755void drm_locked_tasklet(struct drm_device *dev, void (*func)(struct drm_device *))
756{
757 unsigned long irqflags;
758 static DECLARE_TASKLET(drm_tasklet, drm_locked_tasklet_func, 0);
759
760 if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ) ||
761 test_bit(TASKLET_STATE_SCHED, &drm_tasklet.state))
762 return;
763
764 spin_lock_irqsave(&dev->tasklet_lock, irqflags);
765
766 if (dev->locked_tasklet_func) {
767 spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
768 return;
769 }
770
771 dev->locked_tasklet_func = func;
772
773 spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
774
775 drm_tasklet.data = (unsigned long)dev;
776
777 tasklet_hi_schedule(&drm_tasklet);
778}
779EXPORT_SYMBOL(drm_locked_tasklet);
diff --git a/drivers/gpu/drm/drm_lock.c b/drivers/gpu/drm/drm_lock.c
index 888159e03d26..1cfa72031f8f 100644
--- a/drivers/gpu/drm/drm_lock.c
+++ b/drivers/gpu/drm/drm_lock.c
@@ -154,8 +154,6 @@ int drm_lock(struct drm_device *dev, void *data, struct drm_file *file_priv)
154int drm_unlock(struct drm_device *dev, void *data, struct drm_file *file_priv) 154int drm_unlock(struct drm_device *dev, void *data, struct drm_file *file_priv)
155{ 155{
156 struct drm_lock *lock = data; 156 struct drm_lock *lock = data;
157 unsigned long irqflags;
158 void (*tasklet_func)(struct drm_device *);
159 157
160 if (lock->context == DRM_KERNEL_CONTEXT) { 158 if (lock->context == DRM_KERNEL_CONTEXT) {
161 DRM_ERROR("Process %d using kernel context %d\n", 159 DRM_ERROR("Process %d using kernel context %d\n",
@@ -163,13 +161,6 @@ int drm_unlock(struct drm_device *dev, void *data, struct drm_file *file_priv)
163 return -EINVAL; 161 return -EINVAL;
164 } 162 }
165 163
166 spin_lock_irqsave(&dev->tasklet_lock, irqflags);
167 tasklet_func = dev->locked_tasklet_func;
168 dev->locked_tasklet_func = NULL;
169 spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
170 if (tasklet_func != NULL)
171 tasklet_func(dev);
172
173 atomic_inc(&dev->counts[_DRM_STAT_UNLOCKS]); 164 atomic_inc(&dev->counts[_DRM_STAT_UNLOCKS]);
174 165
175 /* kernel_context_switch isn't used by any of the x86 drm 166 /* kernel_context_switch isn't used by any of the x86 drm
diff --git a/drivers/gpu/drm/drm_stub.c b/drivers/gpu/drm/drm_stub.c
index 141e33004a76..66c96ec66672 100644
--- a/drivers/gpu/drm/drm_stub.c
+++ b/drivers/gpu/drm/drm_stub.c
@@ -92,7 +92,6 @@ static int drm_fill_in_dev(struct drm_device * dev, struct pci_dev *pdev,
92 92
93 spin_lock_init(&dev->count_lock); 93 spin_lock_init(&dev->count_lock);
94 spin_lock_init(&dev->drw_lock); 94 spin_lock_init(&dev->drw_lock);
95 spin_lock_init(&dev->tasklet_lock);
96 spin_lock_init(&dev->lock.spinlock); 95 spin_lock_init(&dev->lock.spinlock);
97 init_timer(&dev->timer); 96 init_timer(&dev->timer);
98 mutex_init(&dev->struct_mutex); 97 mutex_init(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5ba78e4fd2b5..d8fb5d8ee7ea 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -3,13 +3,14 @@
3# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. 3# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
4 4
5ccflags-y := -Iinclude/drm 5ccflags-y := -Iinclude/drm
6i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o i915_opregion.o \ 6i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \
7 i915_suspend.o \ 7 i915_suspend.o \
8 i915_gem.o \ 8 i915_gem.o \
9 i915_gem_debug.o \ 9 i915_gem_debug.o \
10 i915_gem_proc.o \ 10 i915_gem_proc.o \
11 i915_gem_tiling.o 11 i915_gem_tiling.o
12 12
13i915-$(CONFIG_ACPI) += i915_opregion.o
13i915-$(CONFIG_COMPAT) += i915_ioc32.o 14i915-$(CONFIG_COMPAT) += i915_ioc32.o
14 15
15obj-$(CONFIG_DRM_I915) += i915.o 16obj-$(CONFIG_DRM_I915) += i915.o
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 01de536e0211..0d215e38606a 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -154,6 +154,9 @@ static int i915_dma_cleanup(struct drm_device * dev)
154 if (I915_NEED_GFX_HWS(dev)) 154 if (I915_NEED_GFX_HWS(dev))
155 i915_free_hws(dev); 155 i915_free_hws(dev);
156 156
157 dev_priv->sarea = NULL;
158 dev_priv->sarea_priv = NULL;
159
157 return 0; 160 return 0;
158} 161}
159 162
@@ -442,7 +445,7 @@ static void i915_emit_breadcrumb(struct drm_device *dev)
442 445
443 BEGIN_LP_RING(4); 446 BEGIN_LP_RING(4);
444 OUT_RING(MI_STORE_DWORD_INDEX); 447 OUT_RING(MI_STORE_DWORD_INDEX);
445 OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); 448 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
446 OUT_RING(dev_priv->counter); 449 OUT_RING(dev_priv->counter);
447 OUT_RING(0); 450 OUT_RING(0);
448 ADVANCE_LP_RING(); 451 ADVANCE_LP_RING();
@@ -573,7 +576,7 @@ static int i915_dispatch_flip(struct drm_device * dev)
573 576
574 BEGIN_LP_RING(4); 577 BEGIN_LP_RING(4);
575 OUT_RING(MI_STORE_DWORD_INDEX); 578 OUT_RING(MI_STORE_DWORD_INDEX);
576 OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); 579 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
577 OUT_RING(dev_priv->counter); 580 OUT_RING(dev_priv->counter);
578 OUT_RING(0); 581 OUT_RING(0);
579 ADVANCE_LP_RING(); 582 ADVANCE_LP_RING();
@@ -608,7 +611,6 @@ static int i915_batchbuffer(struct drm_device *dev, void *data,
608 struct drm_file *file_priv) 611 struct drm_file *file_priv)
609{ 612{
610 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 613 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
611 u32 *hw_status = dev_priv->hw_status_page;
612 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) 614 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
613 dev_priv->sarea_priv; 615 dev_priv->sarea_priv;
614 drm_i915_batchbuffer_t *batch = data; 616 drm_i915_batchbuffer_t *batch = data;
@@ -634,7 +636,7 @@ static int i915_batchbuffer(struct drm_device *dev, void *data,
634 mutex_unlock(&dev->struct_mutex); 636 mutex_unlock(&dev->struct_mutex);
635 637
636 if (sarea_priv) 638 if (sarea_priv)
637 sarea_priv->last_dispatch = (int)hw_status[5]; 639 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
638 return ret; 640 return ret;
639} 641}
640 642
@@ -642,7 +644,6 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
642 struct drm_file *file_priv) 644 struct drm_file *file_priv)
643{ 645{
644 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 646 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
645 u32 *hw_status = dev_priv->hw_status_page;
646 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) 647 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
647 dev_priv->sarea_priv; 648 dev_priv->sarea_priv;
648 drm_i915_cmdbuffer_t *cmdbuf = data; 649 drm_i915_cmdbuffer_t *cmdbuf = data;
@@ -670,7 +671,7 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
670 } 671 }
671 672
672 if (sarea_priv) 673 if (sarea_priv)
673 sarea_priv->last_dispatch = (int)hw_status[5]; 674 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
674 return 0; 675 return 0;
675} 676}
676 677
@@ -849,8 +850,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
849 * be lost or delayed 850 * be lost or delayed
850 */ 851 */
851 if (!IS_I945G(dev) && !IS_I945GM(dev) && !IS_I965GM(dev)) 852 if (!IS_I945G(dev) && !IS_I945GM(dev) && !IS_I965GM(dev))
852 if (pci_enable_msi(dev->pdev)) 853 pci_enable_msi(dev->pdev);
853 DRM_ERROR("failed to enable MSI\n");
854 854
855 intel_opregion_init(dev); 855 intel_opregion_init(dev);
856 856
@@ -960,6 +960,7 @@ struct drm_ioctl_desc i915_ioctls[] = {
960 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0), 960 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
961 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0), 961 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
962 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0), 962 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
963 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),
963}; 964};
964 965
965int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); 966int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f20ffe17df71..ef1c0b8f8d07 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -31,6 +31,7 @@
31#define _I915_DRV_H_ 31#define _I915_DRV_H_
32 32
33#include "i915_reg.h" 33#include "i915_reg.h"
34#include <linux/io-mapping.h>
34 35
35/* General customization: 36/* General customization:
36 */ 37 */
@@ -87,13 +88,6 @@ struct mem_block {
87 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 88 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
88}; 89};
89 90
90typedef struct _drm_i915_vbl_swap {
91 struct list_head head;
92 drm_drawable_t drw_id;
93 unsigned int pipe;
94 unsigned int sequence;
95} drm_i915_vbl_swap_t;
96
97struct opregion_header; 91struct opregion_header;
98struct opregion_acpi; 92struct opregion_acpi;
99struct opregion_swsci; 93struct opregion_swsci;
@@ -145,10 +139,6 @@ typedef struct drm_i915_private {
145 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 139 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
146 int vblank_pipe; 140 int vblank_pipe;
147 141
148 spinlock_t swaps_lock;
149 drm_i915_vbl_swap_t vbl_swaps;
150 unsigned int swaps_pending;
151
152 struct intel_opregion opregion; 142 struct intel_opregion opregion;
153 143
154 /* Register state */ 144 /* Register state */
@@ -156,6 +146,7 @@ typedef struct drm_i915_private {
156 u32 saveDSPACNTR; 146 u32 saveDSPACNTR;
157 u32 saveDSPBCNTR; 147 u32 saveDSPBCNTR;
158 u32 saveDSPARB; 148 u32 saveDSPARB;
149 u32 saveRENDERSTANDBY;
159 u32 savePIPEACONF; 150 u32 savePIPEACONF;
160 u32 savePIPEBCONF; 151 u32 savePIPEBCONF;
161 u32 savePIPEASRC; 152 u32 savePIPEASRC;
@@ -240,12 +231,11 @@ typedef struct drm_i915_private {
240 u8 saveDACDATA[256*3]; /* 256 3-byte colors */ 231 u8 saveDACDATA[256*3]; /* 256 3-byte colors */
241 u8 saveCR[37]; 232 u8 saveCR[37];
242 233
243 /** Work task for vblank-related ring access */
244 struct work_struct vblank_work;
245
246 struct { 234 struct {
247 struct drm_mm gtt_space; 235 struct drm_mm gtt_space;
248 236
237 struct io_mapping *gtt_mapping;
238
249 /** 239 /**
250 * List of objects currently involved in rendering from the 240 * List of objects currently involved in rendering from the
251 * ringbuffer. 241 * ringbuffer.
@@ -441,7 +431,6 @@ extern int i915_irq_wait(struct drm_device *dev, void *data,
441void i915_user_irq_get(struct drm_device *dev); 431void i915_user_irq_get(struct drm_device *dev);
442void i915_user_irq_put(struct drm_device *dev); 432void i915_user_irq_put(struct drm_device *dev);
443 433
444extern void i915_vblank_work_handler(struct work_struct *work);
445extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 434extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
446extern void i915_driver_irq_preinstall(struct drm_device * dev); 435extern void i915_driver_irq_preinstall(struct drm_device * dev);
447extern int i915_driver_irq_postinstall(struct drm_device *dev); 436extern int i915_driver_irq_postinstall(struct drm_device *dev);
@@ -502,6 +491,8 @@ int i915_gem_set_tiling(struct drm_device *dev, void *data,
502 struct drm_file *file_priv); 491 struct drm_file *file_priv);
503int i915_gem_get_tiling(struct drm_device *dev, void *data, 492int i915_gem_get_tiling(struct drm_device *dev, void *data,
504 struct drm_file *file_priv); 493 struct drm_file *file_priv);
494int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
495 struct drm_file *file_priv);
505void i915_gem_load(struct drm_device *dev); 496void i915_gem_load(struct drm_device *dev);
506int i915_gem_proc_init(struct drm_minor *minor); 497int i915_gem_proc_init(struct drm_minor *minor);
507void i915_gem_proc_cleanup(struct drm_minor *minor); 498void i915_gem_proc_cleanup(struct drm_minor *minor);
@@ -539,11 +530,18 @@ extern int i915_restore_state(struct drm_device *dev);
539extern int i915_save_state(struct drm_device *dev); 530extern int i915_save_state(struct drm_device *dev);
540extern int i915_restore_state(struct drm_device *dev); 531extern int i915_restore_state(struct drm_device *dev);
541 532
533#ifdef CONFIG_ACPI
542/* i915_opregion.c */ 534/* i915_opregion.c */
543extern int intel_opregion_init(struct drm_device *dev); 535extern int intel_opregion_init(struct drm_device *dev);
544extern void intel_opregion_free(struct drm_device *dev); 536extern void intel_opregion_free(struct drm_device *dev);
545extern void opregion_asle_intr(struct drm_device *dev); 537extern void opregion_asle_intr(struct drm_device *dev);
546extern void opregion_enable_asle(struct drm_device *dev); 538extern void opregion_enable_asle(struct drm_device *dev);
539#else
540static inline int intel_opregion_init(struct drm_device *dev) { return 0; }
541static inline void intel_opregion_free(struct drm_device *dev) { return; }
542static inline void opregion_asle_intr(struct drm_device *dev) { return; }
543static inline void opregion_enable_asle(struct drm_device *dev) { return; }
544#endif
547 545
548/** 546/**
549 * Lock test for when it's just for synchronization of ring access. 547 * Lock test for when it's just for synchronization of ring access.
@@ -610,8 +608,9 @@ extern void opregion_enable_asle(struct drm_device *dev);
610 * The area from dword 0x20 to 0x3ff is available for driver usage. 608 * The area from dword 0x20 to 0x3ff is available for driver usage.
611 */ 609 */
612#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 610#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
613#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5) 611#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
614#define I915_GEM_HWS_INDEX 0x20 612#define I915_GEM_HWS_INDEX 0x20
613#define I915_BREADCRUMB_INDEX 0x21
615 614
616extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 615extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
617 616
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 17ae330ff269..6b4a2bd20640 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -79,6 +79,28 @@ i915_gem_init_ioctl(struct drm_device *dev, void *data,
79 return 0; 79 return 0;
80} 80}
81 81
82int
83i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
84 struct drm_file *file_priv)
85{
86 drm_i915_private_t *dev_priv = dev->dev_private;
87 struct drm_i915_gem_get_aperture *args = data;
88 struct drm_i915_gem_object *obj_priv;
89
90 if (!(dev->driver->driver_features & DRIVER_GEM))
91 return -ENODEV;
92
93 args->aper_size = dev->gtt_total;
94 args->aper_available_size = args->aper_size;
95
96 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
97 if (obj_priv->pin_count > 0)
98 args->aper_available_size -= obj_priv->obj->size;
99 }
100
101 return 0;
102}
103
82 104
83/** 105/**
84 * Creates a new mm object and returns a handle to it. 106 * Creates a new mm object and returns a handle to it.
@@ -171,35 +193,50 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
171 return 0; 193 return 0;
172} 194}
173 195
174/* 196/* This is the fast write path which cannot handle
175 * Try to write quickly with an atomic kmap. Return true on success. 197 * page faults in the source data
176 *
177 * If this fails (which includes a partial write), we'll redo the whole
178 * thing with the slow version.
179 *
180 * This is a workaround for the low performance of iounmap (approximate
181 * 10% cpu cost on normal 3D workloads). kmap_atomic on HIGHMEM kernels
182 * happens to let us map card memory without taking IPIs. When the vmap
183 * rework lands we should be able to dump this hack.
184 */ 198 */
185static inline int fast_user_write(unsigned long pfn, char __user *user_data, 199
186 int l, int o) 200static inline int
201fast_user_write(struct io_mapping *mapping,
202 loff_t page_base, int page_offset,
203 char __user *user_data,
204 int length)
187{ 205{
188#ifdef CONFIG_HIGHMEM
189 unsigned long unwritten;
190 char *vaddr_atomic; 206 char *vaddr_atomic;
207 unsigned long unwritten;
191 208
192 vaddr_atomic = kmap_atomic_pfn(pfn, KM_USER0); 209 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
193#if WATCH_PWRITE 210 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
194 DRM_INFO("pwrite i %d o %d l %d pfn %ld vaddr %p\n", 211 user_data, length);
195 i, o, l, pfn, vaddr_atomic); 212 io_mapping_unmap_atomic(vaddr_atomic);
196#endif 213 if (unwritten)
197 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + o, user_data, l); 214 return -EFAULT;
198 kunmap_atomic(vaddr_atomic, KM_USER0); 215 return 0;
199 return !unwritten; 216}
200#else 217
218/* Here's the write path which can sleep for
219 * page faults
220 */
221
222static inline int
223slow_user_write(struct io_mapping *mapping,
224 loff_t page_base, int page_offset,
225 char __user *user_data,
226 int length)
227{
228 char __iomem *vaddr;
229 unsigned long unwritten;
230
231 vaddr = io_mapping_map_wc(mapping, page_base);
232 if (vaddr == NULL)
233 return -EFAULT;
234 unwritten = __copy_from_user(vaddr + page_offset,
235 user_data, length);
236 io_mapping_unmap(vaddr);
237 if (unwritten)
238 return -EFAULT;
201 return 0; 239 return 0;
202#endif
203} 240}
204 241
205static int 242static int
@@ -208,10 +245,12 @@ i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
208 struct drm_file *file_priv) 245 struct drm_file *file_priv)
209{ 246{
210 struct drm_i915_gem_object *obj_priv = obj->driver_private; 247 struct drm_i915_gem_object *obj_priv = obj->driver_private;
248 drm_i915_private_t *dev_priv = dev->dev_private;
211 ssize_t remain; 249 ssize_t remain;
212 loff_t offset; 250 loff_t offset, page_base;
213 char __user *user_data; 251 char __user *user_data;
214 int ret = 0; 252 int page_offset, page_length;
253 int ret;
215 254
216 user_data = (char __user *) (uintptr_t) args->data_ptr; 255 user_data = (char __user *) (uintptr_t) args->data_ptr;
217 remain = args->size; 256 remain = args->size;
@@ -235,57 +274,37 @@ i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
235 obj_priv->dirty = 1; 274 obj_priv->dirty = 1;
236 275
237 while (remain > 0) { 276 while (remain > 0) {
238 unsigned long pfn;
239 int i, o, l;
240
241 /* Operation in this page 277 /* Operation in this page
242 * 278 *
243 * i = page number 279 * page_base = page offset within aperture
244 * o = offset within page 280 * page_offset = offset within page
245 * l = bytes to copy 281 * page_length = bytes to copy for this page
246 */ 282 */
247 i = offset >> PAGE_SHIFT; 283 page_base = (offset & ~(PAGE_SIZE-1));
248 o = offset & (PAGE_SIZE-1); 284 page_offset = offset & (PAGE_SIZE-1);
249 l = remain; 285 page_length = remain;
250 if ((o + l) > PAGE_SIZE) 286 if ((page_offset + remain) > PAGE_SIZE)
251 l = PAGE_SIZE - o; 287 page_length = PAGE_SIZE - page_offset;
252 288
253 pfn = (dev->agp->base >> PAGE_SHIFT) + i; 289 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
254 290 page_offset, user_data, page_length);
255 if (!fast_user_write(pfn, user_data, l, o)) { 291
256 unsigned long unwritten; 292 /* If we get a fault while copying data, then (presumably) our
257 char __iomem *vaddr; 293 * source page isn't available. In this case, use the
258 294 * non-atomic function
259 vaddr = ioremap_wc(pfn << PAGE_SHIFT, PAGE_SIZE); 295 */
260#if WATCH_PWRITE 296 if (ret) {
261 DRM_INFO("pwrite slow i %d o %d l %d " 297 ret = slow_user_write (dev_priv->mm.gtt_mapping,
262 "pfn %ld vaddr %p\n", 298 page_base, page_offset,
263 i, o, l, pfn, vaddr); 299 user_data, page_length);
264#endif 300 if (ret)
265 if (vaddr == NULL) {
266 ret = -EFAULT;
267 goto fail;
268 }
269 unwritten = __copy_from_user(vaddr + o, user_data, l);
270#if WATCH_PWRITE
271 DRM_INFO("unwritten %ld\n", unwritten);
272#endif
273 iounmap(vaddr);
274 if (unwritten) {
275 ret = -EFAULT;
276 goto fail; 301 goto fail;
277 }
278 } 302 }
279 303
280 remain -= l; 304 remain -= page_length;
281 user_data += l; 305 user_data += page_length;
282 offset += l; 306 offset += page_length;
283 } 307 }
284#if WATCH_PWRITE && 1
285 i915_gem_clflush_object(obj);
286 i915_gem_dump_object(obj, args->offset + args->size, __func__, ~0);
287 i915_gem_clflush_object(obj);
288#endif
289 308
290fail: 309fail:
291 i915_gem_object_unpin(obj); 310 i915_gem_object_unpin(obj);
@@ -1436,11 +1455,9 @@ i915_gem_object_set_domain_range(struct drm_gem_object *obj,
1436 read_domains, write_domain); 1455 read_domains, write_domain);
1437 1456
1438 /* Wait on any GPU rendering to the object to be flushed. */ 1457 /* Wait on any GPU rendering to the object to be flushed. */
1439 if (obj->write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) { 1458 ret = i915_gem_object_wait_rendering(obj);
1440 ret = i915_gem_object_wait_rendering(obj); 1459 if (ret)
1441 if (ret) 1460 return ret;
1442 return ret;
1443 }
1444 1461
1445 if (obj_priv->page_cpu_valid == NULL) { 1462 if (obj_priv->page_cpu_valid == NULL) {
1446 obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE, 1463 obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
@@ -1503,12 +1520,12 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
1503 struct drm_i915_gem_exec_object *entry) 1520 struct drm_i915_gem_exec_object *entry)
1504{ 1521{
1505 struct drm_device *dev = obj->dev; 1522 struct drm_device *dev = obj->dev;
1523 drm_i915_private_t *dev_priv = dev->dev_private;
1506 struct drm_i915_gem_relocation_entry reloc; 1524 struct drm_i915_gem_relocation_entry reloc;
1507 struct drm_i915_gem_relocation_entry __user *relocs; 1525 struct drm_i915_gem_relocation_entry __user *relocs;
1508 struct drm_i915_gem_object *obj_priv = obj->driver_private; 1526 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1509 int i, ret; 1527 int i, ret;
1510 uint32_t last_reloc_offset = -1; 1528 void __iomem *reloc_page;
1511 void __iomem *reloc_page = NULL;
1512 1529
1513 /* Choose the GTT offset for our buffer and put it there. */ 1530 /* Choose the GTT offset for our buffer and put it there. */
1514 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); 1531 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
@@ -1631,26 +1648,11 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
1631 * perform. 1648 * perform.
1632 */ 1649 */
1633 reloc_offset = obj_priv->gtt_offset + reloc.offset; 1650 reloc_offset = obj_priv->gtt_offset + reloc.offset;
1634 if (reloc_page == NULL || 1651 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
1635 (last_reloc_offset & ~(PAGE_SIZE - 1)) != 1652 (reloc_offset &
1636 (reloc_offset & ~(PAGE_SIZE - 1))) { 1653 ~(PAGE_SIZE - 1)));
1637 if (reloc_page != NULL)
1638 iounmap(reloc_page);
1639
1640 reloc_page = ioremap_wc(dev->agp->base +
1641 (reloc_offset &
1642 ~(PAGE_SIZE - 1)),
1643 PAGE_SIZE);
1644 last_reloc_offset = reloc_offset;
1645 if (reloc_page == NULL) {
1646 drm_gem_object_unreference(target_obj);
1647 i915_gem_object_unpin(obj);
1648 return -ENOMEM;
1649 }
1650 }
1651
1652 reloc_entry = (uint32_t __iomem *)(reloc_page + 1654 reloc_entry = (uint32_t __iomem *)(reloc_page +
1653 (reloc_offset & (PAGE_SIZE - 1))); 1655 (reloc_offset & (PAGE_SIZE - 1)));
1654 reloc_val = target_obj_priv->gtt_offset + reloc.delta; 1656 reloc_val = target_obj_priv->gtt_offset + reloc.delta;
1655 1657
1656#if WATCH_BUF 1658#if WATCH_BUF
@@ -1659,6 +1661,7 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
1659 readl(reloc_entry), reloc_val); 1661 readl(reloc_entry), reloc_val);
1660#endif 1662#endif
1661 writel(reloc_val, reloc_entry); 1663 writel(reloc_val, reloc_entry);
1664 io_mapping_unmap_atomic(reloc_page);
1662 1665
1663 /* Write the updated presumed offset for this entry back out 1666 /* Write the updated presumed offset for this entry back out
1664 * to the user. 1667 * to the user.
@@ -1674,9 +1677,6 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
1674 drm_gem_object_unreference(target_obj); 1677 drm_gem_object_unreference(target_obj);
1675 } 1678 }
1676 1679
1677 if (reloc_page != NULL)
1678 iounmap(reloc_page);
1679
1680#if WATCH_BUF 1680#if WATCH_BUF
1681 if (0) 1681 if (0)
1682 i915_gem_dump_object(obj, 128, __func__, ~0); 1682 i915_gem_dump_object(obj, 128, __func__, ~0);
@@ -2518,6 +2518,10 @@ i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2518 if (ret != 0) 2518 if (ret != 0)
2519 return ret; 2519 return ret;
2520 2520
2521 dev_priv->mm.gtt_mapping = io_mapping_create_wc(dev->agp->base,
2522 dev->agp->agp_info.aper_size
2523 * 1024 * 1024);
2524
2521 mutex_lock(&dev->struct_mutex); 2525 mutex_lock(&dev->struct_mutex);
2522 BUG_ON(!list_empty(&dev_priv->mm.active_list)); 2526 BUG_ON(!list_empty(&dev_priv->mm.active_list));
2523 BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); 2527 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
@@ -2535,11 +2539,13 @@ int
2535i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 2539i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2536 struct drm_file *file_priv) 2540 struct drm_file *file_priv)
2537{ 2541{
2542 drm_i915_private_t *dev_priv = dev->dev_private;
2538 int ret; 2543 int ret;
2539 2544
2540 ret = i915_gem_idle(dev); 2545 ret = i915_gem_idle(dev);
2541 drm_irq_uninstall(dev); 2546 drm_irq_uninstall(dev);
2542 2547
2548 io_mapping_free(dev_priv->mm.gtt_mapping);
2543 return ret; 2549 return ret;
2544} 2550}
2545 2551
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 26f48932a51e..82752d6177a4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -80,211 +80,6 @@ i915_pipe_enabled(struct drm_device *dev, int pipe)
80 return 0; 80 return 0;
81} 81}
82 82
83/**
84 * Emit blits for scheduled buffer swaps.
85 *
86 * This function will be called with the HW lock held.
87 * Because this function must grab the ring mutex (dev->struct_mutex),
88 * it can no longer run at soft irq time. We'll fix this when we do
89 * the DRI2 swap buffer work.
90 */
91static void i915_vblank_tasklet(struct drm_device *dev)
92{
93 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
94 unsigned long irqflags;
95 struct list_head *list, *tmp, hits, *hit;
96 int nhits, nrects, slice[2], upper[2], lower[2], i;
97 unsigned counter[2];
98 struct drm_drawable_info *drw;
99 drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
100 u32 cpp = dev_priv->cpp;
101 u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |
102 XY_SRC_COPY_BLT_WRITE_ALPHA |
103 XY_SRC_COPY_BLT_WRITE_RGB)
104 : XY_SRC_COPY_BLT_CMD;
105 u32 src_pitch = sarea_priv->pitch * cpp;
106 u32 dst_pitch = sarea_priv->pitch * cpp;
107 u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24);
108 RING_LOCALS;
109
110 mutex_lock(&dev->struct_mutex);
111
112 if (IS_I965G(dev) && sarea_priv->front_tiled) {
113 cmd |= XY_SRC_COPY_BLT_DST_TILED;
114 dst_pitch >>= 2;
115 }
116 if (IS_I965G(dev) && sarea_priv->back_tiled) {
117 cmd |= XY_SRC_COPY_BLT_SRC_TILED;
118 src_pitch >>= 2;
119 }
120
121 counter[0] = drm_vblank_count(dev, 0);
122 counter[1] = drm_vblank_count(dev, 1);
123
124 DRM_DEBUG("\n");
125
126 INIT_LIST_HEAD(&hits);
127
128 nhits = nrects = 0;
129
130 spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
131
132 /* Find buffer swaps scheduled for this vertical blank */
133 list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {
134 drm_i915_vbl_swap_t *vbl_swap =
135 list_entry(list, drm_i915_vbl_swap_t, head);
136 int pipe = vbl_swap->pipe;
137
138 if ((counter[pipe] - vbl_swap->sequence) > (1<<23))
139 continue;
140
141 list_del(list);
142 dev_priv->swaps_pending--;
143 drm_vblank_put(dev, pipe);
144
145 spin_unlock(&dev_priv->swaps_lock);
146 spin_lock(&dev->drw_lock);
147
148 drw = drm_get_drawable_info(dev, vbl_swap->drw_id);
149
150 list_for_each(hit, &hits) {
151 drm_i915_vbl_swap_t *swap_cmp =
152 list_entry(hit, drm_i915_vbl_swap_t, head);
153 struct drm_drawable_info *drw_cmp =
154 drm_get_drawable_info(dev, swap_cmp->drw_id);
155
156 /* Make sure both drawables are still
157 * around and have some rectangles before
158 * we look inside to order them for the
159 * blts below.
160 */
161 if (drw_cmp && drw_cmp->num_rects > 0 &&
162 drw && drw->num_rects > 0 &&
163 drw_cmp->rects[0].y1 > drw->rects[0].y1) {
164 list_add_tail(list, hit);
165 break;
166 }
167 }
168
169 spin_unlock(&dev->drw_lock);
170
171 /* List of hits was empty, or we reached the end of it */
172 if (hit == &hits)
173 list_add_tail(list, hits.prev);
174
175 nhits++;
176
177 spin_lock(&dev_priv->swaps_lock);
178 }
179
180 if (nhits == 0) {
181 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
182 mutex_unlock(&dev->struct_mutex);
183 return;
184 }
185
186 spin_unlock(&dev_priv->swaps_lock);
187
188 i915_kernel_lost_context(dev);
189
190 if (IS_I965G(dev)) {
191 BEGIN_LP_RING(4);
192
193 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
194 OUT_RING(0);
195 OUT_RING(((sarea_priv->width - 1) & 0xffff) | ((sarea_priv->height - 1) << 16));
196 OUT_RING(0);
197 ADVANCE_LP_RING();
198 } else {
199 BEGIN_LP_RING(6);
200
201 OUT_RING(GFX_OP_DRAWRECT_INFO);
202 OUT_RING(0);
203 OUT_RING(0);
204 OUT_RING(sarea_priv->width | sarea_priv->height << 16);
205 OUT_RING(sarea_priv->width | sarea_priv->height << 16);
206 OUT_RING(0);
207
208 ADVANCE_LP_RING();
209 }
210
211 sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
212
213 upper[0] = upper[1] = 0;
214 slice[0] = max(sarea_priv->pipeA_h / nhits, 1);
215 slice[1] = max(sarea_priv->pipeB_h / nhits, 1);
216 lower[0] = sarea_priv->pipeA_y + slice[0];
217 lower[1] = sarea_priv->pipeB_y + slice[0];
218
219 spin_lock(&dev->drw_lock);
220
221 /* Emit blits for buffer swaps, partitioning both outputs into as many
222 * slices as there are buffer swaps scheduled in order to avoid tearing
223 * (based on the assumption that a single buffer swap would always
224 * complete before scanout starts).
225 */
226 for (i = 0; i++ < nhits;
227 upper[0] = lower[0], lower[0] += slice[0],
228 upper[1] = lower[1], lower[1] += slice[1]) {
229 if (i == nhits)
230 lower[0] = lower[1] = sarea_priv->height;
231
232 list_for_each(hit, &hits) {
233 drm_i915_vbl_swap_t *swap_hit =
234 list_entry(hit, drm_i915_vbl_swap_t, head);
235 struct drm_clip_rect *rect;
236 int num_rects, pipe;
237 unsigned short top, bottom;
238
239 drw = drm_get_drawable_info(dev, swap_hit->drw_id);
240
241 /* The drawable may have been destroyed since
242 * the vblank swap was queued
243 */
244 if (!drw)
245 continue;
246
247 rect = drw->rects;
248 pipe = swap_hit->pipe;
249 top = upper[pipe];
250 bottom = lower[pipe];
251
252 for (num_rects = drw->num_rects; num_rects--; rect++) {
253 int y1 = max(rect->y1, top);
254 int y2 = min(rect->y2, bottom);
255
256 if (y1 >= y2)
257 continue;
258
259 BEGIN_LP_RING(8);
260
261 OUT_RING(cmd);
262 OUT_RING(ropcpp | dst_pitch);
263 OUT_RING((y1 << 16) | rect->x1);
264 OUT_RING((y2 << 16) | rect->x2);
265 OUT_RING(sarea_priv->front_offset);
266 OUT_RING((y1 << 16) | rect->x1);
267 OUT_RING(src_pitch);
268 OUT_RING(sarea_priv->back_offset);
269
270 ADVANCE_LP_RING();
271 }
272 }
273 }
274
275 spin_unlock_irqrestore(&dev->drw_lock, irqflags);
276 mutex_unlock(&dev->struct_mutex);
277
278 list_for_each_safe(hit, tmp, &hits) {
279 drm_i915_vbl_swap_t *swap_hit =
280 list_entry(hit, drm_i915_vbl_swap_t, head);
281
282 list_del(hit);
283
284 drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER);
285 }
286}
287
288/* Called from drm generic code, passed a 'crtc', which 83/* Called from drm generic code, passed a 'crtc', which
289 * we use as a pipe index 84 * we use as a pipe index
290 */ 85 */
@@ -322,40 +117,6 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
322 return count; 117 return count;
323} 118}
324 119
325void
326i915_vblank_work_handler(struct work_struct *work)
327{
328 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
329 vblank_work);
330 struct drm_device *dev = dev_priv->dev;
331 unsigned long irqflags;
332
333 if (dev->lock.hw_lock == NULL) {
334 i915_vblank_tasklet(dev);
335 return;
336 }
337
338 spin_lock_irqsave(&dev->tasklet_lock, irqflags);
339 dev->locked_tasklet_func = i915_vblank_tasklet;
340 spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
341
342 /* Try to get the lock now, if this fails, the lock
343 * holder will execute the tasklet during unlock
344 */
345 if (!drm_lock_take(&dev->lock, DRM_KERNEL_CONTEXT))
346 return;
347
348 dev->lock.lock_time = jiffies;
349 atomic_inc(&dev->counts[_DRM_STAT_LOCKS]);
350
351 spin_lock_irqsave(&dev->tasklet_lock, irqflags);
352 dev->locked_tasklet_func = NULL;
353 spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
354
355 i915_vblank_tasklet(dev);
356 drm_lock_free(&dev->lock, DRM_KERNEL_CONTEXT);
357}
358
359irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) 120irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
360{ 121{
361 struct drm_device *dev = (struct drm_device *) arg; 122 struct drm_device *dev = (struct drm_device *) arg;
@@ -433,9 +194,6 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
433 if (iir & I915_ASLE_INTERRUPT) 194 if (iir & I915_ASLE_INTERRUPT)
434 opregion_asle_intr(dev); 195 opregion_asle_intr(dev);
435 196
436 if (vblank && dev_priv->swaps_pending > 0)
437 schedule_work(&dev_priv->vblank_work);
438
439 return IRQ_HANDLED; 197 return IRQ_HANDLED;
440} 198}
441 199
@@ -454,12 +212,10 @@ static int i915_emit_irq(struct drm_device * dev)
454 if (dev_priv->sarea_priv) 212 if (dev_priv->sarea_priv)
455 dev_priv->sarea_priv->last_enqueue = dev_priv->counter; 213 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
456 214
457 BEGIN_LP_RING(6); 215 BEGIN_LP_RING(4);
458 OUT_RING(MI_STORE_DWORD_INDEX); 216 OUT_RING(MI_STORE_DWORD_INDEX);
459 OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); 217 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
460 OUT_RING(dev_priv->counter); 218 OUT_RING(dev_priv->counter);
461 OUT_RING(0);
462 OUT_RING(0);
463 OUT_RING(MI_USER_INTERRUPT); 219 OUT_RING(MI_USER_INTERRUPT);
464 ADVANCE_LP_RING(); 220 ADVANCE_LP_RING();
465 221
@@ -696,123 +452,21 @@ int i915_vblank_pipe_get(struct drm_device *dev, void *data,
696int i915_vblank_swap(struct drm_device *dev, void *data, 452int i915_vblank_swap(struct drm_device *dev, void *data,
697 struct drm_file *file_priv) 453 struct drm_file *file_priv)
698{ 454{
699 drm_i915_private_t *dev_priv = dev->dev_private; 455 /* The delayed swap mechanism was fundamentally racy, and has been
700 drm_i915_vblank_swap_t *swap = data; 456 * removed. The model was that the client requested a delayed flip/swap
701 drm_i915_vbl_swap_t *vbl_swap, *vbl_old; 457 * from the kernel, then waited for vblank before continuing to perform
702 unsigned int pipe, seqtype, curseq; 458 * rendering. The problem was that the kernel might wake the client
703 unsigned long irqflags; 459 * up before it dispatched the vblank swap (since the lock has to be
704 struct list_head *list; 460 * held while touching the ringbuffer), in which case the client would
705 int ret; 461 * clear and start the next frame before the swap occurred, and
706 462 * flicker would occur in addition to likely missing the vblank.
707 if (!dev_priv || !dev_priv->sarea_priv) { 463 *
708 DRM_ERROR("%s called with no initialization\n", __func__); 464 * In the absence of this ioctl, userland falls back to a correct path
709 return -EINVAL; 465 * of waiting for a vblank, then dispatching the swap on its own.
710 } 466 * Context switching to userland and back is plenty fast enough for
711 467 * meeting the requirements of vblank swapping.
712 if (dev_priv->sarea_priv->rotation) {
713 DRM_DEBUG("Rotation not supported\n");
714 return -EINVAL;
715 }
716
717 if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE |
718 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)) {
719 DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype);
720 return -EINVAL;
721 }
722
723 pipe = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;
724
725 seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);
726
727 if (!(dev_priv->vblank_pipe & (1 << pipe))) {
728 DRM_ERROR("Invalid pipe %d\n", pipe);
729 return -EINVAL;
730 }
731
732 spin_lock_irqsave(&dev->drw_lock, irqflags);
733
734 if (!drm_get_drawable_info(dev, swap->drawable)) {
735 spin_unlock_irqrestore(&dev->drw_lock, irqflags);
736 DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable);
737 return -EINVAL;
738 }
739
740 spin_unlock_irqrestore(&dev->drw_lock, irqflags);
741
742 /*
743 * We take the ref here and put it when the swap actually completes
744 * in the tasklet.
745 */ 468 */
746 ret = drm_vblank_get(dev, pipe); 469 return -EINVAL;
747 if (ret)
748 return ret;
749 curseq = drm_vblank_count(dev, pipe);
750
751 if (seqtype == _DRM_VBLANK_RELATIVE)
752 swap->sequence += curseq;
753
754 if ((curseq - swap->sequence) <= (1<<23)) {
755 if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) {
756 swap->sequence = curseq + 1;
757 } else {
758 DRM_DEBUG("Missed target sequence\n");
759 drm_vblank_put(dev, pipe);
760 return -EINVAL;
761 }
762 }
763
764 vbl_swap = drm_calloc(1, sizeof(*vbl_swap), DRM_MEM_DRIVER);
765
766 if (!vbl_swap) {
767 DRM_ERROR("Failed to allocate memory to queue swap\n");
768 drm_vblank_put(dev, pipe);
769 return -ENOMEM;
770 }
771
772 vbl_swap->drw_id = swap->drawable;
773 vbl_swap->pipe = pipe;
774 vbl_swap->sequence = swap->sequence;
775
776 spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
777
778 list_for_each(list, &dev_priv->vbl_swaps.head) {
779 vbl_old = list_entry(list, drm_i915_vbl_swap_t, head);
780
781 if (vbl_old->drw_id == swap->drawable &&
782 vbl_old->pipe == pipe &&
783 vbl_old->sequence == swap->sequence) {
784 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
785 drm_vblank_put(dev, pipe);
786 drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
787 DRM_DEBUG("Already scheduled\n");
788 return 0;
789 }
790 }
791
792 if (dev_priv->swaps_pending >= 10) {
793 DRM_DEBUG("Too many swaps queued\n");
794 DRM_DEBUG(" pipe 0: %d pipe 1: %d\n",
795 drm_vblank_count(dev, 0),
796 drm_vblank_count(dev, 1));
797
798 list_for_each(list, &dev_priv->vbl_swaps.head) {
799 vbl_old = list_entry(list, drm_i915_vbl_swap_t, head);
800 DRM_DEBUG("\tdrw %x pipe %d seq %x\n",
801 vbl_old->drw_id, vbl_old->pipe,
802 vbl_old->sequence);
803 }
804 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
805 drm_vblank_put(dev, pipe);
806 drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
807 return -EBUSY;
808 }
809
810 list_add_tail(&vbl_swap->head, &dev_priv->vbl_swaps.head);
811 dev_priv->swaps_pending++;
812
813 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
814
815 return 0;
816} 470}
817 471
818/* drm_dma.h hooks 472/* drm_dma.h hooks
@@ -831,11 +485,6 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
831 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 485 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
832 int ret, num_pipes = 2; 486 int ret, num_pipes = 2;
833 487
834 spin_lock_init(&dev_priv->swaps_lock);
835 INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
836 INIT_WORK(&dev_priv->vblank_work, i915_vblank_work_handler);
837 dev_priv->swaps_pending = 0;
838
839 /* Set initial unmasked IRQs to just the selected vblank pipes. */ 488 /* Set initial unmasked IRQs to just the selected vblank pipes. */
840 dev_priv->irq_mask_reg = ~0; 489 dev_priv->irq_mask_reg = ~0;
841 490
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5c2d9f206d05..0e476eba36e6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -527,6 +527,9 @@
527#define C0DRB3 0x10206 527#define C0DRB3 0x10206
528#define C1DRB3 0x10606 528#define C1DRB3 0x10606
529 529
530/** GM965 GM45 render standby register */
531#define MCHBAR_RENDER_STANDBY 0x111B8
532
530/* 533/*
531 * Overlay regs 534 * Overlay regs
532 */ 535 */
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 603fe742ccd4..5ddc6e595c0c 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -240,6 +240,10 @@ int i915_save_state(struct drm_device *dev)
240 240
241 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); 241 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
242 242
243 /* Render Standby */
244 if (IS_I965G(dev) && IS_MOBILE(dev))
245 dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
246
243 /* Display arbitration control */ 247 /* Display arbitration control */
244 dev_priv->saveDSPARB = I915_READ(DSPARB); 248 dev_priv->saveDSPARB = I915_READ(DSPARB);
245 249
@@ -365,6 +369,11 @@ int i915_restore_state(struct drm_device *dev)
365 369
366 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); 370 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
367 371
372 /* Render Standby */
373 if (IS_I965G(dev) && IS_MOBILE(dev))
374 I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);
375
376 /* Display arbitration */
368 I915_WRITE(DSPARB, dev_priv->saveDSPARB); 377 I915_WRITE(DSPARB, dev_priv->saveDSPARB);
369 378
370 /* Pipe & plane A info */ 379 /* Pipe & plane A info */
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index 59a2132a8f57..abdc1ae38467 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -653,15 +653,16 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
653 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); 653 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
654 654
655 /* Turn on bus mastering */ 655 /* Turn on bus mastering */
656 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || 656 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
657 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
658 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { 657 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
659 /* rs400, rs690/rs740 */ 658 /* rs600/rs690/rs740 */
660 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS400_BUS_MASTER_DIS; 659 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
661 RADEON_WRITE(RADEON_BUS_CNTL, tmp); 660 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
662 } else if (!(((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || 661 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
663 ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R423))) { 662 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
664 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */ 663 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
664 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
665 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
665 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 666 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
666 RADEON_WRITE(RADEON_BUS_CNTL, tmp); 667 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
667 } /* PCIE cards appears to not need this */ 668 } /* PCIE cards appears to not need this */
@@ -1750,6 +1751,12 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1750 else 1751 else
1751 dev_priv->flags |= RADEON_IS_PCI; 1752 dev_priv->flags |= RADEON_IS_PCI;
1752 1753
1754 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1755 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1756 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
1757 if (ret != 0)
1758 return ret;
1759
1753 DRM_DEBUG("%s card detected\n", 1760 DRM_DEBUG("%s card detected\n",
1754 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); 1761 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1755 return ret; 1762 return ret;
@@ -1766,12 +1773,6 @@ int radeon_driver_firstopen(struct drm_device *dev)
1766 1773
1767 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; 1774 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1768 1775
1769 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1770 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1771 _DRM_READ_ONLY, &dev_priv->mmio);
1772 if (ret != 0)
1773 return ret;
1774
1775 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0); 1776 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1776 ret = drm_addmap(dev, dev_priv->fb_aper_offset, 1777 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1777 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER, 1778 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
@@ -1787,6 +1788,9 @@ int radeon_driver_unload(struct drm_device *dev)
1787 drm_radeon_private_t *dev_priv = dev->dev_private; 1788 drm_radeon_private_t *dev_priv = dev->dev_private;
1788 1789
1789 DRM_DEBUG("\n"); 1790 DRM_DEBUG("\n");
1791
1792 drm_rmmap(dev, dev_priv->mmio);
1793
1790 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); 1794 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1791 1795
1792 dev->dev_private = NULL; 1796 dev->dev_private = NULL;
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 4dbb813910c3..7a183789be97 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -287,7 +287,6 @@ typedef struct drm_radeon_private {
287 unsigned long gart_textures_offset; 287 unsigned long gart_textures_offset;
288 288
289 drm_local_map_t *sarea; 289 drm_local_map_t *sarea;
290 drm_local_map_t *mmio;
291 drm_local_map_t *cp_ring; 290 drm_local_map_t *cp_ring;
292 drm_local_map_t *ring_rptr; 291 drm_local_map_t *ring_rptr;
293 drm_local_map_t *gart_textures; 292 drm_local_map_t *gart_textures;
@@ -318,6 +317,7 @@ typedef struct drm_radeon_private {
318 317
319 int num_gb_pipes; 318 int num_gb_pipes;
320 int track_flush; 319 int track_flush;
320 drm_local_map_t *mmio;
321} drm_radeon_private_t; 321} drm_radeon_private_t;
322 322
323typedef struct drm_radeon_buf_priv { 323typedef struct drm_radeon_buf_priv {
@@ -447,12 +447,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
447 * handling, not bus mastering itself. 447 * handling, not bus mastering itself.
448 */ 448 */
449#define RADEON_BUS_CNTL 0x0030 449#define RADEON_BUS_CNTL 0x0030
450/* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */ 450/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
451# define RADEON_BUS_MASTER_DIS (1 << 6) 451# define RADEON_BUS_MASTER_DIS (1 << 6)
452/* rs400, rs690/rs740 */ 452/* rs600/rs690/rs740 */
453# define RS400_BUS_MASTER_DIS (1 << 14) 453# define RS600_BUS_MASTER_DIS (1 << 14)
454# define RS400_MSI_REARM (1 << 20) 454# define RS600_MSI_REARM (1 << 20)
455/* see RS480_MSI_REARM in AIC_CNTL for rs480 */ 455/* see RS400_MSI_REARM in AIC_CNTL for rs480 */
456 456
457#define RADEON_BUS_CNTL1 0x0034 457#define RADEON_BUS_CNTL1 0x0034
458# define RADEON_PMI_BM_DIS (1 << 2) 458# define RADEON_PMI_BM_DIS (1 << 2)
@@ -937,7 +937,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
937 937
938#define RADEON_AIC_CNTL 0x01d0 938#define RADEON_AIC_CNTL 0x01d0
939# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 939# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
940# define RS480_MSI_REARM (1 << 3) 940# define RS400_MSI_REARM (1 << 3)
941#define RADEON_AIC_STAT 0x01d4 941#define RADEON_AIC_STAT 0x01d4
942#define RADEON_AIC_PT_BASE 0x01d8 942#define RADEON_AIC_PT_BASE 0x01d8
943#define RADEON_AIC_LO_ADDR 0x01dc 943#define RADEON_AIC_LO_ADDR 0x01dc