diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2011-07-08 07:22:38 -0400 |
---|---|---|
committer | Keith Packard <keithp@keithp.com> | 2011-07-08 13:23:06 -0400 |
commit | f19a079a800dfd365fa8ed422acf29ca7a036ea3 (patch) | |
tree | 90c8e7ffe4d8dcbd34887f8bcb352479f1936440 /drivers/gpu | |
parent | 973d04f990ac241881c4793cdfbe367b3caf3dba (diff) |
drm/i915: Remove vestigial pitch from post-gen2 FBC control routines
The cfb_pitch was only used for 8xx_enable_fbc(), every later routine
was just overwriting the value with itself thanks to a copy'n'paste
error.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ab78dfd4dfb6..5c359e59d325 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -1482,8 +1482,7 @@ static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |||
1482 | 1482 | ||
1483 | dpfc_ctl = I915_READ(DPFC_CONTROL); | 1483 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
1484 | if (dpfc_ctl & DPFC_CTL_EN) { | 1484 | if (dpfc_ctl & DPFC_CTL_EN) { |
1485 | if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 && | 1485 | if (dev_priv->cfb_fence == obj->fence_reg && |
1486 | dev_priv->cfb_fence == obj->fence_reg && | ||
1487 | dev_priv->cfb_plane == intel_crtc->plane && | 1486 | dev_priv->cfb_plane == intel_crtc->plane && |
1488 | dev_priv->cfb_y == crtc->y) | 1487 | dev_priv->cfb_y == crtc->y) |
1489 | return; | 1488 | return; |
@@ -1492,7 +1491,6 @@ static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |||
1492 | intel_wait_for_vblank(dev, intel_crtc->pipe); | 1491 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
1493 | } | 1492 | } |
1494 | 1493 | ||
1495 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; | ||
1496 | dev_priv->cfb_fence = obj->fence_reg; | 1494 | dev_priv->cfb_fence = obj->fence_reg; |
1497 | dev_priv->cfb_plane = intel_crtc->plane; | 1495 | dev_priv->cfb_plane = intel_crtc->plane; |
1498 | dev_priv->cfb_y = crtc->y; | 1496 | dev_priv->cfb_y = crtc->y; |
@@ -1572,8 +1570,7 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |||
1572 | 1570 | ||
1573 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | 1571 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
1574 | if (dpfc_ctl & DPFC_CTL_EN) { | 1572 | if (dpfc_ctl & DPFC_CTL_EN) { |
1575 | if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 && | 1573 | if (dev_priv->cfb_fence == obj->fence_reg && |
1576 | dev_priv->cfb_fence == obj->fence_reg && | ||
1577 | dev_priv->cfb_plane == intel_crtc->plane && | 1574 | dev_priv->cfb_plane == intel_crtc->plane && |
1578 | dev_priv->cfb_offset == obj->gtt_offset && | 1575 | dev_priv->cfb_offset == obj->gtt_offset && |
1579 | dev_priv->cfb_y == crtc->y) | 1576 | dev_priv->cfb_y == crtc->y) |
@@ -1583,7 +1580,6 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |||
1583 | intel_wait_for_vblank(dev, intel_crtc->pipe); | 1580 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
1584 | } | 1581 | } |
1585 | 1582 | ||
1586 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; | ||
1587 | dev_priv->cfb_fence = obj->fence_reg; | 1583 | dev_priv->cfb_fence = obj->fence_reg; |
1588 | dev_priv->cfb_plane = intel_crtc->plane; | 1584 | dev_priv->cfb_plane = intel_crtc->plane; |
1589 | dev_priv->cfb_offset = obj->gtt_offset; | 1585 | dev_priv->cfb_offset = obj->gtt_offset; |