diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2011-01-24 23:24:59 -0500 |
---|---|---|
committer | Dave Airlie <airlied@gmail.com> | 2011-01-26 22:53:30 -0500 |
commit | d75ee3be44380040b9d2c7925298dc52e049768d (patch) | |
tree | b7677fdbe19922c8e226dcb1419f9d94d17c51a2 /drivers/gpu | |
parent | 9453d621186426500aa50049dfa0a8b15c86201d (diff) |
drm/radeon/kms: clean up some magic numbers
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@gmail.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/radeon/r100.c | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r300.c | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r420.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r520.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_reg.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/rs400.c | 15 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/rv515.c | 10 |
7 files changed, 29 insertions, 21 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 5968dde243e9..5f15820efe12 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c | |||
@@ -1031,8 +1031,8 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) | |||
1031 | WREG32(RADEON_CP_CSQ_MODE, | 1031 | WREG32(RADEON_CP_CSQ_MODE, |
1032 | REG_SET(RADEON_INDIRECT2_START, indirect2_start) | | 1032 | REG_SET(RADEON_INDIRECT2_START, indirect2_start) | |
1033 | REG_SET(RADEON_INDIRECT1_START, indirect1_start)); | 1033 | REG_SET(RADEON_INDIRECT1_START, indirect1_start)); |
1034 | WREG32(0x718, 0); | 1034 | WREG32(RADEON_CP_RB_WPTR_DELAY, 0); |
1035 | WREG32(0x744, 0x00004D4D); | 1035 | WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); |
1036 | WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); | 1036 | WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); |
1037 | radeon_ring_start(rdev); | 1037 | radeon_ring_start(rdev); |
1038 | r = radeon_ring_test(rdev); | 1038 | r = radeon_ring_test(rdev); |
@@ -2347,10 +2347,10 @@ void r100_vga_set_state(struct radeon_device *rdev, bool state) | |||
2347 | 2347 | ||
2348 | temp = RREG32(RADEON_CONFIG_CNTL); | 2348 | temp = RREG32(RADEON_CONFIG_CNTL); |
2349 | if (state == false) { | 2349 | if (state == false) { |
2350 | temp &= ~(1<<8); | 2350 | temp &= ~RADEON_CFG_VGA_RAM_EN; |
2351 | temp |= (1<<9); | 2351 | temp |= RADEON_CFG_VGA_IO_DIS; |
2352 | } else { | 2352 | } else { |
2353 | temp &= ~(1<<9); | 2353 | temp &= ~RADEON_CFG_VGA_IO_DIS; |
2354 | } | 2354 | } |
2355 | WREG32(RADEON_CONFIG_CNTL, temp); | 2355 | WREG32(RADEON_CONFIG_CNTL, temp); |
2356 | } | 2356 | } |
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index cf862ca580bf..55fe5ba7def3 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c | |||
@@ -69,6 +69,9 @@ void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) | |||
69 | mb(); | 69 | mb(); |
70 | } | 70 | } |
71 | 71 | ||
72 | #define R300_PTE_WRITEABLE (1 << 2) | ||
73 | #define R300_PTE_READABLE (1 << 3) | ||
74 | |||
72 | int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) | 75 | int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
73 | { | 76 | { |
74 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; | 77 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
@@ -78,7 +81,7 @@ int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) | |||
78 | } | 81 | } |
79 | addr = (lower_32_bits(addr) >> 8) | | 82 | addr = (lower_32_bits(addr) >> 8) | |
80 | ((upper_32_bits(addr) & 0xff) << 24) | | 83 | ((upper_32_bits(addr) & 0xff) << 24) | |
81 | 0xc; | 84 | R300_PTE_WRITEABLE | R300_PTE_READABLE; |
82 | /* on x86 we want this to be CPU endian, on powerpc | 85 | /* on x86 we want this to be CPU endian, on powerpc |
83 | * on powerpc without HW swappers, it'll get swapped on way | 86 | * on powerpc without HW swappers, it'll get swapped on way |
84 | * into VRAM - so no need for cpu_to_le32 on VRAM tables */ | 87 | * into VRAM - so no need for cpu_to_le32 on VRAM tables */ |
@@ -135,7 +138,7 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev) | |||
135 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); | 138 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); |
136 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); | 139 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); |
137 | /* Clear error */ | 140 | /* Clear error */ |
138 | WREG32_PCIE(0x18, 0); | 141 | WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); |
139 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); | 142 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
140 | tmp |= RADEON_PCIE_TX_GART_EN; | 143 | tmp |= RADEON_PCIE_TX_GART_EN; |
141 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; | 144 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c index c387346f93a9..0b59ed7c7d2c 100644 --- a/drivers/gpu/drm/radeon/r420.c +++ b/drivers/gpu/drm/radeon/r420.c | |||
@@ -96,7 +96,7 @@ void r420_pipes_init(struct radeon_device *rdev) | |||
96 | "programming pipes. Bad things might happen.\n"); | 96 | "programming pipes. Bad things might happen.\n"); |
97 | } | 97 | } |
98 | /* get max number of pipes */ | 98 | /* get max number of pipes */ |
99 | gb_pipe_select = RREG32(0x402C); | 99 | gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); |
100 | num_pipes = ((gb_pipe_select >> 12) & 3) + 1; | 100 | num_pipes = ((gb_pipe_select >> 12) & 3) + 1; |
101 | 101 | ||
102 | /* SE chips have 1 pipe */ | 102 | /* SE chips have 1 pipe */ |
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c index 3c8677f9e385..2ce80d976568 100644 --- a/drivers/gpu/drm/radeon/r520.c +++ b/drivers/gpu/drm/radeon/r520.c | |||
@@ -79,8 +79,8 @@ static void r520_gpu_init(struct radeon_device *rdev) | |||
79 | WREG32(0x4128, 0xFF); | 79 | WREG32(0x4128, 0xFF); |
80 | } | 80 | } |
81 | r420_pipes_init(rdev); | 81 | r420_pipes_init(rdev); |
82 | gb_pipe_select = RREG32(0x402C); | 82 | gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); |
83 | tmp = RREG32(0x170C); | 83 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
84 | pipe_select_current = (tmp >> 2) & 3; | 84 | pipe_select_current = (tmp >> 2) & 3; |
85 | tmp = (1 << pipe_select_current) | | 85 | tmp = (1 << pipe_select_current) | |
86 | (((gb_pipe_select >> 8) & 0xF) << 4); | 86 | (((gb_pipe_select >> 8) & 0xF) << 4); |
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h index 3cd4dace57c7..ec93a75369e6 100644 --- a/drivers/gpu/drm/radeon/radeon_reg.h +++ b/drivers/gpu/drm/radeon/radeon_reg.h | |||
@@ -375,6 +375,8 @@ | |||
375 | #define RADEON_CONFIG_APER_SIZE 0x0108 | 375 | #define RADEON_CONFIG_APER_SIZE 0x0108 |
376 | #define RADEON_CONFIG_BONDS 0x00e8 | 376 | #define RADEON_CONFIG_BONDS 0x00e8 |
377 | #define RADEON_CONFIG_CNTL 0x00e0 | 377 | #define RADEON_CONFIG_CNTL 0x00e0 |
378 | # define RADEON_CFG_VGA_RAM_EN (1 << 8) | ||
379 | # define RADEON_CFG_VGA_IO_DIS (1 << 9) | ||
378 | # define RADEON_CFG_ATI_REV_A11 (0 << 16) | 380 | # define RADEON_CFG_ATI_REV_A11 (0 << 16) |
379 | # define RADEON_CFG_ATI_REV_A12 (1 << 16) | 381 | # define RADEON_CFG_ATI_REV_A12 (1 << 16) |
380 | # define RADEON_CFG_ATI_REV_A13 (2 << 16) | 382 | # define RADEON_CFG_ATI_REV_A13 (2 << 16) |
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c index 5512e4e5e636..c76283d9eb3d 100644 --- a/drivers/gpu/drm/radeon/rs400.c +++ b/drivers/gpu/drm/radeon/rs400.c | |||
@@ -203,6 +203,9 @@ void rs400_gart_fini(struct radeon_device *rdev) | |||
203 | radeon_gart_table_ram_free(rdev); | 203 | radeon_gart_table_ram_free(rdev); |
204 | } | 204 | } |
205 | 205 | ||
206 | #define RS400_PTE_WRITEABLE (1 << 2) | ||
207 | #define RS400_PTE_READABLE (1 << 3) | ||
208 | |||
206 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) | 209 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
207 | { | 210 | { |
208 | uint32_t entry; | 211 | uint32_t entry; |
@@ -213,7 +216,7 @@ int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) | |||
213 | 216 | ||
214 | entry = (lower_32_bits(addr) & PAGE_MASK) | | 217 | entry = (lower_32_bits(addr) & PAGE_MASK) | |
215 | ((upper_32_bits(addr) & 0xff) << 4) | | 218 | ((upper_32_bits(addr) & 0xff) << 4) | |
216 | 0xc; | 219 | RS400_PTE_WRITEABLE | RS400_PTE_READABLE; |
217 | entry = cpu_to_le32(entry); | 220 | entry = cpu_to_le32(entry); |
218 | rdev->gart.table.ram.ptr[i] = entry; | 221 | rdev->gart.table.ram.ptr[i] = entry; |
219 | return 0; | 222 | return 0; |
@@ -226,8 +229,8 @@ int rs400_mc_wait_for_idle(struct radeon_device *rdev) | |||
226 | 229 | ||
227 | for (i = 0; i < rdev->usec_timeout; i++) { | 230 | for (i = 0; i < rdev->usec_timeout; i++) { |
228 | /* read MC_STATUS */ | 231 | /* read MC_STATUS */ |
229 | tmp = RREG32(0x0150); | 232 | tmp = RREG32(RADEON_MC_STATUS); |
230 | if (tmp & (1 << 2)) { | 233 | if (tmp & RADEON_MC_IDLE) { |
231 | return 0; | 234 | return 0; |
232 | } | 235 | } |
233 | DRM_UDELAY(1); | 236 | DRM_UDELAY(1); |
@@ -241,7 +244,7 @@ void rs400_gpu_init(struct radeon_device *rdev) | |||
241 | r420_pipes_init(rdev); | 244 | r420_pipes_init(rdev); |
242 | if (rs400_mc_wait_for_idle(rdev)) { | 245 | if (rs400_mc_wait_for_idle(rdev)) { |
243 | printk(KERN_WARNING "rs400: Failed to wait MC idle while " | 246 | printk(KERN_WARNING "rs400: Failed to wait MC idle while " |
244 | "programming pipes. Bad things might happen. %08x\n", RREG32(0x150)); | 247 | "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS)); |
245 | } | 248 | } |
246 | } | 249 | } |
247 | 250 | ||
@@ -300,9 +303,9 @@ static int rs400_debugfs_gart_info(struct seq_file *m, void *data) | |||
300 | seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); | 303 | seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); |
301 | tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); | 304 | tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); |
302 | seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); | 305 | seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); |
303 | tmp = RREG32_MC(0x100); | 306 | tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION); |
304 | seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); | 307 | seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); |
305 | tmp = RREG32(0x134); | 308 | tmp = RREG32(RS690_HDP_FB_LOCATION); |
306 | seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); | 309 | seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); |
307 | } else { | 310 | } else { |
308 | tmp = RREG32(RADEON_AGP_BASE); | 311 | tmp = RREG32(RADEON_AGP_BASE); |
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c index 5d569f41f4ae..64b57af93714 100644 --- a/drivers/gpu/drm/radeon/rv515.c +++ b/drivers/gpu/drm/radeon/rv515.c | |||
@@ -69,13 +69,13 @@ void rv515_ring_start(struct radeon_device *rdev) | |||
69 | ISYNC_CPSCRATCH_IDLEGUI); | 69 | ISYNC_CPSCRATCH_IDLEGUI); |
70 | radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); | 70 | radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); |
71 | radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); | 71 | radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); |
72 | radeon_ring_write(rdev, PACKET0(0x170C, 0)); | 72 | radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0)); |
73 | radeon_ring_write(rdev, 1 << 31); | 73 | radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG); |
74 | radeon_ring_write(rdev, PACKET0(GB_SELECT, 0)); | 74 | radeon_ring_write(rdev, PACKET0(GB_SELECT, 0)); |
75 | radeon_ring_write(rdev, 0); | 75 | radeon_ring_write(rdev, 0); |
76 | radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0)); | 76 | radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0)); |
77 | radeon_ring_write(rdev, 0); | 77 | radeon_ring_write(rdev, 0); |
78 | radeon_ring_write(rdev, PACKET0(0x42C8, 0)); | 78 | radeon_ring_write(rdev, PACKET0(R500_SU_REG_DEST, 0)); |
79 | radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1); | 79 | radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1); |
80 | radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0)); | 80 | radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0)); |
81 | radeon_ring_write(rdev, 0); | 81 | radeon_ring_write(rdev, 0); |
@@ -153,8 +153,8 @@ void rv515_gpu_init(struct radeon_device *rdev) | |||
153 | } | 153 | } |
154 | rv515_vga_render_disable(rdev); | 154 | rv515_vga_render_disable(rdev); |
155 | r420_pipes_init(rdev); | 155 | r420_pipes_init(rdev); |
156 | gb_pipe_select = RREG32(0x402C); | 156 | gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); |
157 | tmp = RREG32(0x170C); | 157 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
158 | pipe_select_current = (tmp >> 2) & 3; | 158 | pipe_select_current = (tmp >> 2) & 3; |
159 | tmp = (1 << pipe_select_current) | | 159 | tmp = (1 << pipe_select_current) | |
160 | (((gb_pipe_select >> 8) & 0xF) << 4); | 160 | (((gb_pipe_select >> 8) & 0xF) << 4); |