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authorMartin Peres <martin.peres@ensi-bourges.fr>2011-10-06 17:47:58 -0400
committerBen Skeggs <bskeggs@redhat.com>2011-12-21 04:01:24 -0500
commitd4cca9e1fccb9f7804ddfbbc2aebff7be23faa1e (patch)
tree4be314c14630a6a381160fa7f4e2133afe6f6089 /drivers/gpu
parentdd1da8de172057b36860f427777ecfa293bb8f6c (diff)
drm/nv50/pm: s/PLL_UNK05/PLL_VDEC/
Following to "drm/nv50/pm: s/unk05/vdec/", let's rename the PLL to PLL_VDEC PLL names are purely indicative and are based on the most important engine it clocks. Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.h2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_pm.c4
3 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 41899eccf570..89747bebbfc7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -4719,7 +4719,7 @@ static struct pll_mapping nv84_pll_mapping[] = {
4719 { PLL_CORE , 0x004028 }, 4719 { PLL_CORE , 0x004028 },
4720 { PLL_SHADER, 0x004020 }, 4720 { PLL_SHADER, 0x004020 },
4721 { PLL_MEMORY, 0x004008 }, 4721 { PLL_MEMORY, 0x004008 },
4722 { PLL_UNK05 , 0x004030 }, 4722 { PLL_VDEC , 0x004030 },
4723 { PLL_UNK41 , 0x00e818 }, 4723 { PLL_UNK41 , 0x00e818 },
4724 { PLL_VPLL0 , 0x614100 }, 4724 { PLL_VPLL0 , 0x614100 },
4725 { PLL_VPLL1 , 0x614900 }, 4725 { PLL_VPLL1 , 0x614900 },
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h
index a1e31ea2ecbf..dff121d8896f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.h
@@ -196,7 +196,7 @@ enum pll_types {
196 PLL_SHADER = 0x02, 196 PLL_SHADER = 0x02,
197 PLL_UNK03 = 0x03, 197 PLL_UNK03 = 0x03,
198 PLL_MEMORY = 0x04, 198 PLL_MEMORY = 0x04,
199 PLL_UNK05 = 0x05, 199 PLL_VDEC = 0x05,
200 PLL_UNK40 = 0x40, 200 PLL_UNK40 = 0x40,
201 PLL_UNK41 = 0x41, 201 PLL_UNK41 = 0x41,
202 PLL_UNK42 = 0x42, 202 PLL_UNK42 = 0x42,
diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.c b/drivers/gpu/drm/nouveau/nouveau_pm.c
index ea620d8de007..9177358616b0 100644
--- a/drivers/gpu/drm/nouveau/nouveau_pm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_pm.c
@@ -154,7 +154,7 @@ nouveau_pm_perflvl_set(struct drm_device *dev, struct nouveau_pm_level *perflvl)
154 nouveau_pm_clock_set(dev, perflvl, PLL_CORE, perflvl->core); 154 nouveau_pm_clock_set(dev, perflvl, PLL_CORE, perflvl->core);
155 nouveau_pm_clock_set(dev, perflvl, PLL_SHADER, perflvl->shader); 155 nouveau_pm_clock_set(dev, perflvl, PLL_SHADER, perflvl->shader);
156 nouveau_pm_clock_set(dev, perflvl, PLL_MEMORY, perflvl->memory); 156 nouveau_pm_clock_set(dev, perflvl, PLL_MEMORY, perflvl->memory);
157 nouveau_pm_clock_set(dev, perflvl, PLL_UNK05, perflvl->vdec); 157 nouveau_pm_clock_set(dev, perflvl, PLL_VDEC, perflvl->vdec);
158 } 158 }
159 159
160 pm->cur = perflvl; 160 pm->cur = perflvl;
@@ -220,7 +220,7 @@ nouveau_pm_perflvl_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
220 if (ret > 0) 220 if (ret > 0)
221 perflvl->shader = ret; 221 perflvl->shader = ret;
222 222
223 ret = pm->clock_get(dev, PLL_UNK05); 223 ret = pm->clock_get(dev, PLL_VDEC);
224 if (ret > 0) 224 if (ret > 0)
225 perflvl->vdec = ret; 225 perflvl->vdec = ret;
226 } 226 }