aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu
diff options
context:
space:
mode:
authorJerome Glisse <jglisse@redhat.com>2009-09-28 12:34:43 -0400
committerDave Airlie <airlied@linux.ie>2009-09-28 21:15:54 -0400
commitd39c3b895876427c5083a936e00f3f5b7f0fc1b3 (patch)
tree1f57be660f35c99ef6d182d2bf8397a818c8f8d0 /drivers/gpu
parentf4e45d02e4135043fe98bc21be38527c516ad990 (diff)
drm/radeon/kms: Convert RV515 to new init path and associated cleanup
Convert the rv515 asic support to new init path also add an explanation in radeon.h about the new init path. There is also few cleanups associated with this change (others asic calling rv515 helper functions). Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/avivod.h9
-rw-r--r--drivers/gpu/drm/radeon/r520.c9
-rw-r--r--drivers/gpu/drm/radeon/r600.c4
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon.h34
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h37
-rw-r--r--drivers/gpu/drm/radeon/rs600.c20
-rw-r--r--drivers/gpu/drm/radeon/rs690.c3
-rw-r--r--drivers/gpu/drm/radeon/rv515.c364
-rw-r--r--drivers/gpu/drm/radeon/rv515d.h385
-rw-r--r--drivers/gpu/drm/radeon/rv770.c4
11 files changed, 712 insertions, 158 deletions
diff --git a/drivers/gpu/drm/radeon/avivod.h b/drivers/gpu/drm/radeon/avivod.h
index e2b92c445bab..d4e6e6e4a938 100644
--- a/drivers/gpu/drm/radeon/avivod.h
+++ b/drivers/gpu/drm/radeon/avivod.h
@@ -57,13 +57,4 @@
57#define VGA_RENDER_CONTROL 0x0300 57#define VGA_RENDER_CONTROL 0x0300
58#define VGA_VSTATUS_CNTL_MASK 0x00030000 58#define VGA_VSTATUS_CNTL_MASK 0x00030000
59 59
60/* AVIVO disable VGA rendering */
61static inline void radeon_avivo_vga_render_disable(struct radeon_device *rdev)
62{
63 u32 vga_render;
64 vga_render = RREG32(VGA_RENDER_CONTROL);
65 vga_render &= ~VGA_VSTATUS_CNTL_MASK;
66 WREG32(VGA_RENDER_CONTROL, vga_render);
67}
68
69#endif 60#endif
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index d4b0b9d2e39b..2723486ad380 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -33,7 +33,6 @@
33void r100_hdp_reset(struct radeon_device *rdev); 33void r100_hdp_reset(struct radeon_device *rdev);
34void r420_pipes_init(struct radeon_device *rdev); 34void r420_pipes_init(struct radeon_device *rdev);
35void rs600_mc_disable_clients(struct radeon_device *rdev); 35void rs600_mc_disable_clients(struct radeon_device *rdev);
36void rs600_disable_vga(struct radeon_device *rdev);
37int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); 36int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
38int rv515_debugfs_ga_info_init(struct radeon_device *rdev); 37int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
39 38
@@ -148,7 +147,7 @@ void r520_gpu_init(struct radeon_device *rdev)
148 unsigned pipe_select_current, gb_pipe_select, tmp; 147 unsigned pipe_select_current, gb_pipe_select, tmp;
149 148
150 r100_hdp_reset(rdev); 149 r100_hdp_reset(rdev);
151 rs600_disable_vga(rdev); 150 rv515_vga_render_disable(rdev);
152 /* 151 /*
153 * DST_PIPE_CONFIG 0x170C 152 * DST_PIPE_CONFIG 0x170C
154 * GB_TILE_CONFIG 0x4018 153 * GB_TILE_CONFIG 0x4018
@@ -237,3 +236,9 @@ void r520_bandwidth_update(struct radeon_device *rdev)
237{ 236{
238 rv515_bandwidth_avivo_update(rdev); 237 rv515_bandwidth_avivo_update(rdev);
239} 238}
239
240int r520_init(struct radeon_device *rdev)
241{
242 rv515_set_safe_registers(rdev);
243 return 0;
244}
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index c7233ad5dd94..6b7a40b501c0 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -33,8 +33,8 @@
33#include "radeon.h" 33#include "radeon.h"
34#include "radeon_mode.h" 34#include "radeon_mode.h"
35#include "r600d.h" 35#include "r600d.h"
36#include "avivod.h"
37#include "atom.h" 36#include "atom.h"
37#include "avivod.h"
38 38
39#define PFP_UCODE_SIZE 576 39#define PFP_UCODE_SIZE 576
40#define PM4_UCODE_SIZE 1792 40#define PM4_UCODE_SIZE 1792
@@ -342,7 +342,7 @@ static void r600_mc_resume(struct radeon_device *rdev)
342 342
343 /* we need to own VRAM, so turn off the VGA renderer here 343 /* we need to own VRAM, so turn off the VGA renderer here
344 * to stop it overwriting our objects */ 344 * to stop it overwriting our objects */
345 radeon_avivo_vga_render_disable(rdev); 345 rv515_vga_render_disable(rdev);
346} 346}
347 347
348int r600_mc_init(struct radeon_device *rdev) 348int r600_mc_init(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 06eab79c2eec..d28970db6a2d 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -28,7 +28,6 @@
28#include "drmP.h" 28#include "drmP.h"
29#include "radeon.h" 29#include "radeon.h"
30#include "r600d.h" 30#include "r600d.h"
31#include "avivod.h"
32 31
33static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, 32static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
34 struct radeon_cs_reloc **cs_reloc); 33 struct radeon_cs_reloc **cs_reloc);
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 7e34e4376f95..116bedddffe6 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -44,6 +44,24 @@
44 * - TESTING, TESTING, TESTING 44 * - TESTING, TESTING, TESTING
45 */ 45 */
46 46
47/* Initialization path:
48 * We expect that acceleration initialization might fail for various
49 * reasons even thought we work hard to make it works on most
50 * configurations. In order to still have a working userspace in such
51 * situation the init path must succeed up to the memory controller
52 * initialization point. Failure before this point are considered as
53 * fatal error. Here is the init callchain :
54 * radeon_device_init perform common structure, mutex initialization
55 * asic_init setup the GPU memory layout and perform all
56 * one time initialization (failure in this
57 * function are considered fatal)
58 * asic_startup setup the GPU acceleration, in order to
59 * follow guideline the first thing this
60 * function should do is setting the GPU
61 * memory controller (only MC setup failure
62 * are considered as fatal)
63 */
64
47#include <asm/atomic.h> 65#include <asm/atomic.h>
48#include <linux/wait.h> 66#include <linux/wait.h>
49#include <linux/list.h> 67#include <linux/list.h>
@@ -976,6 +994,7 @@ extern void radeon_clocks_fini(struct radeon_device *rdev);
976extern void radeon_scratch_init(struct radeon_device *rdev); 994extern void radeon_scratch_init(struct radeon_device *rdev);
977extern void radeon_surface_init(struct radeon_device *rdev); 995extern void radeon_surface_init(struct radeon_device *rdev);
978extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 996extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
997extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
979 998
980/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ 999/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
981struct r100_mc_save { 1000struct r100_mc_save {
@@ -1007,6 +1026,9 @@ extern void r100_vram_init_sizes(struct radeon_device *rdev);
1007extern void r100_wb_disable(struct radeon_device *rdev); 1026extern void r100_wb_disable(struct radeon_device *rdev);
1008extern void r100_wb_fini(struct radeon_device *rdev); 1027extern void r100_wb_fini(struct radeon_device *rdev);
1009extern int r100_wb_init(struct radeon_device *rdev); 1028extern int r100_wb_init(struct radeon_device *rdev);
1029extern void r100_hdp_reset(struct radeon_device *rdev);
1030extern int r100_rb2d_reset(struct radeon_device *rdev);
1031extern int r100_cp_reset(struct radeon_device *rdev);
1010 1032
1011/* r300,r350,rv350,rv370,rv380 */ 1033/* r300,r350,rv350,rv370,rv380 */
1012extern void r300_set_reg_safe(struct radeon_device *rdev); 1034extern void r300_set_reg_safe(struct radeon_device *rdev);
@@ -1018,12 +1040,24 @@ extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1018extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 1040extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1019 1041
1020/* r420,r423,rv410 */ 1042/* r420,r423,rv410 */
1043extern int r420_mc_init(struct radeon_device *rdev);
1021extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 1044extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1022extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 1045extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1023extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 1046extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1047extern void r420_pipes_init(struct radeon_device *rdev);
1024 1048
1025/* rv515 */ 1049/* rv515 */
1050struct rv515_mc_save {
1051 u32 d1vga_control;
1052 u32 d2vga_control;
1053 u32 vga_render_control;
1054 u32 vga_hdp_control;
1055 u32 d1crtc_control;
1056 u32 d2crtc_control;
1057};
1026extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 1058extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1059extern void rv515_vga_render_disable(struct radeon_device *rdev);
1060extern void rv515_set_safe_registers(struct radeon_device *rdev);
1027 1061
1028/* rs690, rs740 */ 1062/* rs690, rs740 */
1029extern void rs690_line_buffer_adjust(struct radeon_device *rdev, 1063extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 5f2a9e6f12c5..ccbf5253914d 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -413,40 +413,42 @@ static struct radeon_asic rs690_asic = {
413 * rv515 413 * rv515
414 */ 414 */
415int rv515_init(struct radeon_device *rdev); 415int rv515_init(struct radeon_device *rdev);
416void rv515_errata(struct radeon_device *rdev); 416void rv515_fini(struct radeon_device *rdev);
417void rv515_vram_info(struct radeon_device *rdev);
418int rv515_gpu_reset(struct radeon_device *rdev); 417int rv515_gpu_reset(struct radeon_device *rdev);
419int rv515_mc_init(struct radeon_device *rdev);
420void rv515_mc_fini(struct radeon_device *rdev);
421uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); 418uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
422void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 419void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
423void rv515_ring_start(struct radeon_device *rdev); 420void rv515_ring_start(struct radeon_device *rdev);
424uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 421uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
425void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 422void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
426void rv515_bandwidth_update(struct radeon_device *rdev); 423void rv515_bandwidth_update(struct radeon_device *rdev);
424int rv515_resume(struct radeon_device *rdev);
425int rv515_suspend(struct radeon_device *rdev);
427static struct radeon_asic rv515_asic = { 426static struct radeon_asic rv515_asic = {
428 .init = &rv515_init, 427 .init = &rv515_init,
429 .errata = &rv515_errata, 428 .fini = &rv515_fini,
430 .vram_info = &rv515_vram_info, 429 .suspend = &rv515_suspend,
430 .resume = &rv515_resume,
431 .errata = NULL,
432 .vram_info = NULL,
431 .gpu_reset = &rv515_gpu_reset, 433 .gpu_reset = &rv515_gpu_reset,
432 .mc_init = &rv515_mc_init, 434 .mc_init = NULL,
433 .mc_fini = &rv515_mc_fini, 435 .mc_fini = NULL,
434 .wb_init = &r100_wb_init, 436 .wb_init = NULL,
435 .wb_fini = &r100_wb_fini, 437 .wb_fini = NULL,
436 .gart_init = &rv370_pcie_gart_init, 438 .gart_init = &rv370_pcie_gart_init,
437 .gart_fini = &rv370_pcie_gart_fini, 439 .gart_fini = &rv370_pcie_gart_fini,
438 .gart_enable = &rv370_pcie_gart_enable, 440 .gart_enable = NULL,
439 .gart_disable = &rv370_pcie_gart_disable, 441 .gart_disable = NULL,
440 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 442 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
441 .gart_set_page = &rv370_pcie_gart_set_page, 443 .gart_set_page = &rv370_pcie_gart_set_page,
442 .cp_init = &r100_cp_init, 444 .cp_init = NULL,
443 .cp_fini = &r100_cp_fini, 445 .cp_fini = NULL,
444 .cp_disable = &r100_cp_disable, 446 .cp_disable = NULL,
445 .cp_commit = &r100_cp_commit, 447 .cp_commit = &r100_cp_commit,
446 .ring_start = &rv515_ring_start, 448 .ring_start = &rv515_ring_start,
447 .ring_test = &r100_ring_test, 449 .ring_test = &r100_ring_test,
448 .ring_ib_execute = &r100_ring_ib_execute, 450 .ring_ib_execute = &r100_ring_ib_execute,
449 .ib_test = &r100_ib_test, 451 .ib_test = NULL,
450 .irq_set = &rs600_irq_set, 452 .irq_set = &rs600_irq_set,
451 .irq_process = &rs600_irq_process, 453 .irq_process = &rs600_irq_process,
452 .get_vblank_counter = &rs600_get_vblank_counter, 454 .get_vblank_counter = &rs600_get_vblank_counter,
@@ -468,13 +470,14 @@ static struct radeon_asic rv515_asic = {
468/* 470/*
469 * r520,rv530,rv560,rv570,r580 471 * r520,rv530,rv560,rv570,r580
470 */ 472 */
473int r520_init(struct radeon_device *rdev);
471void r520_errata(struct radeon_device *rdev); 474void r520_errata(struct radeon_device *rdev);
472void r520_vram_info(struct radeon_device *rdev); 475void r520_vram_info(struct radeon_device *rdev);
473int r520_mc_init(struct radeon_device *rdev); 476int r520_mc_init(struct radeon_device *rdev);
474void r520_mc_fini(struct radeon_device *rdev); 477void r520_mc_fini(struct radeon_device *rdev);
475void r520_bandwidth_update(struct radeon_device *rdev); 478void r520_bandwidth_update(struct radeon_device *rdev);
476static struct radeon_asic r520_asic = { 479static struct radeon_asic r520_asic = {
477 .init = &rv515_init, 480 .init = &r520_init,
478 .errata = &r520_errata, 481 .errata = &r520_errata,
479 .vram_info = &r520_vram_info, 482 .vram_info = &r520_vram_info,
480 .gpu_reset = &rv515_gpu_reset, 483 .gpu_reset = &rv515_gpu_reset,
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 0e791e26def3..4a4fe1cb131c 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -28,7 +28,6 @@
28#include "drmP.h" 28#include "drmP.h"
29#include "radeon_reg.h" 29#include "radeon_reg.h"
30#include "radeon.h" 30#include "radeon.h"
31#include "avivod.h"
32 31
33#include "rs600_reg_safe.h" 32#include "rs600_reg_safe.h"
34 33
@@ -45,7 +44,6 @@ void r420_pipes_init(struct radeon_device *rdev);
45 */ 44 */
46void rs600_gpu_init(struct radeon_device *rdev); 45void rs600_gpu_init(struct radeon_device *rdev);
47int rs600_mc_wait_for_idle(struct radeon_device *rdev); 46int rs600_mc_wait_for_idle(struct radeon_device *rdev);
48void rs600_disable_vga(struct radeon_device *rdev);
49 47
50 48
51/* 49/*
@@ -198,7 +196,7 @@ void rs600_mc_disable_clients(struct radeon_device *rdev)
198 "programming pipes. Bad things might happen.\n"); 196 "programming pipes. Bad things might happen.\n");
199 } 197 }
200 198
201 radeon_avivo_vga_render_disable(rdev); 199 rv515_vga_render_disable(rdev);
202 200
203 tmp = RREG32(AVIVO_D1VGA_CONTROL); 201 tmp = RREG32(AVIVO_D1VGA_CONTROL);
204 WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 202 WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
@@ -346,20 +344,6 @@ u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
346/* 344/*
347 * Global GPU functions 345 * Global GPU functions
348 */ 346 */
349void rs600_disable_vga(struct radeon_device *rdev)
350{
351 unsigned tmp;
352
353 WREG32(0x330, 0);
354 WREG32(0x338, 0);
355 tmp = RREG32(0x300);
356 tmp &= ~(3 << 16);
357 WREG32(0x300, tmp);
358 WREG32(0x308, (1 << 8));
359 WREG32(0x310, rdev->mc.vram_location);
360 WREG32(0x594, 0);
361}
362
363int rs600_mc_wait_for_idle(struct radeon_device *rdev) 347int rs600_mc_wait_for_idle(struct radeon_device *rdev)
364{ 348{
365 unsigned i; 349 unsigned i;
@@ -385,7 +369,7 @@ void rs600_gpu_init(struct radeon_device *rdev)
385{ 369{
386 /* FIXME: HDP same place on rs600 ? */ 370 /* FIXME: HDP same place on rs600 ? */
387 r100_hdp_reset(rdev); 371 r100_hdp_reset(rdev);
388 rs600_disable_vga(rdev); 372 rv515_vga_render_disable(rdev);
389 /* FIXME: is this correct ? */ 373 /* FIXME: is this correct ? */
390 r420_pipes_init(rdev); 374 r420_pipes_init(rdev);
391 if (rs600_mc_wait_for_idle(rdev)) { 375 if (rs600_mc_wait_for_idle(rdev)) {
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 0f585ca8276d..7a0098ddf977 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -40,7 +40,6 @@ void rs400_gart_disable(struct radeon_device *rdev);
40int rs400_gart_enable(struct radeon_device *rdev); 40int rs400_gart_enable(struct radeon_device *rdev);
41void rs400_gart_adjust_size(struct radeon_device *rdev); 41void rs400_gart_adjust_size(struct radeon_device *rdev);
42void rs600_mc_disable_clients(struct radeon_device *rdev); 42void rs600_mc_disable_clients(struct radeon_device *rdev);
43void rs600_disable_vga(struct radeon_device *rdev);
44 43
45/* This files gather functions specifics to : 44/* This files gather functions specifics to :
46 * rs690,rs740 45 * rs690,rs740
@@ -125,7 +124,7 @@ void rs690_gpu_init(struct radeon_device *rdev)
125{ 124{
126 /* FIXME: HDP same place on rs690 ? */ 125 /* FIXME: HDP same place on rs690 ? */
127 r100_hdp_reset(rdev); 126 r100_hdp_reset(rdev);
128 rs600_disable_vga(rdev); 127 rv515_vga_render_disable(rdev);
129 /* FIXME: is this correct ? */ 128 /* FIXME: is this correct ? */
130 r420_pipes_init(rdev); 129 r420_pipes_init(rdev);
131 if (rs690_mc_wait_for_idle(rdev)) { 130 if (rs690_mc_wait_for_idle(rdev)) {
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index fd799748e7d8..a837ddcada1e 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -29,37 +29,17 @@
29#include "drmP.h" 29#include "drmP.h"
30#include "rv515d.h" 30#include "rv515d.h"
31#include "radeon.h" 31#include "radeon.h"
32 32#include "atom.h"
33#include "rv515_reg_safe.h" 33#include "rv515_reg_safe.h"
34/* rv515 depends on : */ 34
35void r100_hdp_reset(struct radeon_device *rdev); 35/* This files gather functions specifics to: rv515 */
36int r100_cp_reset(struct radeon_device *rdev);
37int r100_rb2d_reset(struct radeon_device *rdev);
38int r100_gui_wait_for_idle(struct radeon_device *rdev);
39int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
40void r420_pipes_init(struct radeon_device *rdev);
41void rs600_mc_disable_clients(struct radeon_device *rdev);
42void rs600_disable_vga(struct radeon_device *rdev);
43
44/* This files gather functions specifics to:
45 * rv515
46 *
47 * Some of these functions might be used by newer ASICs.
48 */
49int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); 36int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
50int rv515_debugfs_ga_info_init(struct radeon_device *rdev); 37int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
51void rv515_gpu_init(struct radeon_device *rdev); 38void rv515_gpu_init(struct radeon_device *rdev);
52int rv515_mc_wait_for_idle(struct radeon_device *rdev); 39int rv515_mc_wait_for_idle(struct radeon_device *rdev);
53 40
54 41static void rv515_debugfs(struct radeon_device *rdev)
55/*
56 * MC
57 */
58int rv515_mc_init(struct radeon_device *rdev)
59{ 42{
60 uint32_t tmp;
61 int r;
62
63 if (r100_debugfs_rbbm_init(rdev)) { 43 if (r100_debugfs_rbbm_init(rdev)) {
64 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 44 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
65 } 45 }
@@ -69,67 +49,8 @@ int rv515_mc_init(struct radeon_device *rdev)
69 if (rv515_debugfs_ga_info_init(rdev)) { 49 if (rv515_debugfs_ga_info_init(rdev)) {
70 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 50 DRM_ERROR("Failed to register debugfs file for pipes !\n");
71 } 51 }
72
73 rv515_gpu_init(rdev);
74 rv370_pcie_gart_disable(rdev);
75
76 /* Setup GPU memory space */
77 rdev->mc.vram_location = 0xFFFFFFFFUL;
78 rdev->mc.gtt_location = 0xFFFFFFFFUL;
79 if (rdev->flags & RADEON_IS_AGP) {
80 r = radeon_agp_init(rdev);
81 if (r) {
82 printk(KERN_WARNING "[drm] Disabling AGP\n");
83 rdev->flags &= ~RADEON_IS_AGP;
84 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
85 } else {
86 rdev->mc.gtt_location = rdev->mc.agp_base;
87 }
88 }
89 r = radeon_mc_setup(rdev);
90 if (r) {
91 return r;
92 }
93
94 /* Program GPU memory space */
95 rs600_mc_disable_clients(rdev);
96 if (rv515_mc_wait_for_idle(rdev)) {
97 printk(KERN_WARNING "Failed to wait MC idle while "
98 "programming pipes. Bad things might happen.\n");
99 }
100 /* Write VRAM size in case we are limiting it */
101 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
102 tmp = REG_SET(MC_FB_START, rdev->mc.vram_location >> 16);
103 WREG32(0x134, tmp);
104 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
105 tmp = REG_SET(MC_FB_TOP, tmp >> 16);
106 tmp |= REG_SET(MC_FB_START, rdev->mc.vram_location >> 16);
107 WREG32_MC(MC_FB_LOCATION, tmp);
108 WREG32(HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
109 WREG32(0x310, rdev->mc.vram_location);
110 if (rdev->flags & RADEON_IS_AGP) {
111 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
112 tmp = REG_SET(MC_AGP_TOP, tmp >> 16);
113 tmp |= REG_SET(MC_AGP_START, rdev->mc.gtt_location >> 16);
114 WREG32_MC(MC_AGP_LOCATION, tmp);
115 WREG32_MC(MC_AGP_BASE, rdev->mc.agp_base);
116 WREG32_MC(MC_AGP_BASE_2, 0);
117 } else {
118 WREG32_MC(MC_AGP_LOCATION, 0x0FFFFFFF);
119 WREG32_MC(MC_AGP_BASE, 0);
120 WREG32_MC(MC_AGP_BASE_2, 0);
121 }
122 return 0;
123}
124
125void rv515_mc_fini(struct radeon_device *rdev)
126{
127} 52}
128 53
129
130/*
131 * Global GPU functions
132 */
133void rv515_ring_start(struct radeon_device *rdev) 54void rv515_ring_start(struct radeon_device *rdev)
134{ 55{
135 int r; 56 int r;
@@ -198,11 +119,6 @@ void rv515_ring_start(struct radeon_device *rdev)
198 radeon_ring_unlock_commit(rdev); 119 radeon_ring_unlock_commit(rdev);
199} 120}
200 121
201void rv515_errata(struct radeon_device *rdev)
202{
203 rdev->pll_errata = 0;
204}
205
206int rv515_mc_wait_for_idle(struct radeon_device *rdev) 122int rv515_mc_wait_for_idle(struct radeon_device *rdev)
207{ 123{
208 unsigned i; 124 unsigned i;
@@ -219,6 +135,12 @@ int rv515_mc_wait_for_idle(struct radeon_device *rdev)
219 return -1; 135 return -1;
220} 136}
221 137
138void rv515_vga_render_disable(struct radeon_device *rdev)
139{
140 WREG32(R_000300_VGA_RENDER_CONTROL,
141 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
142}
143
222void rv515_gpu_init(struct radeon_device *rdev) 144void rv515_gpu_init(struct radeon_device *rdev)
223{ 145{
224 unsigned pipe_select_current, gb_pipe_select, tmp; 146 unsigned pipe_select_current, gb_pipe_select, tmp;
@@ -231,7 +153,7 @@ void rv515_gpu_init(struct radeon_device *rdev)
231 "reseting GPU. Bad things might happen.\n"); 153 "reseting GPU. Bad things might happen.\n");
232 } 154 }
233 155
234 rs600_disable_vga(rdev); 156 rv515_vga_render_disable(rdev);
235 157
236 r420_pipes_init(rdev); 158 r420_pipes_init(rdev);
237 gb_pipe_select = RREG32(0x402C); 159 gb_pipe_select = RREG32(0x402C);
@@ -335,10 +257,6 @@ int rv515_gpu_reset(struct radeon_device *rdev)
335 return 0; 257 return 0;
336} 258}
337 259
338
339/*
340 * VRAM info
341 */
342static void rv515_vram_get_type(struct radeon_device *rdev) 260static void rv515_vram_get_type(struct radeon_device *rdev)
343{ 261{
344 uint32_t tmp; 262 uint32_t tmp;
@@ -374,10 +292,6 @@ void rv515_vram_info(struct radeon_device *rdev)
374 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); 292 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
375} 293}
376 294
377
378/*
379 * Indirect registers accessor
380 */
381uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) 295uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
382{ 296{
383 uint32_t r; 297 uint32_t r;
@@ -395,9 +309,6 @@ void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
395 WREG32(MC_IND_INDEX, 0); 309 WREG32(MC_IND_INDEX, 0);
396} 310}
397 311
398/*
399 * Debugfs info
400 */
401#if defined(CONFIG_DEBUG_FS) 312#if defined(CONFIG_DEBUG_FS)
402static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) 313static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
403{ 314{
@@ -459,13 +370,258 @@ int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
459#endif 370#endif
460} 371}
461 372
462/* 373void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
463 * Asic initialization 374{
464 */ 375 save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL);
465int rv515_init(struct radeon_device *rdev) 376 save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL);
377 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
378 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
379 save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);
380 save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
381
382 /* Stop all video */
383 WREG32(R_000330_D1VGA_CONTROL, 0);
384 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
385 WREG32(R_000300_VGA_RENDER_CONTROL, 0);
386 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
387 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
388 WREG32(R_006080_D1CRTC_CONTROL, 0);
389 WREG32(R_006880_D2CRTC_CONTROL, 0);
390 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
391 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
392}
393
394void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
395{
396 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
397 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
398 WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
399 WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
400 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
401 /* Unlock host access */
402 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
403 mdelay(1);
404 /* Restore video state */
405 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
406 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
407 WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
408 WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
409 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
410 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
411 WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
412 WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
413 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
414}
415
416void rv515_mc_program(struct radeon_device *rdev)
417{
418 struct rv515_mc_save save;
419
420 /* Stops all mc clients */
421 rv515_mc_stop(rdev, &save);
422
423 /* Wait for mc idle */
424 if (rv515_mc_wait_for_idle(rdev))
425 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
426 /* Write VRAM size in case we are limiting it */
427 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
428 /* Program MC, should be a 32bits limited address space */
429 WREG32_MC(R_000001_MC_FB_LOCATION,
430 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
431 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
432 WREG32(R_000134_HDP_FB_LOCATION,
433 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
434 if (rdev->flags & RADEON_IS_AGP) {
435 WREG32_MC(R_000002_MC_AGP_LOCATION,
436 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
437 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
438 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
439 WREG32_MC(R_000004_MC_AGP_BASE_2,
440 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
441 } else {
442 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
443 WREG32_MC(R_000003_MC_AGP_BASE, 0);
444 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
445 }
446
447 rv515_mc_resume(rdev, &save);
448}
449
450void rv515_clock_startup(struct radeon_device *rdev)
451{
452 if (radeon_dynclks != -1 && radeon_dynclks)
453 radeon_atom_set_clock_gating(rdev, 1);
454 /* We need to force on some of the block */
455 WREG32_PLL(R_00000F_CP_DYN_CNTL,
456 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
457 WREG32_PLL(R_000011_E2_DYN_CNTL,
458 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
459 WREG32_PLL(R_000013_IDCT_DYN_CNTL,
460 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
461}
462
463static int rv515_startup(struct radeon_device *rdev)
464{
465 int r;
466
467 rv515_mc_program(rdev);
468 /* Resume clock */
469 rv515_clock_startup(rdev);
470 /* Initialize GPU configuration (# pipes, ...) */
471 rv515_gpu_init(rdev);
472 /* Initialize GART (initialize after TTM so we can allocate
473 * memory through TTM but finalize after TTM) */
474 if (rdev->flags & RADEON_IS_PCIE) {
475 r = rv370_pcie_gart_enable(rdev);
476 if (r)
477 return r;
478 }
479 /* Enable IRQ */
480 rdev->irq.sw_int = true;
481 r100_irq_set(rdev);
482 /* 1M ring buffer */
483 r = r100_cp_init(rdev, 1024 * 1024);
484 if (r) {
485 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
486 return r;
487 }
488 r = r100_wb_init(rdev);
489 if (r)
490 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
491 r = r100_ib_init(rdev);
492 if (r) {
493 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
494 return r;
495 }
496 return 0;
497}
498
499int rv515_resume(struct radeon_device *rdev)
500{
501 /* Make sur GART are not working */
502 if (rdev->flags & RADEON_IS_PCIE)
503 rv370_pcie_gart_disable(rdev);
504 /* Resume clock before doing reset */
505 rv515_clock_startup(rdev);
506 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
507 if (radeon_gpu_reset(rdev)) {
508 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
509 RREG32(R_000E40_RBBM_STATUS),
510 RREG32(R_0007C0_CP_STAT));
511 }
512 /* post */
513 atom_asic_init(rdev->mode_info.atom_context);
514 /* Resume clock after posting */
515 rv515_clock_startup(rdev);
516 return rv515_startup(rdev);
517}
518
519int rv515_suspend(struct radeon_device *rdev)
520{
521 r100_cp_disable(rdev);
522 r100_wb_disable(rdev);
523 r100_irq_disable(rdev);
524 if (rdev->flags & RADEON_IS_PCIE)
525 rv370_pcie_gart_disable(rdev);
526 return 0;
527}
528
529void rv515_set_safe_registers(struct radeon_device *rdev)
466{ 530{
467 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; 531 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
468 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); 532 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
533}
534
535void rv515_fini(struct radeon_device *rdev)
536{
537 rv515_suspend(rdev);
538 r100_cp_fini(rdev);
539 r100_wb_fini(rdev);
540 r100_ib_fini(rdev);
541 radeon_gem_fini(rdev);
542 rv370_pcie_gart_fini(rdev);
543 radeon_agp_fini(rdev);
544 radeon_irq_kms_fini(rdev);
545 radeon_fence_driver_fini(rdev);
546 radeon_object_fini(rdev);
547 radeon_atombios_fini(rdev);
548 kfree(rdev->bios);
549 rdev->bios = NULL;
550}
551
552int rv515_init(struct radeon_device *rdev)
553{
554 int r;
555
556 rdev->new_init_path = true;
557 /* Initialize scratch registers */
558 radeon_scratch_init(rdev);
559 /* Initialize surface registers */
560 radeon_surface_init(rdev);
561 /* TODO: disable VGA need to use VGA request */
562 /* BIOS*/
563 if (!radeon_get_bios(rdev)) {
564 if (ASIC_IS_AVIVO(rdev))
565 return -EINVAL;
566 }
567 if (rdev->is_atom_bios) {
568 r = radeon_atombios_init(rdev);
569 if (r)
570 return r;
571 } else {
572 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
573 return -EINVAL;
574 }
575 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
576 if (radeon_gpu_reset(rdev)) {
577 dev_warn(rdev->dev,
578 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
579 RREG32(R_000E40_RBBM_STATUS),
580 RREG32(R_0007C0_CP_STAT));
581 }
582 /* check if cards are posted or not */
583 if (!radeon_card_posted(rdev) && rdev->bios) {
584 DRM_INFO("GPU not posted. posting now...\n");
585 atom_asic_init(rdev->mode_info.atom_context);
586 }
587 /* Initialize clocks */
588 radeon_get_clock_info(rdev->ddev);
589 /* Get vram informations */
590 rv515_vram_info(rdev);
591 /* Initialize memory controller (also test AGP) */
592 r = r420_mc_init(rdev);
593 if (r)
594 return r;
595 rv515_debugfs(rdev);
596 /* Fence driver */
597 r = radeon_fence_driver_init(rdev);
598 if (r)
599 return r;
600 r = radeon_irq_kms_init(rdev);
601 if (r)
602 return r;
603 /* Memory manager */
604 r = radeon_object_init(rdev);
605 if (r)
606 return r;
607 r = rv370_pcie_gart_init(rdev);
608 if (r)
609 return r;
610 rv515_set_safe_registers(rdev);
611 rdev->accel_working = true;
612 r = rv515_startup(rdev);
613 if (r) {
614 /* Somethings want wront with the accel init stop accel */
615 dev_err(rdev->dev, "Disabling GPU acceleration\n");
616 rv515_suspend(rdev);
617 r100_cp_fini(rdev);
618 r100_wb_fini(rdev);
619 r100_ib_fini(rdev);
620 rv370_pcie_gart_fini(rdev);
621 radeon_agp_fini(rdev);
622 radeon_irq_kms_fini(rdev);
623 rdev->accel_working = false;
624 }
469 return 0; 625 return 0;
470} 626}
471 627
diff --git a/drivers/gpu/drm/radeon/rv515d.h b/drivers/gpu/drm/radeon/rv515d.h
index a65e17ec1c08..fc216e49384d 100644
--- a/drivers/gpu/drm/radeon/rv515d.h
+++ b/drivers/gpu/drm/radeon/rv515d.h
@@ -216,5 +216,388 @@
216#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) 216#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
217#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 217#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
218 218
219#endif 219/* Registers */
220#define R_0000F8_CONFIG_MEMSIZE 0x0000F8
221#define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0)
222#define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF)
223#define C_0000F8_CONFIG_MEMSIZE 0x00000000
224#define R_000134_HDP_FB_LOCATION 0x000134
225#define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0)
226#define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF)
227#define C_000134_HDP_FB_START 0xFFFF0000
228#define R_000300_VGA_RENDER_CONTROL 0x000300
229#define S_000300_VGA_BLINK_RATE(x) (((x) & 0x1F) << 0)
230#define G_000300_VGA_BLINK_RATE(x) (((x) >> 0) & 0x1F)
231#define C_000300_VGA_BLINK_RATE 0xFFFFFFE0
232#define S_000300_VGA_BLINK_MODE(x) (((x) & 0x3) << 5)
233#define G_000300_VGA_BLINK_MODE(x) (((x) >> 5) & 0x3)
234#define C_000300_VGA_BLINK_MODE 0xFFFFFF9F
235#define S_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) & 0x1) << 7)
236#define G_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) >> 7) & 0x1)
237#define C_000300_VGA_CURSOR_BLINK_INVERT 0xFFFFFF7F
238#define S_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) & 0x1) << 8)
239#define G_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) >> 8) & 0x1)
240#define C_000300_VGA_EXTD_ADDR_COUNT_ENABLE 0xFFFFFEFF
241#define S_000300_VGA_VSTATUS_CNTL(x) (((x) & 0x3) << 16)
242#define G_000300_VGA_VSTATUS_CNTL(x) (((x) >> 16) & 0x3)
243#define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF
244#define S_000300_VGA_LOCK_8DOT(x) (((x) & 0x1) << 24)
245#define G_000300_VGA_LOCK_8DOT(x) (((x) >> 24) & 0x1)
246#define C_000300_VGA_LOCK_8DOT 0xFEFFFFFF
247#define S_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) & 0x1) << 25)
248#define G_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) >> 25) & 0x1)
249#define C_000300_VGAREG_LINECMP_COMPATIBILITY_SEL 0xFDFFFFFF
250#define R_000310_VGA_MEMORY_BASE_ADDRESS 0x000310
251#define S_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
252#define G_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
253#define C_000310_VGA_MEMORY_BASE_ADDRESS 0x00000000
254#define R_000328_VGA_HDP_CONTROL 0x000328
255#define S_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) & 0x1) << 0)
256#define G_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) >> 0) & 0x1)
257#define C_000328_VGA_MEM_PAGE_SELECT_EN 0xFFFFFFFE
258#define S_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) & 0x1) << 8)
259#define G_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) >> 8) & 0x1)
260#define C_000328_VGA_RBBM_LOCK_DISABLE 0xFFFFFEFF
261#define S_000328_VGA_SOFT_RESET(x) (((x) & 0x1) << 16)
262#define G_000328_VGA_SOFT_RESET(x) (((x) >> 16) & 0x1)
263#define C_000328_VGA_SOFT_RESET 0xFFFEFFFF
264#define S_000328_VGA_TEST_RESET_CONTROL(x) (((x) & 0x1) << 24)
265#define G_000328_VGA_TEST_RESET_CONTROL(x) (((x) >> 24) & 0x1)
266#define C_000328_VGA_TEST_RESET_CONTROL 0xFEFFFFFF
267#define R_000330_D1VGA_CONTROL 0x000330
268#define S_000330_D1VGA_MODE_ENABLE(x) (((x) & 0x1) << 0)
269#define G_000330_D1VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1)
270#define C_000330_D1VGA_MODE_ENABLE 0xFFFFFFFE
271#define S_000330_D1VGA_TIMING_SELECT(x) (((x) & 0x1) << 8)
272#define G_000330_D1VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1)
273#define C_000330_D1VGA_TIMING_SELECT 0xFFFFFEFF
274#define S_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9)
275#define G_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1)
276#define C_000330_D1VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF
277#define S_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10)
278#define G_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1)
279#define C_000330_D1VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF
280#define S_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16)
281#define G_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1)
282#define C_000330_D1VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF
283#define S_000330_D1VGA_ROTATE(x) (((x) & 0x3) << 24)
284#define G_000330_D1VGA_ROTATE(x) (((x) >> 24) & 0x3)
285#define C_000330_D1VGA_ROTATE 0xFCFFFFFF
286#define R_000338_D2VGA_CONTROL 0x000338
287#define S_000338_D2VGA_MODE_ENABLE(x) (((x) & 0x1) << 0)
288#define G_000338_D2VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1)
289#define C_000338_D2VGA_MODE_ENABLE 0xFFFFFFFE
290#define S_000338_D2VGA_TIMING_SELECT(x) (((x) & 0x1) << 8)
291#define G_000338_D2VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1)
292#define C_000338_D2VGA_TIMING_SELECT 0xFFFFFEFF
293#define S_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9)
294#define G_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1)
295#define C_000338_D2VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF
296#define S_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10)
297#define G_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1)
298#define C_000338_D2VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF
299#define S_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16)
300#define G_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1)
301#define C_000338_D2VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF
302#define S_000338_D2VGA_ROTATE(x) (((x) & 0x3) << 24)
303#define G_000338_D2VGA_ROTATE(x) (((x) >> 24) & 0x3)
304#define C_000338_D2VGA_ROTATE 0xFCFFFFFF
305#define R_0007C0_CP_STAT 0x0007C0
306#define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
307#define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
308#define C_0007C0_MRU_BUSY 0xFFFFFFFE
309#define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
310#define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
311#define C_0007C0_MWU_BUSY 0xFFFFFFFD
312#define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
313#define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
314#define C_0007C0_RSIU_BUSY 0xFFFFFFFB
315#define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
316#define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
317#define C_0007C0_RCIU_BUSY 0xFFFFFFF7
318#define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)
319#define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)
320#define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF
321#define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10)
322#define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1)
323#define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF
324#define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11)
325#define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1)
326#define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF
327#define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12)
328#define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1)
329#define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF
330#define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13)
331#define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1)
332#define C_0007C0_CSI_BUSY 0xFFFFDFFF
333#define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14)
334#define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1)
335#define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF
336#define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15)
337#define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1)
338#define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF
339#define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28)
340#define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1)
341#define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF
342#define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29)
343#define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1)
344#define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF
345#define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30)
346#define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1)
347#define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF
348#define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31)
349#define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1)
350#define C_0007C0_CP_BUSY 0x7FFFFFFF
351#define R_000E40_RBBM_STATUS 0x000E40
352#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0)
353#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F)
354#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80
355#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8)
356#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1)
357#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF
358#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9)
359#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1)
360#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF
361#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10)
362#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1)
363#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF
364#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11)
365#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1)
366#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF
367#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12)
368#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1)
369#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF
370#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13)
371#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1)
372#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF
373#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14)
374#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1)
375#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF
376#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15)
377#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1)
378#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF
379#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16)
380#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1)
381#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF
382#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17)
383#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1)
384#define C_000E40_E2_BUSY 0xFFFDFFFF
385#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18)
386#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1)
387#define C_000E40_RB2D_BUSY 0xFFFBFFFF
388#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19)
389#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1)
390#define C_000E40_RB3D_BUSY 0xFFF7FFFF
391#define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20)
392#define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1)
393#define C_000E40_VAP_BUSY 0xFFEFFFFF
394#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21)
395#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1)
396#define C_000E40_RE_BUSY 0xFFDFFFFF
397#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22)
398#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1)
399#define C_000E40_TAM_BUSY 0xFFBFFFFF
400#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23)
401#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1)
402#define C_000E40_TDM_BUSY 0xFF7FFFFF
403#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24)
404#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1)
405#define C_000E40_PB_BUSY 0xFEFFFFFF
406#define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25)
407#define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1)
408#define C_000E40_TIM_BUSY 0xFDFFFFFF
409#define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26)
410#define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1)
411#define C_000E40_GA_BUSY 0xFBFFFFFF
412#define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27)
413#define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1)
414#define C_000E40_CBA2D_BUSY 0xF7FFFFFF
415#define S_000E40_RBBM_HIBUSY(x) (((x) & 0x1) << 28)
416#define G_000E40_RBBM_HIBUSY(x) (((x) >> 28) & 0x1)
417#define C_000E40_RBBM_HIBUSY 0xEFFFFFFF
418#define S_000E40_SKID_CFBUSY(x) (((x) & 0x1) << 29)
419#define G_000E40_SKID_CFBUSY(x) (((x) >> 29) & 0x1)
420#define C_000E40_SKID_CFBUSY 0xDFFFFFFF
421#define S_000E40_VAP_VF_BUSY(x) (((x) & 0x1) << 30)
422#define G_000E40_VAP_VF_BUSY(x) (((x) >> 30) & 0x1)
423#define C_000E40_VAP_VF_BUSY 0xBFFFFFFF
424#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31)
425#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1)
426#define C_000E40_GUI_ACTIVE 0x7FFFFFFF
427#define R_006080_D1CRTC_CONTROL 0x006080
428#define S_006080_D1CRTC_MASTER_EN(x) (((x) & 0x1) << 0)
429#define G_006080_D1CRTC_MASTER_EN(x) (((x) >> 0) & 0x1)
430#define C_006080_D1CRTC_MASTER_EN 0xFFFFFFFE
431#define S_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4)
432#define G_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1)
433#define C_006080_D1CRTC_SYNC_RESET_SEL 0xFFFFFFEF
434#define S_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8)
435#define G_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3)
436#define C_006080_D1CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF
437#define S_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16)
438#define G_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1)
439#define C_006080_D1CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF
440#define S_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24)
441#define G_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1)
442#define C_006080_D1CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF
443#define R_0060E8_D1CRTC_UPDATE_LOCK 0x0060E8
444#define S_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0)
445#define G_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1)
446#define C_0060E8_D1CRTC_UPDATE_LOCK 0xFFFFFFFE
447#define R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x006110
448#define S_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
449#define G_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
450#define C_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000
451#define R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x006118
452#define S_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
453#define G_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
454#define C_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000
455#define R_006880_D2CRTC_CONTROL 0x006880
456#define S_006880_D2CRTC_MASTER_EN(x) (((x) & 0x1) << 0)
457#define G_006880_D2CRTC_MASTER_EN(x) (((x) >> 0) & 0x1)
458#define C_006880_D2CRTC_MASTER_EN 0xFFFFFFFE
459#define S_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4)
460#define G_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1)
461#define C_006880_D2CRTC_SYNC_RESET_SEL 0xFFFFFFEF
462#define S_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8)
463#define G_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3)
464#define C_006880_D2CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF
465#define S_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16)
466#define G_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1)
467#define C_006880_D2CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF
468#define S_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24)
469#define G_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1)
470#define C_006880_D2CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF
471#define R_0068E8_D2CRTC_UPDATE_LOCK 0x0068E8
472#define S_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0)
473#define G_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1)
474#define C_0068E8_D2CRTC_UPDATE_LOCK 0xFFFFFFFE
475#define R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x006910
476#define S_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
477#define G_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
478#define C_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000
479#define R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x006918
480#define S_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
481#define G_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
482#define C_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000
483
484
485#define R_000001_MC_FB_LOCATION 0x000001
486#define S_000001_MC_FB_START(x) (((x) & 0xFFFF) << 0)
487#define G_000001_MC_FB_START(x) (((x) >> 0) & 0xFFFF)
488#define C_000001_MC_FB_START 0xFFFF0000
489#define S_000001_MC_FB_TOP(x) (((x) & 0xFFFF) << 16)
490#define G_000001_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF)
491#define C_000001_MC_FB_TOP 0x0000FFFF
492#define R_000002_MC_AGP_LOCATION 0x000002
493#define S_000002_MC_AGP_START(x) (((x) & 0xFFFF) << 0)
494#define G_000002_MC_AGP_START(x) (((x) >> 0) & 0xFFFF)
495#define C_000002_MC_AGP_START 0xFFFF0000
496#define S_000002_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16)
497#define G_000002_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF)
498#define C_000002_MC_AGP_TOP 0x0000FFFF
499#define R_000003_MC_AGP_BASE 0x000003
500#define S_000003_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
501#define G_000003_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
502#define C_000003_AGP_BASE_ADDR 0x00000000
503#define R_000004_MC_AGP_BASE_2 0x000004
504#define S_000004_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0)
505#define G_000004_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF)
506#define C_000004_AGP_BASE_ADDR_2 0xFFFFFFF0
220 507
508
509#define R_00000F_CP_DYN_CNTL 0x00000F
510#define S_00000F_CP_FORCEON(x) (((x) & 0x1) << 0)
511#define G_00000F_CP_FORCEON(x) (((x) >> 0) & 0x1)
512#define C_00000F_CP_FORCEON 0xFFFFFFFE
513#define S_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1)
514#define G_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1)
515#define C_00000F_CP_MAX_DYN_STOP_LAT 0xFFFFFFFD
516#define S_00000F_CP_CLOCK_STATUS(x) (((x) & 0x1) << 2)
517#define G_00000F_CP_CLOCK_STATUS(x) (((x) >> 2) & 0x1)
518#define C_00000F_CP_CLOCK_STATUS 0xFFFFFFFB
519#define S_00000F_CP_PROG_SHUTOFF(x) (((x) & 0x1) << 3)
520#define G_00000F_CP_PROG_SHUTOFF(x) (((x) >> 3) & 0x1)
521#define C_00000F_CP_PROG_SHUTOFF 0xFFFFFFF7
522#define S_00000F_CP_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4)
523#define G_00000F_CP_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF)
524#define C_00000F_CP_PROG_DELAY_VALUE 0xFFFFF00F
525#define S_00000F_CP_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12)
526#define G_00000F_CP_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF)
527#define C_00000F_CP_LOWER_POWER_IDLE 0xFFF00FFF
528#define S_00000F_CP_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20)
529#define G_00000F_CP_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1)
530#define C_00000F_CP_LOWER_POWER_IGNORE 0xFFEFFFFF
531#define S_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21)
532#define G_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1)
533#define C_00000F_CP_NORMAL_POWER_IGNORE 0xFFDFFFFF
534#define S_00000F_SPARE(x) (((x) & 0x3) << 22)
535#define G_00000F_SPARE(x) (((x) >> 22) & 0x3)
536#define C_00000F_SPARE 0xFF3FFFFF
537#define S_00000F_CP_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24)
538#define G_00000F_CP_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF)
539#define C_00000F_CP_NORMAL_POWER_BUSY 0x00FFFFFF
540#define R_000011_E2_DYN_CNTL 0x000011
541#define S_000011_E2_FORCEON(x) (((x) & 0x1) << 0)
542#define G_000011_E2_FORCEON(x) (((x) >> 0) & 0x1)
543#define C_000011_E2_FORCEON 0xFFFFFFFE
544#define S_000011_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1)
545#define G_000011_E2_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1)
546#define C_000011_E2_MAX_DYN_STOP_LAT 0xFFFFFFFD
547#define S_000011_E2_CLOCK_STATUS(x) (((x) & 0x1) << 2)
548#define G_000011_E2_CLOCK_STATUS(x) (((x) >> 2) & 0x1)
549#define C_000011_E2_CLOCK_STATUS 0xFFFFFFFB
550#define S_000011_E2_PROG_SHUTOFF(x) (((x) & 0x1) << 3)
551#define G_000011_E2_PROG_SHUTOFF(x) (((x) >> 3) & 0x1)
552#define C_000011_E2_PROG_SHUTOFF 0xFFFFFFF7
553#define S_000011_E2_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4)
554#define G_000011_E2_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF)
555#define C_000011_E2_PROG_DELAY_VALUE 0xFFFFF00F
556#define S_000011_E2_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12)
557#define G_000011_E2_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF)
558#define C_000011_E2_LOWER_POWER_IDLE 0xFFF00FFF
559#define S_000011_E2_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20)
560#define G_000011_E2_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1)
561#define C_000011_E2_LOWER_POWER_IGNORE 0xFFEFFFFF
562#define S_000011_E2_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21)
563#define G_000011_E2_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1)
564#define C_000011_E2_NORMAL_POWER_IGNORE 0xFFDFFFFF
565#define S_000011_SPARE(x) (((x) & 0x3) << 22)
566#define G_000011_SPARE(x) (((x) >> 22) & 0x3)
567#define C_000011_SPARE 0xFF3FFFFF
568#define S_000011_E2_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24)
569#define G_000011_E2_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF)
570#define C_000011_E2_NORMAL_POWER_BUSY 0x00FFFFFF
571#define R_000013_IDCT_DYN_CNTL 0x000013
572#define S_000013_IDCT_FORCEON(x) (((x) & 0x1) << 0)
573#define G_000013_IDCT_FORCEON(x) (((x) >> 0) & 0x1)
574#define C_000013_IDCT_FORCEON 0xFFFFFFFE
575#define S_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1)
576#define G_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1)
577#define C_000013_IDCT_MAX_DYN_STOP_LAT 0xFFFFFFFD
578#define S_000013_IDCT_CLOCK_STATUS(x) (((x) & 0x1) << 2)
579#define G_000013_IDCT_CLOCK_STATUS(x) (((x) >> 2) & 0x1)
580#define C_000013_IDCT_CLOCK_STATUS 0xFFFFFFFB
581#define S_000013_IDCT_PROG_SHUTOFF(x) (((x) & 0x1) << 3)
582#define G_000013_IDCT_PROG_SHUTOFF(x) (((x) >> 3) & 0x1)
583#define C_000013_IDCT_PROG_SHUTOFF 0xFFFFFFF7
584#define S_000013_IDCT_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4)
585#define G_000013_IDCT_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF)
586#define C_000013_IDCT_PROG_DELAY_VALUE 0xFFFFF00F
587#define S_000013_IDCT_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12)
588#define G_000013_IDCT_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF)
589#define C_000013_IDCT_LOWER_POWER_IDLE 0xFFF00FFF
590#define S_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20)
591#define G_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1)
592#define C_000013_IDCT_LOWER_POWER_IGNORE 0xFFEFFFFF
593#define S_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21)
594#define G_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1)
595#define C_000013_IDCT_NORMAL_POWER_IGNORE 0xFFDFFFFF
596#define S_000013_SPARE(x) (((x) & 0x3) << 22)
597#define G_000013_SPARE(x) (((x) >> 22) & 0x3)
598#define C_000013_SPARE 0xFF3FFFFF
599#define S_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24)
600#define G_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF)
601#define C_000013_IDCT_NORMAL_POWER_BUSY 0x00FFFFFF
602
603#endif
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index efca509b24f6..e0b97d161397 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -31,8 +31,8 @@
31#include "radeon.h" 31#include "radeon.h"
32#include "radeon_drm.h" 32#include "radeon_drm.h"
33#include "rv770d.h" 33#include "rv770d.h"
34#include "avivod.h"
35#include "atom.h" 34#include "atom.h"
35#include "avivod.h"
36 36
37#define R700_PFP_UCODE_SIZE 848 37#define R700_PFP_UCODE_SIZE 848
38#define R700_PM4_UCODE_SIZE 1360 38#define R700_PM4_UCODE_SIZE 1360
@@ -231,7 +231,7 @@ static void rv770_mc_resume(struct radeon_device *rdev)
231 231
232 /* we need to own VRAM, so turn off the VGA renderer here 232 /* we need to own VRAM, so turn off the VGA renderer here
233 * to stop it overwriting our objects */ 233 * to stop it overwriting our objects */
234 radeon_avivo_vga_render_disable(rdev); 234 rv515_vga_render_disable(rdev);
235} 235}
236 236
237 237
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 11:55:23 -0500