diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2011-06-23 02:37:00 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2011-09-20 02:11:55 -0400 |
commit | 8ce51fcfee2355cc38ea6fd3062d94bb38dfbaf0 (patch) | |
tree | 0bff98ac2f51951a7676a26b03f003c421b92a51 /drivers/gpu | |
parent | 59ef9742f6b24d1f3062b975ec959512519f8987 (diff) |
drm/nvc0/pm: minor clock readback fixes
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/nouveau/nvc0_pm.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/drm/nouveau/nvc0_pm.c b/drivers/gpu/drm/nouveau/nvc0_pm.c index 6dc1a974b577..929aded35cb5 100644 --- a/drivers/gpu/drm/nouveau/nvc0_pm.c +++ b/drivers/gpu/drm/nouveau/nvc0_pm.c | |||
@@ -42,12 +42,16 @@ read_vco(struct drm_device *dev, u32 dsrc) | |||
42 | static u32 | 42 | static u32 |
43 | read_pll(struct drm_device *dev, u32 pll) | 43 | read_pll(struct drm_device *dev, u32 pll) |
44 | { | 44 | { |
45 | u32 ctrl = nv_rd32(dev, pll + 0); | ||
45 | u32 coef = nv_rd32(dev, pll + 4); | 46 | u32 coef = nv_rd32(dev, pll + 4); |
46 | u32 P = (coef & 0x003f0000) >> 16; | 47 | u32 P = (coef & 0x003f0000) >> 16; |
47 | u32 N = (coef & 0x0000ff00) >> 8; | 48 | u32 N = (coef & 0x0000ff00) >> 8; |
48 | u32 M = (coef & 0x000000ff) >> 0; | 49 | u32 M = (coef & 0x000000ff) >> 0; |
49 | u32 sclk, doff; | 50 | u32 sclk, doff; |
50 | 51 | ||
52 | if (!(ctrl & 0x00000001)) | ||
53 | return 0; | ||
54 | |||
51 | switch (pll & 0xfff000) { | 55 | switch (pll & 0xfff000) { |
52 | case 0x00e000: | 56 | case 0x00e000: |
53 | sclk = 27000; | 57 | sclk = 27000; |
@@ -91,12 +95,12 @@ read_div(struct drm_device *dev, int doff, u32 dsrc, u32 dctl) | |||
91 | return 100000; | 95 | return 100000; |
92 | case 3: | 96 | case 3: |
93 | if (sctl & 0x80000000) { | 97 | if (sctl & 0x80000000) { |
94 | u32 sclk = read_vco(dev, dsrc); | 98 | u32 sclk = read_vco(dev, dsrc + (doff * 4)); |
95 | u32 sdiv = (sctl & 0x0000003f) + 2; | 99 | u32 sdiv = (sctl & 0x0000003f) + 2; |
96 | return (sclk * 2) / sdiv; | 100 | return (sclk * 2) / sdiv; |
97 | } | 101 | } |
98 | 102 | ||
99 | return read_vco(dev, dsrc); | 103 | return read_vco(dev, dsrc + (doff * 4)); |
100 | default: | 104 | default: |
101 | return 0; | 105 | return 0; |
102 | } | 106 | } |