diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2010-04-22 14:25:19 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2010-05-18 04:21:08 -0400 |
commit | 79daedc942813c0417ff5e277da6f7f35705cde5 (patch) | |
tree | 36f08e83553eb048066fc0374da971aa8861d3ec /drivers/gpu | |
parent | d91eeb7862a4a5f7c5c92b953fa69d2f1430e840 (diff) |
drm/radeon/kms: minor pm cleanups
- remove non_clock_info struct
- track power state misc flags
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/radeon/r100.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 13 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_atombios.c | 22 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_combios.c | 15 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_pm.c | 2 |
6 files changed, 24 insertions, 32 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index a6b2aca36b47..f10b747024f1 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c | |||
@@ -137,7 +137,7 @@ void r100_get_power_state(struct radeon_device *rdev, | |||
137 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | 137 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
138 | clock_info[rdev->pm.requested_clock_mode_index].mclk, | 138 | clock_info[rdev->pm.requested_clock_mode_index].mclk, |
139 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | 139 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
140 | non_clock_info.pcie_lanes); | 140 | pcie_lanes); |
141 | } | 141 | } |
142 | 142 | ||
143 | void r100_set_power_state(struct radeon_device *rdev) | 143 | void r100_set_power_state(struct radeon_device *rdev) |
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index cc2797949ee5..35a5d4856f46 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -234,7 +234,7 @@ void r600_get_power_state(struct radeon_device *rdev, | |||
234 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | 234 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
235 | clock_info[rdev->pm.requested_clock_mode_index].mclk, | 235 | clock_info[rdev->pm.requested_clock_mode_index].mclk, |
236 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | 236 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
237 | non_clock_info.pcie_lanes); | 237 | pcie_lanes); |
238 | } | 238 | } |
239 | 239 | ||
240 | void r600_set_power_state(struct radeon_device *rdev) | 240 | void r600_set_power_state(struct radeon_device *rdev) |
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index b5eccc4094e8..b9ad976cfb9c 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -654,13 +654,6 @@ struct radeon_voltage { | |||
654 | u32 voltage; | 654 | u32 voltage; |
655 | }; | 655 | }; |
656 | 656 | ||
657 | struct radeon_pm_non_clock_info { | ||
658 | /* pcie lanes */ | ||
659 | int pcie_lanes; | ||
660 | /* standardized non-clock flags */ | ||
661 | u32 flags; | ||
662 | }; | ||
663 | |||
664 | struct radeon_pm_clock_info { | 657 | struct radeon_pm_clock_info { |
665 | /* memory clock */ | 658 | /* memory clock */ |
666 | u32 mclk; | 659 | u32 mclk; |
@@ -682,11 +675,11 @@ struct radeon_power_state { | |||
682 | /* number of valid clock modes in this power state */ | 675 | /* number of valid clock modes in this power state */ |
683 | int num_clock_modes; | 676 | int num_clock_modes; |
684 | struct radeon_pm_clock_info *default_clock_mode; | 677 | struct radeon_pm_clock_info *default_clock_mode; |
685 | /* non clock info about this state */ | ||
686 | struct radeon_pm_non_clock_info non_clock_info; | ||
687 | bool voltage_drop_active; | ||
688 | /* standardized state flags */ | 678 | /* standardized state flags */ |
689 | u32 flags; | 679 | u32 flags; |
680 | u32 misc; /* vbios specific flags */ | ||
681 | u32 misc2; /* vbios specific flags */ | ||
682 | int pcie_lanes; /* pcie lanes */ | ||
690 | }; | 683 | }; |
691 | 684 | ||
692 | /* | 685 | /* |
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index a0a99b66af82..c29ac74a1d20 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c | |||
@@ -1528,7 +1528,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) | |||
1528 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || | 1528 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || |
1529 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) | 1529 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) |
1530 | continue; | 1530 | continue; |
1531 | rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = | 1531 | rdev->pm.power_state[state_index].pcie_lanes = |
1532 | power_info->info.asPowerPlayInfo[i].ucNumPciELanes; | 1532 | power_info->info.asPowerPlayInfo[i].ucNumPciELanes; |
1533 | misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); | 1533 | misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); |
1534 | if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { | 1534 | if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { |
@@ -1550,6 +1550,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) | |||
1550 | power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; | 1550 | power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; |
1551 | } | 1551 | } |
1552 | rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY; | 1552 | rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY; |
1553 | rdev->pm.power_state[state_index].misc = misc; | ||
1553 | /* order matters! */ | 1554 | /* order matters! */ |
1554 | if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) | 1555 | if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) |
1555 | rdev->pm.power_state[state_index].type = | 1556 | rdev->pm.power_state[state_index].type = |
@@ -1590,7 +1591,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) | |||
1590 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || | 1591 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || |
1591 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) | 1592 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) |
1592 | continue; | 1593 | continue; |
1593 | rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = | 1594 | rdev->pm.power_state[state_index].pcie_lanes = |
1594 | power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; | 1595 | power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; |
1595 | misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); | 1596 | misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); |
1596 | misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2); | 1597 | misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2); |
@@ -1613,6 +1614,8 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) | |||
1613 | power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; | 1614 | power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; |
1614 | } | 1615 | } |
1615 | rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY; | 1616 | rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY; |
1617 | rdev->pm.power_state[state_index].misc = misc; | ||
1618 | rdev->pm.power_state[state_index].misc2 = misc2; | ||
1616 | /* order matters! */ | 1619 | /* order matters! */ |
1617 | if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) | 1620 | if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) |
1618 | rdev->pm.power_state[state_index].type = | 1621 | rdev->pm.power_state[state_index].type = |
@@ -1659,7 +1662,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) | |||
1659 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || | 1662 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || |
1660 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) | 1663 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) |
1661 | continue; | 1664 | continue; |
1662 | rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = | 1665 | rdev->pm.power_state[state_index].pcie_lanes = |
1663 | power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; | 1666 | power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; |
1664 | misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); | 1667 | misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); |
1665 | misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2); | 1668 | misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2); |
@@ -1688,6 +1691,8 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) | |||
1688 | } | 1691 | } |
1689 | } | 1692 | } |
1690 | rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY; | 1693 | rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY; |
1694 | rdev->pm.power_state[state_index].misc = misc; | ||
1695 | rdev->pm.power_state[state_index].misc2 = misc2; | ||
1691 | /* order matters! */ | 1696 | /* order matters! */ |
1692 | if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) | 1697 | if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) |
1693 | rdev->pm.power_state[state_index].type = | 1698 | rdev->pm.power_state[state_index].type = |
@@ -1730,6 +1735,8 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) | |||
1730 | &rdev->pm.power_state[state_index - 1].clock_info[0]; | 1735 | &rdev->pm.power_state[state_index - 1].clock_info[0]; |
1731 | rdev->pm.power_state[state_index].flags &= | 1736 | rdev->pm.power_state[state_index].flags &= |
1732 | ~RADEON_PM_SINGLE_DISPLAY_ONLY; | 1737 | ~RADEON_PM_SINGLE_DISPLAY_ONLY; |
1738 | rdev->pm.power_state[state_index].misc = 0; | ||
1739 | rdev->pm.power_state[state_index].misc2 = 0; | ||
1733 | } | 1740 | } |
1734 | } else { | 1741 | } else { |
1735 | /* add the i2c bus for thermal/fan chip */ | 1742 | /* add the i2c bus for thermal/fan chip */ |
@@ -1852,7 +1859,9 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) | |||
1852 | if (mode_index) { | 1859 | if (mode_index) { |
1853 | misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); | 1860 | misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); |
1854 | misc2 = le16_to_cpu(non_clock_info->usClassification); | 1861 | misc2 = le16_to_cpu(non_clock_info->usClassification); |
1855 | rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = | 1862 | rdev->pm.power_state[state_index].misc = misc; |
1863 | rdev->pm.power_state[state_index].misc2 = misc2; | ||
1864 | rdev->pm.power_state[state_index].pcie_lanes = | ||
1856 | ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> | 1865 | ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> |
1857 | ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; | 1866 | ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; |
1858 | switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { | 1867 | switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { |
@@ -1902,10 +1911,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) | |||
1902 | rdev->pm.power_state[state_index].default_clock_mode = | 1911 | rdev->pm.power_state[state_index].default_clock_mode = |
1903 | &rdev->pm.power_state[state_index].clock_info[0]; | 1912 | &rdev->pm.power_state[state_index].clock_info[0]; |
1904 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; | 1913 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
1905 | if (rdev->asic->get_pcie_lanes) | 1914 | rdev->pm.power_state[state_index].pcie_lanes = 16; |
1906 | rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev); | ||
1907 | else | ||
1908 | rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16; | ||
1909 | rdev->pm.default_power_state_index = state_index; | 1915 | rdev->pm.default_power_state_index = state_index; |
1910 | rdev->pm.power_state[state_index].flags = 0; | 1916 | rdev->pm.power_state[state_index].flags = 0; |
1911 | state_index++; | 1917 | state_index++; |
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c index 6a9ec8511261..c22344b7fc58 100644 --- a/drivers/gpu/drm/radeon/radeon_combios.c +++ b/drivers/gpu/drm/radeon/radeon_combios.c | |||
@@ -2382,17 +2382,13 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev) | |||
2382 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || | 2382 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || |
2383 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) | 2383 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) |
2384 | goto default_mode; | 2384 | goto default_mode; |
2385 | /* skip overclock modes for now */ | ||
2386 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk > | ||
2387 | rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) || | ||
2388 | (rdev->pm.power_state[state_index].clock_info[0].sclk > | ||
2389 | rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)) | ||
2390 | goto default_mode; | ||
2391 | rdev->pm.power_state[state_index].type = | 2385 | rdev->pm.power_state[state_index].type = |
2392 | POWER_STATE_TYPE_BATTERY; | 2386 | POWER_STATE_TYPE_BATTERY; |
2393 | misc = RBIOS16(offset + 0x5 + 0x0); | 2387 | misc = RBIOS16(offset + 0x5 + 0x0); |
2394 | if (rev > 4) | 2388 | if (rev > 4) |
2395 | misc2 = RBIOS16(offset + 0x5 + 0xe); | 2389 | misc2 = RBIOS16(offset + 0x5 + 0xe); |
2390 | rdev->pm.power_state[state_index].misc = misc; | ||
2391 | rdev->pm.power_state[state_index].misc2 = misc2; | ||
2396 | if (misc & 0x4) { | 2392 | if (misc & 0x4) { |
2397 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; | 2393 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; |
2398 | if (misc & 0x8) | 2394 | if (misc & 0x8) |
@@ -2439,7 +2435,7 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev) | |||
2439 | } else | 2435 | } else |
2440 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; | 2436 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
2441 | if (rev > 6) | 2437 | if (rev > 6) |
2442 | rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = | 2438 | rdev->pm.power_state[state_index].pcie_lanes = |
2443 | RBIOS8(offset + 0x5 + 0x10); | 2439 | RBIOS8(offset + 0x5 + 0x10); |
2444 | rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY; | 2440 | rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY; |
2445 | state_index++; | 2441 | state_index++; |
@@ -2459,10 +2455,7 @@ default_mode: | |||
2459 | rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; | 2455 | rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; |
2460 | rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; | 2456 | rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; |
2461 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; | 2457 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
2462 | if (rdev->asic->get_pcie_lanes) | 2458 | rdev->pm.power_state[state_index].pcie_lanes = 16; |
2463 | rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev); | ||
2464 | else | ||
2465 | rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16; | ||
2466 | rdev->pm.power_state[state_index].flags = 0; | 2459 | rdev->pm.power_state[state_index].flags = 0; |
2467 | rdev->pm.default_power_state_index = state_index; | 2460 | rdev->pm.default_power_state_index = state_index; |
2468 | rdev->pm.num_power_states = state_index + 1; | 2461 | rdev->pm.num_power_states = state_index + 1; |
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 1febb62bdd95..87814eb8a1b4 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c | |||
@@ -64,7 +64,7 @@ static void radeon_print_power_mode_info(struct radeon_device *rdev) | |||
64 | pm_state_types[rdev->pm.power_state[i].type], | 64 | pm_state_types[rdev->pm.power_state[i].type], |
65 | is_default ? "(default)" : ""); | 65 | is_default ? "(default)" : ""); |
66 | if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) | 66 | if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) |
67 | DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].non_clock_info.pcie_lanes); | 67 | DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].pcie_lanes); |
68 | if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY) | 68 | if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY) |
69 | DRM_INFO("\tSingle display only\n"); | 69 | DRM_INFO("\tSingle display only\n"); |
70 | DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes); | 70 | DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes); |