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authorAlex Deucher <alexander.deucher@amd.com>2013-07-17 10:52:43 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-07-17 14:52:48 -0400
commit77c7d50a4a9f1fa3aa42adad00e7b44aa70ec910 (patch)
treeebe496453b1b7d76b1a2ed61ffefa95379f7aa81 /drivers/gpu
parent1fa4252af760560f77ca3d5d360fd62df3292c7f (diff)
drm/radeon/dpm: fix atom vram table parsing
Parsing the table in incorrectly led to problems with certain asics with mclk switching. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c26
1 files changed, 10 insertions, 16 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 0c3455a73992..a2e324188bc9 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -3513,7 +3513,6 @@ int radeon_atom_get_memory_info(struct radeon_device *rdev,
3513 u8 frev, crev, i; 3513 u8 frev, crev, i;
3514 u16 data_offset, size; 3514 u16 data_offset, size;
3515 union vram_info *vram_info; 3515 union vram_info *vram_info;
3516 u8 *p;
3517 3516
3518 memset(mem_info, 0, sizeof(struct atom_memory_info)); 3517 memset(mem_info, 0, sizeof(struct atom_memory_info));
3519 3518
@@ -3529,13 +3528,12 @@ int radeon_atom_get_memory_info(struct radeon_device *rdev,
3529 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) { 3528 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3530 ATOM_VRAM_MODULE_V3 *vram_module = 3529 ATOM_VRAM_MODULE_V3 *vram_module =
3531 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo; 3530 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3532 p = (u8 *)vram_info->v1_3.aVramInfo;
3533 3531
3534 for (i = 0; i < module_index; i++) { 3532 for (i = 0; i < module_index; i++) {
3535 vram_module = (ATOM_VRAM_MODULE_V3 *)p;
3536 if (le16_to_cpu(vram_module->usSize) == 0) 3533 if (le16_to_cpu(vram_module->usSize) == 0)
3537 return -EINVAL; 3534 return -EINVAL;
3538 p += le16_to_cpu(vram_module->usSize); 3535 vram_module = (ATOM_VRAM_MODULE_V3 *)
3536 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3539 } 3537 }
3540 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf; 3538 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3541 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0; 3539 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
@@ -3547,13 +3545,12 @@ int radeon_atom_get_memory_info(struct radeon_device *rdev,
3547 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { 3545 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3548 ATOM_VRAM_MODULE_V4 *vram_module = 3546 ATOM_VRAM_MODULE_V4 *vram_module =
3549 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; 3547 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3550 p = (u8 *)vram_info->v1_4.aVramInfo;
3551 3548
3552 for (i = 0; i < module_index; i++) { 3549 for (i = 0; i < module_index; i++) {
3553 vram_module = (ATOM_VRAM_MODULE_V4 *)p;
3554 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3550 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3555 return -EINVAL; 3551 return -EINVAL;
3556 p += le16_to_cpu(vram_module->usModuleSize); 3552 vram_module = (ATOM_VRAM_MODULE_V4 *)
3553 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3557 } 3554 }
3558 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; 3555 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3559 mem_info->mem_type = vram_module->ucMemoryType & 0xf0; 3556 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
@@ -3572,13 +3569,12 @@ int radeon_atom_get_memory_info(struct radeon_device *rdev,
3572 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 3569 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3573 ATOM_VRAM_MODULE_V7 *vram_module = 3570 ATOM_VRAM_MODULE_V7 *vram_module =
3574 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo; 3571 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3575 p = (u8 *)vram_info->v2_1.aVramInfo;
3576 3572
3577 for (i = 0; i < module_index; i++) { 3573 for (i = 0; i < module_index; i++) {
3578 vram_module = (ATOM_VRAM_MODULE_V7 *)p;
3579 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3574 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3580 return -EINVAL; 3575 return -EINVAL;
3581 p += le16_to_cpu(vram_module->usModuleSize); 3576 vram_module = (ATOM_VRAM_MODULE_V7 *)
3577 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3582 } 3578 }
3583 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; 3579 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3584 mem_info->mem_type = vram_module->ucMemoryType & 0xf0; 3580 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
@@ -3628,21 +3624,19 @@ int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3628 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { 3624 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3629 ATOM_VRAM_MODULE_V4 *vram_module = 3625 ATOM_VRAM_MODULE_V4 *vram_module =
3630 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; 3626 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3631 ATOM_MEMORY_TIMING_FORMAT *format;
3632 p = (u8 *)vram_info->v1_4.aVramInfo;
3633 3627
3634 for (i = 0; i < module_index; i++) { 3628 for (i = 0; i < module_index; i++) {
3635 vram_module = (ATOM_VRAM_MODULE_V4 *)p;
3636 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3629 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3637 return -EINVAL; 3630 return -EINVAL;
3638 p += le16_to_cpu(vram_module->usModuleSize); 3631 vram_module = (ATOM_VRAM_MODULE_V4 *)
3632 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3639 } 3633 }
3640 mclk_range_table->num_entries = (u8) 3634 mclk_range_table->num_entries = (u8)
3641 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) / 3635 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3642 mem_timing_size); 3636 mem_timing_size);
3643 p = (u8 *)vram_module->asMemTiming; 3637 p = (u8 *)&vram_module->asMemTiming[0];
3644 for (i = 0; i < mclk_range_table->num_entries; i++) { 3638 for (i = 0; i < mclk_range_table->num_entries; i++) {
3645 format = (ATOM_MEMORY_TIMING_FORMAT *)p; 3639 ATOM_MEMORY_TIMING_FORMAT *format = (ATOM_MEMORY_TIMING_FORMAT *)p;
3646 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange); 3640 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3647 p += mem_timing_size; 3641 p += mem_timing_size;
3648 } 3642 }