drm/i915: Re-use set_base_atomic to share setting of the display registers

Lets try to avoid repeating old bugs.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

1 files changed, 9 insertions, 71 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 334665cbe7df..cbb509383089 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1502,7 +1502,7 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
                         dspcntr &= ~DISPPLANE_TILED;
         }
 
-        if (IS_IRONLAKE(dev))
+        if (HAS_PCH_SPLIT(dev))
                 /* must disable */
                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
 
@@ -1511,20 +1511,19 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
         Start = obj_priv->gtt_offset;
         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
 
-        DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
+        DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
+                      Start, Offset, x, y, fb->pitch);
         I915_WRITE(dspstride, fb->pitch);
         if (IS_I965G(dev)) {
-                I915_WRITE(dspbase, Offset);
-                I915_READ(dspbase);
                 I915_WRITE(dspsurf, Start);
-                I915_READ(dspsurf);
                 I915_WRITE(dsptileoff, (y << 16) | x);
+                I915_WRITE(dspbase, Offset);
         } else {
                 I915_WRITE(dspbase, Start + Offset);
-                I915_READ(dspbase);
         }
+        POSTING_READ(dspbase);
 
-        if ((IS_I965G(dev) || plane == 0))
+        if (IS_I965G(dev) || plane == 0)
                 intel_update_fbc(crtc, &crtc->mode);
 
         intel_wait_for_vblank(dev, intel_crtc->pipe);
@@ -1538,7 +1537,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                     struct drm_framebuffer *old_fb)
 {
         struct drm_device *dev = crtc->dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
         struct drm_i915_master_private *master_priv;
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         struct intel_framebuffer *intel_fb;
@@ -1546,13 +1544,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
         struct drm_gem_object *obj;
         int pipe = intel_crtc->pipe;
         int plane = intel_crtc->plane;
-        unsigned long Start, Offset;
-        int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
-        int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
-        int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
-        int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
-        int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
-        u32 dspcntr;
         int ret;
 
         /* no fb bound */
@@ -1588,71 +1579,18 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                 return ret;
         }
 
-        dspcntr = I915_READ(dspcntr_reg);
-        /* Mask out pixel format bits in case we change it */
-        dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
-        switch (crtc->fb->bits_per_pixel) {
-        case 8:
-                dspcntr |= DISPPLANE_8BPP;
-                break;
-        case 16:
-                if (crtc->fb->depth == 15)
-                        dspcntr |= DISPPLANE_15_16BPP;
-                else
-                        dspcntr |= DISPPLANE_16BPP;
-                break;
-        case 24:
-        case 32:
-                if (crtc->fb->depth == 30)
-                        dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
-                else
-                        dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
-                break;
-        default:
-                DRM_ERROR("Unknown color depth\n");
+        ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
+        if (ret) {
                 i915_gem_object_unpin(obj);
                 mutex_unlock(&dev->struct_mutex);
-                return -EINVAL;
-        }
-        if (IS_I965G(dev)) {
-                if (obj_priv->tiling_mode != I915_TILING_NONE)
-                        dspcntr |= DISPPLANE_TILED;
-                else
-                        dspcntr &= ~DISPPLANE_TILED;
-        }
-
-        if (HAS_PCH_SPLIT(dev))
-                /* must disable */
-                dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
-
-        I915_WRITE(dspcntr_reg, dspcntr);
-
-        Start = obj_priv->gtt_offset;
-        Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
-
-        DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
-                      Start, Offset, x, y, crtc->fb->pitch);
-        I915_WRITE(dspstride, crtc->fb->pitch);
-        if (IS_I965G(dev)) {
-                I915_WRITE(dspsurf, Start);
-                I915_WRITE(dsptileoff, (y << 16) | x);
-                I915_WRITE(dspbase, Offset);
-        } else {
-                I915_WRITE(dspbase, Start + Offset);
+                return ret;
         }
-        POSTING_READ(dspbase);
-
-        if ((IS_I965G(dev) || plane == 0))
-                intel_update_fbc(crtc, &crtc->mode);
-
-        intel_wait_for_vblank(dev, pipe);
 
         if (old_fb) {
                 intel_fb = to_intel_framebuffer(old_fb);
                 obj_priv = to_intel_bo(intel_fb->obj);
                 i915_gem_object_unpin(intel_fb->obj);
         }
-        intel_increase_pllclock(crtc, true);
 
         mutex_unlock(&dev->struct_mutex);