drm/radeon/kms/atom: add support for DCE6.x dig transmitters

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 57 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index b88c4608731b..28b55dab8d4f 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -703,6 +703,7 @@ union dig_transmitter_control {
         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
+        DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
 };
 
 void
@@ -723,6 +724,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
         int connector_object_id = 0;
         int igp_lane_info = 0;
         int dig_encoder = dig->dig_encoder;
+        int hpd_id = RADEON_HPD_NONE;
 
         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
                 connector = radeon_get_connector_for_encoder_init(encoder);
@@ -738,6 +740,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
                 struct radeon_connector_atom_dig *dig_connector =
                         radeon_connector->con_priv;
 
+                hpd_id = radeon_connector->hpd.hpd;
                 dp_clock = dig_connector->dp_clock;
                 dp_lane_count = dig_connector->dp_lane_count;
                 connector_object_id =
@@ -1003,6 +1006,60 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
                                         args.v4.acConfig.fDualLinkConnector = 1;
                         }
                         break;
+                case 5:
+                        args.v5.ucAction = action;
+                        if (is_dp)
+                                args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
+                        else
+                                args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
+
+                        switch (radeon_encoder->encoder_id) {
+                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+                                if (dig->linkb)
+                                        args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
+                                else
+                                        args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
+                                break;
+                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+                                if (dig->linkb)
+                                        args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
+                                else
+                                        args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
+                                break;
+                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+                                if (dig->linkb)
+                                        args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
+                                else
+                                        args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
+                                break;
+                        }
+                        if (is_dp)
+                                args.v5.ucLaneNum = dp_lane_count;
+                        else if (radeon_encoder->pixel_clock > 165000)
+                                args.v5.ucLaneNum = 8;
+                        else
+                                args.v5.ucLaneNum = 4;
+                        args.v5.ucConnObjId = connector_object_id;
+                        args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
+
+                        if (is_dp && rdev->clock.dp_extclk)
+                                args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
+                        else
+                                args.v5.asConfig.ucPhyClkSrcId = pll_id;
+
+                        if (is_dp)
+                                args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
+                        else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
+                                if (dig->coherent_mode)
+                                        args.v5.asConfig.ucCoherentMode = 1;
+                        }
+                        if (hpd_id == RADEON_HPD_NONE)
+                                args.v5.asConfig.ucHPDSel = 0;
+                        else
+                                args.v5.asConfig.ucHPDSel = hpd_id + 1;
+                        args.v5.ucDigEncoderSel = 1 << dig_encoder;
+                        args.v5.ucDPLaneSet = lane_set;
+                        break;
                 default:
                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
                         break;