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authorAlex Deucher <alexander.deucher@amd.com>2011-09-16 12:04:08 -0400
committerDave Airlie <airlied@redhat.com>2011-09-18 14:44:36 -0400
commit003cefe0c238e683a29d2207dba945b508cd45b7 (patch)
treeeb310780feff0bbdccda730dceb67a4379dea04c /drivers/gpu
parent18b4fada275dd2b6dd9db904ddf70fe39e272222 (diff)
drm/radeon/kms: Make GPU/CPU page size handling consistent in blit code (v2)
The BO blit code inconsistenly handled the page size. This wasn't an issue on system with 4k pages since the GPU's page size is 4k as well. Switch the driver blit callbacks to take num pages in GPU page units. Fixes lemote mipsel systems using AMD rs780/rs880 chipsets. v2: incorporate suggestions from Michel. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c10
-rw-r--r--drivers/gpu/drm/radeon/r100.c12
-rw-r--r--drivers/gpu/drm/radeon/r200.c4
-rw-r--r--drivers/gpu/drm/radeon/r600.c10
-rw-r--r--drivers/gpu/drm/radeon/radeon.h7
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h8
-rw-r--r--drivers/gpu/drm/radeon/radeon_ttm.c7
7 files changed, 34 insertions, 24 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index f10d1c1c2554..e8a746712b5b 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -3171,21 +3171,23 @@ int evergreen_suspend(struct radeon_device *rdev)
3171} 3171}
3172 3172
3173int evergreen_copy_blit(struct radeon_device *rdev, 3173int evergreen_copy_blit(struct radeon_device *rdev,
3174 uint64_t src_offset, uint64_t dst_offset, 3174 uint64_t src_offset,
3175 unsigned num_pages, struct radeon_fence *fence) 3175 uint64_t dst_offset,
3176 unsigned num_gpu_pages,
3177 struct radeon_fence *fence)
3176{ 3178{
3177 int r; 3179 int r;
3178 3180
3179 mutex_lock(&rdev->r600_blit.mutex); 3181 mutex_lock(&rdev->r600_blit.mutex);
3180 rdev->r600_blit.vb_ib = NULL; 3182 rdev->r600_blit.vb_ib = NULL;
3181 r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE); 3183 r = evergreen_blit_prepare_copy(rdev, num_gpu_pages * RADEON_GPU_PAGE_SIZE);
3182 if (r) { 3184 if (r) {
3183 if (rdev->r600_blit.vb_ib) 3185 if (rdev->r600_blit.vb_ib)
3184 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); 3186 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
3185 mutex_unlock(&rdev->r600_blit.mutex); 3187 mutex_unlock(&rdev->r600_blit.mutex);
3186 return r; 3188 return r;
3187 } 3189 }
3188 evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE); 3190 evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages * RADEON_GPU_PAGE_SIZE);
3189 evergreen_blit_done_copy(rdev, fence); 3191 evergreen_blit_done_copy(rdev, fence);
3190 mutex_unlock(&rdev->r600_blit.mutex); 3192 mutex_unlock(&rdev->r600_blit.mutex);
3191 return 0; 3193 return 0;
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index a536505342d8..5b1837b4aacf 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -721,11 +721,11 @@ void r100_fence_ring_emit(struct radeon_device *rdev,
721int r100_copy_blit(struct radeon_device *rdev, 721int r100_copy_blit(struct radeon_device *rdev,
722 uint64_t src_offset, 722 uint64_t src_offset,
723 uint64_t dst_offset, 723 uint64_t dst_offset,
724 unsigned num_pages, 724 unsigned num_gpu_pages,
725 struct radeon_fence *fence) 725 struct radeon_fence *fence)
726{ 726{
727 uint32_t cur_pages; 727 uint32_t cur_pages;
728 uint32_t stride_bytes = PAGE_SIZE; 728 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
729 uint32_t pitch; 729 uint32_t pitch;
730 uint32_t stride_pixels; 730 uint32_t stride_pixels;
731 unsigned ndw; 731 unsigned ndw;
@@ -737,7 +737,7 @@ int r100_copy_blit(struct radeon_device *rdev,
737 /* radeon pitch is /64 */ 737 /* radeon pitch is /64 */
738 pitch = stride_bytes / 64; 738 pitch = stride_bytes / 64;
739 stride_pixels = stride_bytes / 4; 739 stride_pixels = stride_bytes / 4;
740 num_loops = DIV_ROUND_UP(num_pages, 8191); 740 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
741 741
742 /* Ask for enough room for blit + flush + fence */ 742 /* Ask for enough room for blit + flush + fence */
743 ndw = 64 + (10 * num_loops); 743 ndw = 64 + (10 * num_loops);
@@ -746,12 +746,12 @@ int r100_copy_blit(struct radeon_device *rdev,
746 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); 746 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
747 return -EINVAL; 747 return -EINVAL;
748 } 748 }
749 while (num_pages > 0) { 749 while (num_gpu_pages > 0) {
750 cur_pages = num_pages; 750 cur_pages = num_gpu_pages;
751 if (cur_pages > 8191) { 751 if (cur_pages > 8191) {
752 cur_pages = 8191; 752 cur_pages = 8191;
753 } 753 }
754 num_pages -= cur_pages; 754 num_gpu_pages -= cur_pages;
755 755
756 /* pages are in Y direction - height 756 /* pages are in Y direction - height
757 page width in X direction - width */ 757 page width in X direction - width */
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
index f24058300413..a1f3ba063c2d 100644
--- a/drivers/gpu/drm/radeon/r200.c
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -84,7 +84,7 @@ static int r200_get_vtx_size_0(uint32_t vtx_fmt_0)
84int r200_copy_dma(struct radeon_device *rdev, 84int r200_copy_dma(struct radeon_device *rdev,
85 uint64_t src_offset, 85 uint64_t src_offset,
86 uint64_t dst_offset, 86 uint64_t dst_offset,
87 unsigned num_pages, 87 unsigned num_gpu_pages,
88 struct radeon_fence *fence) 88 struct radeon_fence *fence)
89{ 89{
90 uint32_t size; 90 uint32_t size;
@@ -93,7 +93,7 @@ int r200_copy_dma(struct radeon_device *rdev,
93 int r = 0; 93 int r = 0;
94 94
95 /* radeon pitch is /64 */ 95 /* radeon pitch is /64 */
96 size = num_pages << PAGE_SHIFT; 96 size = num_gpu_pages << RADEON_GPU_PAGE_SHIFT;
97 num_loops = DIV_ROUND_UP(size, 0x1FFFFF); 97 num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
98 r = radeon_ring_lock(rdev, num_loops * 4 + 64); 98 r = radeon_ring_lock(rdev, num_loops * 4 + 64);
99 if (r) { 99 if (r) {
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index c68427612e3b..720dd99163f8 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2353,21 +2353,23 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
2353} 2353}
2354 2354
2355int r600_copy_blit(struct radeon_device *rdev, 2355int r600_copy_blit(struct radeon_device *rdev,
2356 uint64_t src_offset, uint64_t dst_offset, 2356 uint64_t src_offset,
2357 unsigned num_pages, struct radeon_fence *fence) 2357 uint64_t dst_offset,
2358 unsigned num_gpu_pages,
2359 struct radeon_fence *fence)
2358{ 2360{
2359 int r; 2361 int r;
2360 2362
2361 mutex_lock(&rdev->r600_blit.mutex); 2363 mutex_lock(&rdev->r600_blit.mutex);
2362 rdev->r600_blit.vb_ib = NULL; 2364 rdev->r600_blit.vb_ib = NULL;
2363 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE); 2365 r = r600_blit_prepare_copy(rdev, num_gpu_pages * RADEON_GPU_PAGE_SIZE);
2364 if (r) { 2366 if (r) {
2365 if (rdev->r600_blit.vb_ib) 2367 if (rdev->r600_blit.vb_ib)
2366 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); 2368 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2367 mutex_unlock(&rdev->r600_blit.mutex); 2369 mutex_unlock(&rdev->r600_blit.mutex);
2368 return r; 2370 return r;
2369 } 2371 }
2370 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE); 2372 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages * RADEON_GPU_PAGE_SIZE);
2371 r600_blit_done_copy(rdev, fence); 2373 r600_blit_done_copy(rdev, fence);
2372 mutex_unlock(&rdev->r600_blit.mutex); 2374 mutex_unlock(&rdev->r600_blit.mutex);
2373 return 0; 2375 return 0;
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 32807baf55e2..c1e056b35b29 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -322,6 +322,7 @@ union radeon_gart_table {
322 322
323#define RADEON_GPU_PAGE_SIZE 4096 323#define RADEON_GPU_PAGE_SIZE 4096
324#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 324#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
325#define RADEON_GPU_PAGE_SHIFT 12
325 326
326struct radeon_gart { 327struct radeon_gart {
327 dma_addr_t table_addr; 328 dma_addr_t table_addr;
@@ -914,17 +915,17 @@ struct radeon_asic {
914 int (*copy_blit)(struct radeon_device *rdev, 915 int (*copy_blit)(struct radeon_device *rdev,
915 uint64_t src_offset, 916 uint64_t src_offset,
916 uint64_t dst_offset, 917 uint64_t dst_offset,
917 unsigned num_pages, 918 unsigned num_gpu_pages,
918 struct radeon_fence *fence); 919 struct radeon_fence *fence);
919 int (*copy_dma)(struct radeon_device *rdev, 920 int (*copy_dma)(struct radeon_device *rdev,
920 uint64_t src_offset, 921 uint64_t src_offset,
921 uint64_t dst_offset, 922 uint64_t dst_offset,
922 unsigned num_pages, 923 unsigned num_gpu_pages,
923 struct radeon_fence *fence); 924 struct radeon_fence *fence);
924 int (*copy)(struct radeon_device *rdev, 925 int (*copy)(struct radeon_device *rdev,
925 uint64_t src_offset, 926 uint64_t src_offset,
926 uint64_t dst_offset, 927 uint64_t dst_offset,
927 unsigned num_pages, 928 unsigned num_gpu_pages,
928 struct radeon_fence *fence); 929 struct radeon_fence *fence);
929 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 930 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
930 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 931 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 3d7a0d7c6a9a..3dedaa07aac1 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -75,7 +75,7 @@ uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
75int r100_copy_blit(struct radeon_device *rdev, 75int r100_copy_blit(struct radeon_device *rdev,
76 uint64_t src_offset, 76 uint64_t src_offset,
77 uint64_t dst_offset, 77 uint64_t dst_offset,
78 unsigned num_pages, 78 unsigned num_gpu_pages,
79 struct radeon_fence *fence); 79 struct radeon_fence *fence);
80int r100_set_surface_reg(struct radeon_device *rdev, int reg, 80int r100_set_surface_reg(struct radeon_device *rdev, int reg,
81 uint32_t tiling_flags, uint32_t pitch, 81 uint32_t tiling_flags, uint32_t pitch,
@@ -143,7 +143,7 @@ extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
143extern int r200_copy_dma(struct radeon_device *rdev, 143extern int r200_copy_dma(struct radeon_device *rdev,
144 uint64_t src_offset, 144 uint64_t src_offset,
145 uint64_t dst_offset, 145 uint64_t dst_offset,
146 unsigned num_pages, 146 unsigned num_gpu_pages,
147 struct radeon_fence *fence); 147 struct radeon_fence *fence);
148void r200_set_safe_registers(struct radeon_device *rdev); 148void r200_set_safe_registers(struct radeon_device *rdev);
149 149
@@ -311,7 +311,7 @@ void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
311int r600_ring_test(struct radeon_device *rdev); 311int r600_ring_test(struct radeon_device *rdev);
312int r600_copy_blit(struct radeon_device *rdev, 312int r600_copy_blit(struct radeon_device *rdev,
313 uint64_t src_offset, uint64_t dst_offset, 313 uint64_t src_offset, uint64_t dst_offset,
314 unsigned num_pages, struct radeon_fence *fence); 314 unsigned num_gpu_pages, struct radeon_fence *fence);
315void r600_hpd_init(struct radeon_device *rdev); 315void r600_hpd_init(struct radeon_device *rdev);
316void r600_hpd_fini(struct radeon_device *rdev); 316void r600_hpd_fini(struct radeon_device *rdev);
317bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 317bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
@@ -403,7 +403,7 @@ void evergreen_bandwidth_update(struct radeon_device *rdev);
403void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 403void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
404int evergreen_copy_blit(struct radeon_device *rdev, 404int evergreen_copy_blit(struct radeon_device *rdev,
405 uint64_t src_offset, uint64_t dst_offset, 405 uint64_t src_offset, uint64_t dst_offset,
406 unsigned num_pages, struct radeon_fence *fence); 406 unsigned num_gpu_pages, struct radeon_fence *fence);
407void evergreen_hpd_init(struct radeon_device *rdev); 407void evergreen_hpd_init(struct radeon_device *rdev);
408void evergreen_hpd_fini(struct radeon_device *rdev); 408void evergreen_hpd_fini(struct radeon_device *rdev);
409bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 409bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 9b86fb0e4122..0b5468bfaf54 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -277,7 +277,12 @@ static int radeon_move_blit(struct ttm_buffer_object *bo,
277 DRM_ERROR("Trying to move memory with CP turned off.\n"); 277 DRM_ERROR("Trying to move memory with CP turned off.\n");
278 return -EINVAL; 278 return -EINVAL;
279 } 279 }
280 r = radeon_copy(rdev, old_start, new_start, new_mem->num_pages, fence); 280
281 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
282
283 r = radeon_copy(rdev, old_start, new_start,
284 new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */
285 fence);
281 /* FIXME: handle copy error */ 286 /* FIXME: handle copy error */
282 r = ttm_bo_move_accel_cleanup(bo, (void *)fence, NULL, 287 r = ttm_bo_move_accel_cleanup(bo, (void *)fence, NULL,
283 evict, no_wait_reserve, no_wait_gpu, new_mem); 288 evict, no_wait_reserve, no_wait_gpu, new_mem);