drm/i915: Fix LVDS panel fitting on Arrandale

Arrandale has new window based method for panel fitting.
This one enables full screen aspect scaling on LVDS. It fixes
standard mode display failure on LVDS for Arrandale.

Cc: Stable Team <stable@kernel.org>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

3 files changed, 24 insertions, 3 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f7c2de8fdf09..6345bf20db03 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2000,6 +2000,8 @@
 #define  PF_ENABLE              (1<<31)
 #define PFA_WIN_SZ              0x68074
 #define PFB_WIN_SZ              0x68874
+#define PFA_WIN_POS             0x68070
+#define PFB_WIN_POS             0x68870
 
 /* legacy palette */
 #define LGC_PALETTE_A           0x4a000
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d2f3692be8eb..42cd68da74ab 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1391,6 +1391,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
+        int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
@@ -1442,6 +1443,19 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
                         }
                 }
 
+                /* Enable panel fitting for LVDS */
+                if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
+                        temp = I915_READ(pf_ctl_reg);
+                        I915_WRITE(pf_ctl_reg, temp | PF_ENABLE);
+
+                        /* currently full aspect */
+                        I915_WRITE(pf_win_pos, 0);
+
+                        I915_WRITE(pf_win_size,
+                                   (dev_priv->panel_fixed_mode->hdisplay << 16) |
+                                   (dev_priv->panel_fixed_mode->vdisplay));
+                }
+
                 /* Enable CPU pipe */
                 temp = I915_READ(pipeconf_reg);
                 if ((temp & PIPEACONF_ENABLE) == 0) {
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index c4799bd7eaad..4c55596649f9 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -296,6 +296,10 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
                 goto out;
         }
 
+        /* full screen scale for now */
+        if (IS_IGDNG(dev))
+                goto out;
+
         /* 965+ wants fuzzy fitting */
         if (IS_I965G(dev))
                 pfit_control |= (intel_crtc->pipe << PFIT_PIPE_SHIFT) |
@@ -323,8 +327,10 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
          * to register description and PRM.
          * Change the value here to see the borders for debugging
          */
-        I915_WRITE(BCLRPAT_A, 0);
-        I915_WRITE(BCLRPAT_B, 0);
+        if (!IS_IGDNG(dev)) {
+                I915_WRITE(BCLRPAT_A, 0);
+                I915_WRITE(BCLRPAT_B, 0);
+        }
 
         switch (lvds_priv->fitting_mode) {
         case DRM_MODE_SCALE_CENTER:
@@ -573,7 +579,6 @@ static void intel_lvds_mode_set(struct drm_encoder *encoder,
          * settings.
          */
 
-        /* No panel fitting yet, fixme */
         if (IS_IGDNG(dev))
                 return;