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authorDave Airlie <airlied@redhat.com>2010-08-01 20:05:18 -0400
committerDave Airlie <airlied@redhat.com>2010-08-01 20:05:24 -0400
commitd656ae53f64cb0f01dac8a02c4d31453d64ef97c (patch)
treecf641d4e5828b8f7c430b42657237c5daf9571fd /drivers/gpu
parent167ffc44caaee68ea60dadf6931a4d195a4ed1f0 (diff)
parentb37fa16e78d6f9790462b3181602a26b5af36260 (diff)
Merge tag 'v2.6.35-rc6' into drm-radeon-next
Need this to avoid conflicts with future radeon fixes
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c13
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h64
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.c33
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fbcon.c3
-rw-r--r--drivers/gpu/drm/radeon/evergreen_cs.c2
-rw-r--r--drivers/gpu/drm/radeon/r100.c3
-rw-r--r--drivers/gpu/drm/radeon/r300.c3
-rw-r--r--drivers/gpu/drm/radeon/r520.c1
-rw-r--r--drivers/gpu/drm/radeon/r600.c1
-rw-r--r--drivers/gpu/drm/radeon/r600_blit.c5
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c20
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c8
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c23
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c8
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_encoders.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_tv.c4
-rw-r--r--drivers/gpu/drm/radeon/rs400.c5
-rw-r--r--drivers/gpu/drm/radeon/rs600.c1
-rw-r--r--drivers/gpu/drm/radeon/rs690.c1
-rw-r--r--drivers/gpu/drm/radeon/rv515.c1
-rw-r--r--drivers/gpu/drm/ttm/ttm_page_alloc.c6
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_kms.c1
25 files changed, 155 insertions, 59 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 75061b305b8c..15d2d93aaca9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2241,6 +2241,7 @@ i915_gem_object_get_pages(struct drm_gem_object *obj,
2241 page = read_cache_page_gfp(mapping, i, 2241 page = read_cache_page_gfp(mapping, i,
2242 GFP_HIGHUSER | 2242 GFP_HIGHUSER |
2243 __GFP_COLD | 2243 __GFP_COLD |
2244 __GFP_RECLAIMABLE |
2244 gfpmask); 2245 gfpmask);
2245 if (IS_ERR(page)) 2246 if (IS_ERR(page))
2246 goto err_pages; 2247 goto err_pages;
@@ -4739,6 +4740,16 @@ i915_gem_load(struct drm_device *dev)
4739 list_add(&dev_priv->mm.shrink_list, &shrink_list); 4740 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4740 spin_unlock(&shrink_list_lock); 4741 spin_unlock(&shrink_list_lock);
4741 4742
4743 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4744 if (IS_GEN3(dev)) {
4745 u32 tmp = I915_READ(MI_ARB_STATE);
4746 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4747 /* arb state is a masked write, so set bit + bit in mask */
4748 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4749 I915_WRITE(MI_ARB_STATE, tmp);
4750 }
4751 }
4752
4742 /* Old X drivers will take 0-2 for front, back, depth buffers */ 4753 /* Old X drivers will take 0-2 for front, back, depth buffers */
4743 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 4754 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4744 dev_priv->fence_reg_start = 3; 4755 dev_priv->fence_reg_start = 3;
@@ -4975,7 +4986,7 @@ i915_gpu_is_active(struct drm_device *dev)
4975} 4986}
4976 4987
4977static int 4988static int
4978i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask) 4989i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
4979{ 4990{
4980 drm_i915_private_t *dev_priv, *next_dev; 4991 drm_i915_private_t *dev_priv, *next_dev;
4981 struct drm_i915_gem_object *obj_priv, *next_obj; 4992 struct drm_i915_gem_object *obj_priv, *next_obj;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 150400f40534..6d9b0288272a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -359,6 +359,70 @@
359#define LM_BURST_LENGTH 0x00000700 359#define LM_BURST_LENGTH 0x00000700
360#define LM_FIFO_WATERMARK 0x0000001F 360#define LM_FIFO_WATERMARK 0x0000001F
361#define MI_ARB_STATE 0x020e4 /* 915+ only */ 361#define MI_ARB_STATE 0x020e4 /* 915+ only */
362#define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */
363
364/* Make render/texture TLB fetches lower priorty than associated data
365 * fetches. This is not turned on by default
366 */
367#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
368
369/* Isoch request wait on GTT enable (Display A/B/C streams).
370 * Make isoch requests stall on the TLB update. May cause
371 * display underruns (test mode only)
372 */
373#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
374
375/* Block grant count for isoch requests when block count is
376 * set to a finite value.
377 */
378#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
379#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
380#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
381#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
382#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
383
384/* Enable render writes to complete in C2/C3/C4 power states.
385 * If this isn't enabled, render writes are prevented in low
386 * power states. That seems bad to me.
387 */
388#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
389
390/* This acknowledges an async flip immediately instead
391 * of waiting for 2TLB fetches.
392 */
393#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
394
395/* Enables non-sequential data reads through arbiter
396 */
397#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
398
399/* Disable FSB snooping of cacheable write cycles from binner/render
400 * command stream
401 */
402#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
403
404/* Arbiter time slice for non-isoch streams */
405#define MI_ARB_TIME_SLICE_MASK (7 << 5)
406#define MI_ARB_TIME_SLICE_1 (0 << 5)
407#define MI_ARB_TIME_SLICE_2 (1 << 5)
408#define MI_ARB_TIME_SLICE_4 (2 << 5)
409#define MI_ARB_TIME_SLICE_6 (3 << 5)
410#define MI_ARB_TIME_SLICE_8 (4 << 5)
411#define MI_ARB_TIME_SLICE_10 (5 << 5)
412#define MI_ARB_TIME_SLICE_14 (6 << 5)
413#define MI_ARB_TIME_SLICE_16 (7 << 5)
414
415/* Low priority grace period page size */
416#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
417#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
418
419/* Disable display A/B trickle feed */
420#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
421
422/* Set display plane priority */
423#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
424#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
425
362#define CACHE_MODE_0 0x02120 /* 915+ only */ 426#define CACHE_MODE_0 0x02120 /* 915+ only */
363#define CM0_MASK_SHIFT 16 427#define CM0_MASK_SHIFT 16
364#define CM0_IZ_OPT_DISABLE (1<<6) 428#define CM0_IZ_OPT_DISABLE (1<<6)
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index fc924b649195..e492919faf44 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -203,36 +203,26 @@ struct methods {
203 const bool rw; 203 const bool rw;
204}; 204};
205 205
206static struct methods nv04_methods[] = { 206static struct methods shadow_methods[] = {
207 { "PROM", load_vbios_prom, false },
208 { "PRAMIN", load_vbios_pramin, true },
209 { "PCIROM", load_vbios_pci, true },
210};
211
212static struct methods nv50_methods[] = {
213 { "ACPI", load_vbios_acpi, true },
214 { "PRAMIN", load_vbios_pramin, true }, 207 { "PRAMIN", load_vbios_pramin, true },
215 { "PROM", load_vbios_prom, false }, 208 { "PROM", load_vbios_prom, false },
216 { "PCIROM", load_vbios_pci, true }, 209 { "PCIROM", load_vbios_pci, true },
210 { "ACPI", load_vbios_acpi, true },
217}; 211};
218 212
219#define METHODCNT 3
220
221static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data) 213static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
222{ 214{
223 struct drm_nouveau_private *dev_priv = dev->dev_private; 215 const int nr_methods = ARRAY_SIZE(shadow_methods);
224 struct methods *methods; 216 struct methods *methods = shadow_methods;
225 int i;
226 int testscore = 3; 217 int testscore = 3;
227 int scores[METHODCNT]; 218 int scores[nr_methods], i;
228 219
229 if (nouveau_vbios) { 220 if (nouveau_vbios) {
230 methods = nv04_methods; 221 for (i = 0; i < nr_methods; i++)
231 for (i = 0; i < METHODCNT; i++)
232 if (!strcasecmp(nouveau_vbios, methods[i].desc)) 222 if (!strcasecmp(nouveau_vbios, methods[i].desc))
233 break; 223 break;
234 224
235 if (i < METHODCNT) { 225 if (i < nr_methods) {
236 NV_INFO(dev, "Attempting to use BIOS image from %s\n", 226 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
237 methods[i].desc); 227 methods[i].desc);
238 228
@@ -244,12 +234,7 @@ static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
244 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios); 234 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
245 } 235 }
246 236
247 if (dev_priv->card_type < NV_50) 237 for (i = 0; i < nr_methods; i++) {
248 methods = nv04_methods;
249 else
250 methods = nv50_methods;
251
252 for (i = 0; i < METHODCNT; i++) {
253 NV_TRACE(dev, "Attempting to load BIOS image from %s\n", 238 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
254 methods[i].desc); 239 methods[i].desc);
255 data[0] = data[1] = 0; /* avoid reuse of previous image */ 240 data[0] = data[1] = 0; /* avoid reuse of previous image */
@@ -260,7 +245,7 @@ static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
260 } 245 }
261 246
262 while (--testscore > 0) { 247 while (--testscore > 0) {
263 for (i = 0; i < METHODCNT; i++) { 248 for (i = 0; i < nr_methods; i++) {
264 if (scores[i] == testscore) { 249 if (scores[i] == testscore) {
265 NV_TRACE(dev, "Using BIOS image from %s\n", 250 NV_TRACE(dev, "Using BIOS image from %s\n",
266 methods[i].desc); 251 methods[i].desc);
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index c9a4a0d2a115..257ea130ae13 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -387,7 +387,8 @@ int nouveau_fbcon_init(struct drm_device *dev)
387 dev_priv->nfbdev = nfbdev; 387 dev_priv->nfbdev = nfbdev;
388 nfbdev->helper.funcs = &nouveau_fbcon_helper_funcs; 388 nfbdev->helper.funcs = &nouveau_fbcon_helper_funcs;
389 389
390 ret = drm_fb_helper_init(dev, &nfbdev->helper, 2, 4); 390 ret = drm_fb_helper_init(dev, &nfbdev->helper,
391 nv_two_heads(dev) ? 2 : 1, 4);
391 if (ret) { 392 if (ret) {
392 kfree(nfbdev); 393 kfree(nfbdev);
393 return ret; 394 return ret;
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 010963d4570f..345a75a03c96 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -333,7 +333,6 @@ static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
333 header = radeon_get_ib_value(p, h_idx); 333 header = radeon_get_ib_value(p, h_idx);
334 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); 334 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
335 reg = CP_PACKET0_GET_REG(header); 335 reg = CP_PACKET0_GET_REG(header);
336 mutex_lock(&p->rdev->ddev->mode_config.mutex);
337 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 336 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
338 if (!obj) { 337 if (!obj) {
339 DRM_ERROR("cannot find crtc %d\n", crtc_id); 338 DRM_ERROR("cannot find crtc %d\n", crtc_id);
@@ -368,7 +367,6 @@ static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
368 } 367 }
369 } 368 }
370out: 369out:
371 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
372 return r; 370 return r;
373} 371}
374 372
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 5d14732dc284..e115583f84fb 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1230,7 +1230,6 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1230 header = radeon_get_ib_value(p, h_idx); 1230 header = radeon_get_ib_value(p, h_idx);
1231 crtc_id = radeon_get_ib_value(p, h_idx + 5); 1231 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1232 reg = CP_PACKET0_GET_REG(header); 1232 reg = CP_PACKET0_GET_REG(header);
1233 mutex_lock(&p->rdev->ddev->mode_config.mutex);
1234 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 1233 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1235 if (!obj) { 1234 if (!obj) {
1236 DRM_ERROR("cannot find crtc %d\n", crtc_id); 1235 DRM_ERROR("cannot find crtc %d\n", crtc_id);
@@ -1264,7 +1263,6 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1264 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 1263 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1265 } 1264 }
1266out: 1265out:
1267 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1268 return r; 1266 return r;
1269} 1267}
1270 1268
@@ -2354,6 +2352,7 @@ void r100_mc_init(struct radeon_device *rdev)
2354 if (rdev->flags & RADEON_IS_IGP) 2352 if (rdev->flags & RADEON_IS_IGP)
2355 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 2353 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2356 radeon_vram_location(rdev, &rdev->mc, base); 2354 radeon_vram_location(rdev, &rdev->mc, base);
2355 rdev->mc.gtt_base_align = 0;
2357 if (!(rdev->flags & RADEON_IS_AGP)) 2356 if (!(rdev->flags & RADEON_IS_AGP))
2358 radeon_gtt_location(rdev, &rdev->mc); 2357 radeon_gtt_location(rdev, &rdev->mc);
2359 radeon_update_bandwidth_info(rdev); 2358 radeon_update_bandwidth_info(rdev);
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 3c34da0c899a..58eab5d47305 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -481,6 +481,7 @@ void r300_mc_init(struct radeon_device *rdev)
481 if (rdev->flags & RADEON_IS_IGP) 481 if (rdev->flags & RADEON_IS_IGP)
482 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 482 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
483 radeon_vram_location(rdev, &rdev->mc, base); 483 radeon_vram_location(rdev, &rdev->mc, base);
484 rdev->mc.gtt_base_align = 0;
484 if (!(rdev->flags & RADEON_IS_AGP)) 485 if (!(rdev->flags & RADEON_IS_AGP))
485 radeon_gtt_location(rdev, &rdev->mc); 486 radeon_gtt_location(rdev, &rdev->mc);
486 radeon_update_bandwidth_info(rdev); 487 radeon_update_bandwidth_info(rdev);
@@ -1176,6 +1177,8 @@ int r300_cs_parse(struct radeon_cs_parser *p)
1176 int r; 1177 int r;
1177 1178
1178 track = kzalloc(sizeof(*track), GFP_KERNEL); 1179 track = kzalloc(sizeof(*track), GFP_KERNEL);
1180 if (track == NULL)
1181 return -ENOMEM;
1179 r100_cs_track_clear(p->rdev, track); 1182 r100_cs_track_clear(p->rdev, track);
1180 p->track = track; 1183 p->track = track;
1181 do { 1184 do {
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index 213e2e0027a3..1458dee902dd 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -125,6 +125,7 @@ void r520_mc_init(struct radeon_device *rdev)
125 r520_vram_get_type(rdev); 125 r520_vram_get_type(rdev);
126 r100_vram_init_sizes(rdev); 126 r100_vram_init_sizes(rdev);
127 radeon_vram_location(rdev, &rdev->mc, 0); 127 radeon_vram_location(rdev, &rdev->mc, 0);
128 rdev->mc.gtt_base_align = 0;
128 if (!(rdev->flags & RADEON_IS_AGP)) 129 if (!(rdev->flags & RADEON_IS_AGP))
129 radeon_gtt_location(rdev, &rdev->mc); 130 radeon_gtt_location(rdev, &rdev->mc);
130 radeon_update_bandwidth_info(rdev); 131 radeon_update_bandwidth_info(rdev);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index aa36ef69ba61..e1e59e1b318d 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1194,6 +1194,7 @@ void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1194 if (rdev->flags & RADEON_IS_IGP) 1194 if (rdev->flags & RADEON_IS_IGP)
1195 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24; 1195 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
1196 radeon_vram_location(rdev, &rdev->mc, base); 1196 radeon_vram_location(rdev, &rdev->mc, base);
1197 rdev->mc.gtt_base_align = 0;
1197 radeon_gtt_location(rdev, mc); 1198 radeon_gtt_location(rdev, mc);
1198 } 1199 }
1199} 1200}
diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c
index f4fb88ece2bb..ca5c29f70779 100644
--- a/drivers/gpu/drm/radeon/r600_blit.c
+++ b/drivers/gpu/drm/radeon/r600_blit.c
@@ -538,9 +538,12 @@ int
538r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv) 538r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv)
539{ 539{
540 drm_radeon_private_t *dev_priv = dev->dev_private; 540 drm_radeon_private_t *dev_priv = dev->dev_private;
541 int ret;
541 DRM_DEBUG("\n"); 542 DRM_DEBUG("\n");
542 543
543 r600_nomm_get_vb(dev); 544 ret = r600_nomm_get_vb(dev);
545 if (ret)
546 return ret;
544 547
545 dev_priv->blit_vb->file_priv = file_priv; 548 dev_priv->blit_vb->file_priv = file_priv;
546 549
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 39bac5c3bb2b..c3ea212e0c3c 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -636,7 +636,7 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
636 header = radeon_get_ib_value(p, h_idx); 636 header = radeon_get_ib_value(p, h_idx);
637 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); 637 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
638 reg = CP_PACKET0_GET_REG(header); 638 reg = CP_PACKET0_GET_REG(header);
639 mutex_lock(&p->rdev->ddev->mode_config.mutex); 639
640 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 640 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
641 if (!obj) { 641 if (!obj) {
642 DRM_ERROR("cannot find crtc %d\n", crtc_id); 642 DRM_ERROR("cannot find crtc %d\n", crtc_id);
@@ -671,7 +671,6 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
671 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2; 671 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
672 } 672 }
673out: 673out:
674 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
675 return r; 674 return r;
676} 675}
677 676
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 966ba0751feb..c84f9a311550 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -354,6 +354,7 @@ struct radeon_mc {
354 int vram_mtrr; 354 int vram_mtrr;
355 bool vram_is_ddr; 355 bool vram_is_ddr;
356 bool igp_sideport_enabled; 356 bool igp_sideport_enabled;
357 u64 gtt_base_align;
357}; 358};
358 359
359bool radeon_combios_sideport_present(struct radeon_device *rdev); 360bool radeon_combios_sideport_present(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 5dd86b95b992..0a97aeb083dd 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -280,6 +280,15 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
280 } 280 }
281 } 281 }
282 282
283 /* ASUS HD 3600 board lists the DVI port as HDMI */
284 if ((dev->pdev->device == 0x9598) &&
285 (dev->pdev->subsystem_vendor == 0x1043) &&
286 (dev->pdev->subsystem_device == 0x01e4)) {
287 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
288 *connector_type = DRM_MODE_CONNECTOR_DVII;
289 }
290 }
291
283 /* ASUS HD 3450 board lists the DVI port as HDMI */ 292 /* ASUS HD 3450 board lists the DVI port as HDMI */
284 if ((dev->pdev->device == 0x95C5) && 293 if ((dev->pdev->device == 0x95C5) &&
285 (dev->pdev->subsystem_vendor == 0x1043) && 294 (dev->pdev->subsystem_vendor == 0x1043) &&
@@ -1029,8 +1038,15 @@ bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1029 data_offset); 1038 data_offset);
1030 switch (crev) { 1039 switch (crev) {
1031 case 1: 1040 case 1:
1032 if (igp_info->info.ucMemoryType & 0xf0) 1041 /* AMD IGPS */
1033 return true; 1042 if ((rdev->family == CHIP_RS690) ||
1043 (rdev->family == CHIP_RS740)) {
1044 if (igp_info->info.ulBootUpMemoryClock)
1045 return true;
1046 } else {
1047 if (igp_info->info.ucMemoryType & 0xf0)
1048 return true;
1049 }
1034 break; 1050 break;
1035 case 2: 1051 case 2:
1036 if (igp_info->info_2.ucMemoryType & 0x0f) 1052 if (igp_info->info_2.ucMemoryType & 0x0f)
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 3426dd22aa08..5e45cb27eb98 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -3047,6 +3047,14 @@ void radeon_combios_asic_init(struct drm_device *dev)
3047 rdev->pdev->subsystem_device == 0x308b) 3047 rdev->pdev->subsystem_device == 0x308b)
3048 return; 3048 return;
3049 3049
3050 /* quirk for rs4xx HP dv5000 laptop to make it resume
3051 * - it hangs on resume inside the dynclk 1 table.
3052 */
3053 if (rdev->family == CHIP_RS480 &&
3054 rdev->pdev->subsystem_vendor == 0x103c &&
3055 rdev->pdev->subsystem_device == 0x30a4)
3056 return;
3057
3050 /* DYN CLK 1 */ 3058 /* DYN CLK 1 */
3051 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 3059 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3052 if (table) 3060 if (table)
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index f58f8bd8f77b..adccbc2c202c 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -771,14 +771,14 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
771 } else 771 } else
772 ret = connector_status_connected; 772 ret = connector_status_connected;
773 773
774 /* multiple connectors on the same encoder with the same ddc line 774 /* This gets complicated. We have boards with VGA + HDMI with a
775 * This tends to be HDMI and DVI on the same encoder with the 775 * shared DDC line and we have boards with DVI-D + HDMI with a shared
776 * same ddc line. If the edid says HDMI, consider the HDMI port 776 * DDC line. The latter is more complex because with DVI<->HDMI adapters
777 * connected and the DVI port disconnected. If the edid doesn't 777 * you don't really know what's connected to which port as both are digital.
778 * say HDMI, vice versa.
779 */ 778 */
780 if (radeon_connector->shared_ddc && (ret == connector_status_connected)) { 779 if (radeon_connector->shared_ddc && (ret == connector_status_connected)) {
781 struct drm_device *dev = connector->dev; 780 struct drm_device *dev = connector->dev;
781 struct radeon_device *rdev = dev->dev_private;
782 struct drm_connector *list_connector; 782 struct drm_connector *list_connector;
783 struct radeon_connector *list_radeon_connector; 783 struct radeon_connector *list_radeon_connector;
784 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) { 784 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
@@ -788,15 +788,10 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
788 if (list_radeon_connector->shared_ddc && 788 if (list_radeon_connector->shared_ddc &&
789 (list_radeon_connector->ddc_bus->rec.i2c_id == 789 (list_radeon_connector->ddc_bus->rec.i2c_id ==
790 radeon_connector->ddc_bus->rec.i2c_id)) { 790 radeon_connector->ddc_bus->rec.i2c_id)) {
791 if (drm_detect_hdmi_monitor(radeon_connector->edid)) { 791 /* cases where both connectors are digital */
792 if (connector->connector_type == DRM_MODE_CONNECTOR_DVID) { 792 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
793 kfree(radeon_connector->edid); 793 /* hpd is our only option in this case */
794 radeon_connector->edid = NULL; 794 if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) {
795 ret = connector_status_disconnected;
796 }
797 } else {
798 if ((connector->connector_type == DRM_MODE_CONNECTOR_HDMIA) ||
799 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)) {
800 kfree(radeon_connector->edid); 795 kfree(radeon_connector->edid);
801 radeon_connector->edid = NULL; 796 radeon_connector->edid = NULL;
802 ret = connector_status_disconnected; 797 ret = connector_status_disconnected;
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index fefeb0f958bf..0fea894fc127 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -226,20 +226,20 @@ void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
226{ 226{
227 u64 size_af, size_bf; 227 u64 size_af, size_bf;
228 228
229 size_af = 0xFFFFFFFF - mc->vram_end; 229 size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
230 size_bf = mc->vram_start; 230 size_bf = mc->vram_start & ~mc->gtt_base_align;
231 if (size_bf > size_af) { 231 if (size_bf > size_af) {
232 if (mc->gtt_size > size_bf) { 232 if (mc->gtt_size > size_bf) {
233 dev_warn(rdev->dev, "limiting GTT\n"); 233 dev_warn(rdev->dev, "limiting GTT\n");
234 mc->gtt_size = size_bf; 234 mc->gtt_size = size_bf;
235 } 235 }
236 mc->gtt_start = mc->vram_start - mc->gtt_size; 236 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
237 } else { 237 } else {
238 if (mc->gtt_size > size_af) { 238 if (mc->gtt_size > size_af) {
239 dev_warn(rdev->dev, "limiting GTT\n"); 239 dev_warn(rdev->dev, "limiting GTT\n");
240 mc->gtt_size = size_af; 240 mc->gtt_size = size_af;
241 } 241 }
242 mc->gtt_start = mc->vram_end + 1; 242 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
243 } 243 }
244 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 244 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
245 dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n", 245 dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 9012e6fbadb6..8931c8e78101 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -134,7 +134,8 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
134 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 134 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
135 crtc = (struct drm_crtc *)minfo->crtcs[i]; 135 crtc = (struct drm_crtc *)minfo->crtcs[i];
136 if (crtc && crtc->base.id == value) { 136 if (crtc && crtc->base.id == value) {
137 value = i; 137 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
138 value = radeon_crtc->crtc_id;
138 found = 1; 139 found = 1;
139 break; 140 break;
140 } 141 }
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index bad77f40a9da..5688a0cf6bbe 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -108,6 +108,7 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
108 udelay(panel_pwr_delay * 1000); 108 udelay(panel_pwr_delay * 1000);
109 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 109 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
110 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 110 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
111 udelay(panel_pwr_delay * 1000);
111 break; 112 break;
112 } 113 }
113 114
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_tv.c b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
index f2ed27c8055b..032040397743 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_tv.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
@@ -642,8 +642,8 @@ void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
642 } 642 }
643 flicker_removal = (tmp + 500) / 1000; 643 flicker_removal = (tmp + 500) / 1000;
644 644
645 if (flicker_removal < 2) 645 if (flicker_removal < 3)
646 flicker_removal = 2; 646 flicker_removal = 3;
647 for (i = 0; i < ARRAY_SIZE(SLOPE_limit); ++i) { 647 for (i = 0; i < ARRAY_SIZE(SLOPE_limit); ++i) {
648 if (flicker_removal == SLOPE_limit[i]) 648 if (flicker_removal == SLOPE_limit[i])
649 break; 649 break;
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index c178481101e9..037b93a1b373 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -57,7 +57,9 @@ void rs400_gart_adjust_size(struct radeon_device *rdev)
57 } 57 }
58 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 58 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
59 /* FIXME: RS400 & RS480 seems to have issue with GART size 59 /* FIXME: RS400 & RS480 seems to have issue with GART size
60 * if 4G of system memory (needs more testing) */ 60 * if 4G of system memory (needs more testing)
61 */
62 /* XXX is this still an issue with proper alignment? */
61 rdev->mc.gtt_size = 32 * 1024 * 1024; 63 rdev->mc.gtt_size = 32 * 1024 * 1024;
62 DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n"); 64 DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n");
63 } 65 }
@@ -263,6 +265,7 @@ void rs400_mc_init(struct radeon_device *rdev)
263 r100_vram_init_sizes(rdev); 265 r100_vram_init_sizes(rdev);
264 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 266 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
265 radeon_vram_location(rdev, &rdev->mc, base); 267 radeon_vram_location(rdev, &rdev->mc, base);
268 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
266 radeon_gtt_location(rdev, &rdev->mc); 269 radeon_gtt_location(rdev, &rdev->mc);
267 radeon_update_bandwidth_info(rdev); 270 radeon_update_bandwidth_info(rdev);
268} 271}
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index c5760921d166..85cd911952c1 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -698,6 +698,7 @@ void rs600_mc_init(struct radeon_device *rdev)
698 base = G_000004_MC_FB_START(base) << 16; 698 base = G_000004_MC_FB_START(base) << 16;
699 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 699 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
700 radeon_vram_location(rdev, &rdev->mc, base); 700 radeon_vram_location(rdev, &rdev->mc, base);
701 rdev->mc.gtt_base_align = 0;
701 radeon_gtt_location(rdev, &rdev->mc); 702 radeon_gtt_location(rdev, &rdev->mc);
702 radeon_update_bandwidth_info(rdev); 703 radeon_update_bandwidth_info(rdev);
703} 704}
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 3dde54d57d09..f3a8c9344c64 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -162,6 +162,7 @@ void rs690_mc_init(struct radeon_device *rdev)
162 rs690_pm_info(rdev); 162 rs690_pm_info(rdev);
163 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 163 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
164 radeon_vram_location(rdev, &rdev->mc, base); 164 radeon_vram_location(rdev, &rdev->mc, base);
165 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
165 radeon_gtt_location(rdev, &rdev->mc); 166 radeon_gtt_location(rdev, &rdev->mc);
166 radeon_update_bandwidth_info(rdev); 167 radeon_update_bandwidth_info(rdev);
167} 168}
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 3f04f735deae..b951b8790175 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -195,6 +195,7 @@ void rv515_mc_init(struct radeon_device *rdev)
195 rv515_vram_get_type(rdev); 195 rv515_vram_get_type(rdev);
196 r100_vram_init_sizes(rdev); 196 r100_vram_init_sizes(rdev);
197 radeon_vram_location(rdev, &rdev->mc, 0); 197 radeon_vram_location(rdev, &rdev->mc, 0);
198 rdev->mc.gtt_base_align = 0;
198 if (!(rdev->flags & RADEON_IS_AGP)) 199 if (!(rdev->flags & RADEON_IS_AGP))
199 radeon_gtt_location(rdev, &rdev->mc); 200 radeon_gtt_location(rdev, &rdev->mc);
200 radeon_update_bandwidth_info(rdev); 201 radeon_update_bandwidth_info(rdev);
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index b1d67dc973dc..ca904799f018 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -40,11 +40,13 @@
40#include <linux/slab.h> 40#include <linux/slab.h>
41 41
42#include <asm/atomic.h> 42#include <asm/atomic.h>
43#include <asm/agp.h>
44 43
45#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_bo_driver.h"
46#include "ttm/ttm_page_alloc.h" 45#include "ttm/ttm_page_alloc.h"
47 46
47#ifdef TTM_HAS_AGP
48#include <asm/agp.h>
49#endif
48 50
49#define NUM_PAGES_TO_ALLOC (PAGE_SIZE/sizeof(struct page *)) 51#define NUM_PAGES_TO_ALLOC (PAGE_SIZE/sizeof(struct page *))
50#define SMALL_ALLOCATION 16 52#define SMALL_ALLOCATION 16
@@ -392,7 +394,7 @@ static int ttm_pool_get_num_unused_pages(void)
392/** 394/**
393 * Callback for mm to request pool to reduce number of page held. 395 * Callback for mm to request pool to reduce number of page held.
394 */ 396 */
395static int ttm_pool_mm_shrink(int shrink_pages, gfp_t gfp_mask) 397static int ttm_pool_mm_shrink(struct shrinker *shrink, int shrink_pages, gfp_t gfp_mask)
396{ 398{
397 static atomic_t start_pool = ATOMIC_INIT(0); 399 static atomic_t start_pool = ATOMIC_INIT(0);
398 unsigned i; 400 unsigned i;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index f1d626112415..437ac786277a 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -972,6 +972,7 @@ int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
972 ret = copy_from_user(rects, user_rects, rects_size); 972 ret = copy_from_user(rects, user_rects, rects_size);
973 if (unlikely(ret != 0)) { 973 if (unlikely(ret != 0)) {
974 DRM_ERROR("Failed to get rects.\n"); 974 DRM_ERROR("Failed to get rects.\n");
975 ret = -EFAULT;
975 goto out_free; 976 goto out_free;
976 } 977 }
977 978