diff options
author | Eric Anholt <eric@anholt.net> | 2010-07-26 17:49:07 -0400 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2010-08-03 19:23:58 -0400 |
commit | 7b824ec2e5d7d086264ecae51e30e3c5e00cdecc (patch) | |
tree | f52e8a3f04f5651efa9ec8dc354b9804ce23dc67 /drivers/gpu | |
parent | d1d6ca73ef548748e141747e7260798327d6a2c1 (diff) |
drm/i915: Clear the Ironlake dithering flags when the pipe doesn't want it.
My fine DisplayPort output was getting ST dithering forever after
having had the LVDS enabled at one point.
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ca3b8a8933c6..ae1718549eec 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -3888,6 +3888,11 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, | |||
3888 | udelay(150); | 3888 | udelay(150); |
3889 | } | 3889 | } |
3890 | 3890 | ||
3891 | if (HAS_PCH_SPLIT(dev)) { | ||
3892 | pipeconf &= ~PIPE_ENABLE_DITHER; | ||
3893 | pipeconf &= ~PIPE_DITHER_TYPE_MASK; | ||
3894 | } | ||
3895 | |||
3891 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. | 3896 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
3892 | * This is an exception to the general rule that mode_set doesn't turn | 3897 | * This is an exception to the general rule that mode_set doesn't turn |
3893 | * things on. | 3898 | * things on. |
@@ -3930,16 +3935,13 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, | |||
3930 | if (dev_priv->lvds_dither) { | 3935 | if (dev_priv->lvds_dither) { |
3931 | if (HAS_PCH_SPLIT(dev)) { | 3936 | if (HAS_PCH_SPLIT(dev)) { |
3932 | pipeconf |= PIPE_ENABLE_DITHER; | 3937 | pipeconf |= PIPE_ENABLE_DITHER; |
3933 | pipeconf &= ~PIPE_DITHER_TYPE_MASK; | ||
3934 | pipeconf |= PIPE_DITHER_TYPE_ST01; | 3938 | pipeconf |= PIPE_DITHER_TYPE_ST01; |
3935 | } else | 3939 | } else |
3936 | lvds |= LVDS_ENABLE_DITHER; | 3940 | lvds |= LVDS_ENABLE_DITHER; |
3937 | } else { | 3941 | } else { |
3938 | if (HAS_PCH_SPLIT(dev)) { | 3942 | if (!HAS_PCH_SPLIT(dev)) { |
3939 | pipeconf &= ~PIPE_ENABLE_DITHER; | ||
3940 | pipeconf &= ~PIPE_DITHER_TYPE_MASK; | ||
3941 | } else | ||
3942 | lvds &= ~LVDS_ENABLE_DITHER; | 3943 | lvds &= ~LVDS_ENABLE_DITHER; |
3944 | } | ||
3943 | } | 3945 | } |
3944 | } | 3946 | } |
3945 | I915_WRITE(lvds_reg, lvds); | 3947 | I915_WRITE(lvds_reg, lvds); |