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authorVille Syrjälä <ville.syrjala@linux.intel.com>2013-09-24 14:26:27 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-10-10 06:46:53 -0400
commit889059d8f0eff8d179d98c3fee64a27d7ff6312f (patch)
tree38d111bbf41ca349e4cdb5249138530512ef7208 /drivers/gpu
parentb99ab66301f384766b8e37abe52719c65a7da140 (diff)
drm/i915: Respect p2 divider minimum limit on VLV
VLV2_DPLL_mphy_hsdpll_frequency_table_ww6_rev1p1.xlsm tells us that the minimum p2 divider is 2. Use that limit on the code. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c4658e7c3bb6..89d04612cc29 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -319,7 +319,7 @@ static const intel_limit_t intel_limits_vlv_dac = {
319 .p = { .min = 10, .max = 30 }, 319 .p = { .min = 10, .max = 30 },
320 .p1 = { .min = 2, .max = 3 }, 320 .p1 = { .min = 2, .max = 3 },
321 .p2 = { .dot_limit = 270000, 321 .p2 = { .dot_limit = 270000,
322 .p2_slow = 2, .p2_fast = 20 }, 322 .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
323}; 323};
324 324
325static const intel_limit_t intel_limits_vlv_hdmi = { 325static const intel_limit_t intel_limits_vlv_hdmi = {
@@ -332,7 +332,7 @@ static const intel_limit_t intel_limits_vlv_hdmi = {
332 .p = { .min = 10, .max = 30 }, 332 .p = { .min = 10, .max = 30 },
333 .p1 = { .min = 2, .max = 3 }, 333 .p1 = { .min = 2, .max = 3 },
334 .p2 = { .dot_limit = 270000, 334 .p2 = { .dot_limit = 270000,
335 .p2_slow = 2, .p2_fast = 20 }, 335 .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
336}; 336};
337 337
338static void vlv_clock(int refclk, intel_clock_t *clock) 338static void vlv_clock(int refclk, intel_clock_t *clock)
@@ -689,7 +689,7 @@ vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
689 /* based on hardware requirement, prefer smaller n to precision */ 689 /* based on hardware requirement, prefer smaller n to precision */
690 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 690 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
691 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 691 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
692 for (clock.p2 = limit->p2.p2_fast; clock.p2 > 0; 692 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
693 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 693 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
694 clock.p = clock.p1 * clock.p2; 694 clock.p = clock.p1 * clock.p2;
695 /* based on hardware requirement, prefer bigger m1,m2 values */ 695 /* based on hardware requirement, prefer bigger m1,m2 values */