drm/radeon/cik: Add macrotile mode array query

This is required to properly calculate the tiling parameters
in userspace.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

4 files changed, 15 insertions, 1 deletions

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 08aa58ef8d0a..b43a3a3c9067 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -2427,6 +2427,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                 gb_tile_moden = 0;
                                 break;
                         }
+                        rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
                         WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
                 }
         } else if (num_pipe_configs == 4) {
@@ -2773,6 +2774,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                 gb_tile_moden = 0;
                                 break;
                         }
+                        rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
                         WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
                 }
         } else if (num_pipe_configs == 2) {
@@ -2990,6 +2992,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                 gb_tile_moden = 0;
                                 break;
                         }
+                        rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
                         WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
                 }
         } else
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 4970ac0ebc80..ecf2a3960c07 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1982,6 +1982,7 @@ struct cik_asic {
 
         unsigned tile_config;
         uint32_t tile_mode_array[32];
+        uint32_t macrotile_mode_array[16];
 };
 
 union radeon_asic_config {
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 1aee32213f66..9f5ff28864f6 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -76,9 +76,10 @@
  *   2.32.0 - new info request for rings working
  *   2.33.0 - Add SI tiling mode array query
  *   2.34.0 - Add CIK tiling mode array query
+ *   2.35.0 - Add CIK macrotile mode array query
  */
 #define KMS_DRIVER_MAJOR        2
-#define KMS_DRIVER_MINOR        34
+#define KMS_DRIVER_MINOR        35
 #define KMS_DRIVER_PATCHLEVEL   0
 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
 int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index fa42c81da500..55d0b474bd37 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -449,6 +449,15 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
                         return -EINVAL;
                 }
                 break;
+        case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
+                if (rdev->family >= CHIP_BONAIRE) {
+                        value = rdev->config.cik.macrotile_mode_array;
+                        value_size = sizeof(uint32_t)*16;
+                } else {
+                        DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
+                        return -EINVAL;
+                }
+                break;
         case RADEON_INFO_SI_CP_DMA_COMPUTE:
                 *value = 1;
                 break;