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authorAlex Deucher <alexander.deucher@amd.com>2012-10-08 09:45:46 -0400
committerAlex Deucher <alexander.deucher@amd.com>2012-10-15 13:21:00 -0400
commit23d4f1f246a98dde1dc485e0be9a647126630347 (patch)
treec437e633496807489290e51646cf2325f431333a /drivers/gpu
parent29dbe3bcd2e28e71823febdca989d63d5c27d152 (diff)
drm/radeon: update comments to clarify VM setup (v2)
The actual set up and assignment of VM page tables is done on the fly in radeon_gart.c. v2: update vm size comments Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/ni.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c4
-rw-r--r--drivers/gpu/drm/radeon/si.c7
3 files changed, 12 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 8bcb554ea0c5..83dc0852d5c9 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -770,6 +770,10 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev)
770 WREG32(0x15DC, 0); 770 WREG32(0x15DC, 0);
771 771
772 /* empty context1-7 */ 772 /* empty context1-7 */
773 /* Assign the pt base to something valid for now; the pts used for
774 * the VMs are determined by the application and setup and assigned
775 * on the fly in the vm part of radeon_gart.c
776 */
773 for (i = 1; i < 8; i++) { 777 for (i = 1; i < 8; i++) {
774 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0); 778 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
775 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), 0); 779 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), 0);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 64a42647f08a..bd13ca09eb62 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1018,6 +1018,10 @@ int radeon_device_init(struct radeon_device *rdev,
1018 return r; 1018 return r;
1019 /* initialize vm here */ 1019 /* initialize vm here */
1020 mutex_init(&rdev->vm_manager.lock); 1020 mutex_init(&rdev->vm_manager.lock);
1021 /* Adjust VM size here.
1022 * Currently set to 4GB ((1 << 20) 4k pages).
1023 * Max GPUVM size for cayman and SI is 40 bits.
1024 */
1021 rdev->vm_manager.max_pfn = 1 << 20; 1025 rdev->vm_manager.max_pfn = 1 << 20;
1022 INIT_LIST_HEAD(&rdev->vm_manager.lru_vm); 1026 INIT_LIST_HEAD(&rdev->vm_manager.lru_vm);
1023 1027
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index f79633a036c3..df8dd7701643 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2407,12 +2407,13 @@ static int si_pcie_gart_enable(struct radeon_device *rdev)
2407 WREG32(0x15DC, 0); 2407 WREG32(0x15DC, 0);
2408 2408
2409 /* empty context1-15 */ 2409 /* empty context1-15 */
2410 /* FIXME start with 4G, once using 2 level pt switch to full
2411 * vm size space
2412 */
2413 /* set vm size, must be a multiple of 4 */ 2410 /* set vm size, must be a multiple of 4 */
2414 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 2411 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
2415 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn); 2412 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
2413 /* Assign the pt base to something valid for now; the pts used for
2414 * the VMs are determined by the application and setup and assigned
2415 * on the fly in the vm part of radeon_gart.c
2416 */
2416 for (i = 1; i < 16; i++) { 2417 for (i = 1; i < 16; i++) {
2417 if (i < 8) 2418 if (i < 8)
2418 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), 2419 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),