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authorKeith Packard <keithp@keithp.com>2009-04-07 19:16:42 -0400
committerKeith Packard <keithp@keithp.com>2009-06-18 18:54:07 -0400
commita4fc5ed69817c73e32571ad7837bb707f9890009 (patch)
tree1a54e8ca9917330359118c1709895c80d74c15af /drivers/gpu
parentc31c4ba3437d98efa19710e30d694a1cfdf87aa5 (diff)
drm/i915: Add Display Port support
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/Makefile2
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h12
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c34
-rw-r--r--drivers/gpu/drm/i915/intel_display.c107
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c1098
-rw-r--r--drivers/gpu/drm/i915/intel_dp.h144
-rw-r--r--drivers/gpu/drm/i915/intel_dp_i2c.c272
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h5
8 files changed, 1668 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 51c5a050aa73..30d6b99fb302 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -13,6 +13,8 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \
13 intel_crt.o \ 13 intel_crt.o \
14 intel_lvds.o \ 14 intel_lvds.o \
15 intel_bios.o \ 15 intel_bios.o \
16 intel_dp.o \
17 intel_dp_i2c.o \
16 intel_hdmi.o \ 18 intel_hdmi.o \
17 intel_sdvo.o \ 19 intel_sdvo.o \
18 intel_modes.o \ 20 intel_modes.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7a84f04e8439..bb4c2d387b6c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -306,6 +306,17 @@ typedef struct drm_i915_private {
306 u32 saveCURBPOS; 306 u32 saveCURBPOS;
307 u32 saveCURBBASE; 307 u32 saveCURBBASE;
308 u32 saveCURSIZE; 308 u32 saveCURSIZE;
309 u32 saveDP_B;
310 u32 saveDP_C;
311 u32 saveDP_D;
312 u32 savePIPEA_GMCH_DATA_M;
313 u32 savePIPEB_GMCH_DATA_M;
314 u32 savePIPEA_GMCH_DATA_N;
315 u32 savePIPEB_GMCH_DATA_N;
316 u32 savePIPEA_DP_LINK_M;
317 u32 savePIPEB_DP_LINK_M;
318 u32 savePIPEA_DP_LINK_N;
319 u32 savePIPEB_DP_LINK_N;
309 320
310 struct { 321 struct {
311 struct drm_mm gtt_space; 322 struct drm_mm gtt_space;
@@ -857,6 +868,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
857#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \ 868#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
858 IS_I915GM(dev))) 869 IS_I915GM(dev)))
859#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev)) 870#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
871#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev))
860#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev)) 872#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev))
861 873
862#define PRIMARY_RINGBUFFER_SIZE (128*1024) 874#define PRIMARY_RINGBUFFER_SIZE (128*1024)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index a98e2831ed31..8d8e083d14ab 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -322,6 +322,20 @@ int i915_save_state(struct drm_device *dev)
322 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); 322 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
323 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR); 323 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
324 324
325 /* Display Port state */
326 if (SUPPORTS_INTEGRATED_DP(dev)) {
327 dev_priv->saveDP_B = I915_READ(DP_B);
328 dev_priv->saveDP_C = I915_READ(DP_C);
329 dev_priv->saveDP_D = I915_READ(DP_D);
330 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(PIPEA_GMCH_DATA_M);
331 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(PIPEB_GMCH_DATA_M);
332 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(PIPEA_GMCH_DATA_N);
333 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(PIPEB_GMCH_DATA_N);
334 dev_priv->savePIPEA_DP_LINK_M = I915_READ(PIPEA_DP_LINK_M);
335 dev_priv->savePIPEB_DP_LINK_M = I915_READ(PIPEB_DP_LINK_M);
336 dev_priv->savePIPEA_DP_LINK_N = I915_READ(PIPEA_DP_LINK_N);
337 dev_priv->savePIPEB_DP_LINK_N = I915_READ(PIPEB_DP_LINK_N);
338 }
325 /* FIXME: save TV & SDVO state */ 339 /* FIXME: save TV & SDVO state */
326 340
327 /* FBC state */ 341 /* FBC state */
@@ -404,7 +418,19 @@ int i915_restore_state(struct drm_device *dev)
404 for (i = 0; i < 8; i++) 418 for (i = 0; i < 8; i++)
405 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]); 419 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
406 } 420 }
407 421
422 /* Display port ratios (must be done before clock is set) */
423 if (SUPPORTS_INTEGRATED_DP(dev)) {
424 I915_WRITE(PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
425 I915_WRITE(PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
426 I915_WRITE(PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
427 I915_WRITE(PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
428 I915_WRITE(PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
429 I915_WRITE(PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
430 I915_WRITE(PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
431 I915_WRITE(PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
432 }
433
408 /* Pipe & plane A info */ 434 /* Pipe & plane A info */
409 /* Prime the clock */ 435 /* Prime the clock */
410 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { 436 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
@@ -518,6 +544,12 @@ int i915_restore_state(struct drm_device *dev)
518 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR); 544 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
519 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL); 545 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
520 546
547 /* Display Port state */
548 if (SUPPORTS_INTEGRATED_DP(dev)) {
549 I915_WRITE(DP_B, dev_priv->saveDP_B);
550 I915_WRITE(DP_C, dev_priv->saveDP_C);
551 I915_WRITE(DP_D, dev_priv->saveDP_D);
552 }
521 /* FIXME: restore TV & SDVO state */ 553 /* FIXME: restore TV & SDVO state */
522 554
523 /* FBC info */ 555 /* FBC info */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3e1c78162119..5af55aa0d7a6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -29,6 +29,7 @@
29#include "intel_drv.h" 29#include "intel_drv.h"
30#include "i915_drm.h" 30#include "i915_drm.h"
31#include "i915_drv.h" 31#include "i915_drv.h"
32#include "intel_dp.h"
32 33
33#include "drm_crtc_helper.h" 34#include "drm_crtc_helper.h"
34 35
@@ -135,10 +136,11 @@ struct intel_limit {
135#define INTEL_LIMIT_G4X_HDMI_DAC 5 136#define INTEL_LIMIT_G4X_HDMI_DAC 5
136#define INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS 6 137#define INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS 6
137#define INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS 7 138#define INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS 7
138#define INTEL_LIMIT_IGD_SDVO_DAC 8 139#define INTEL_LIMIT_G4X_DISPLAY_PORT 8
139#define INTEL_LIMIT_IGD_LVDS 9 140#define INTEL_LIMIT_IGD_SDVO_DAC 9
140#define INTEL_LIMIT_IGDNG_SDVO_DAC 10 141#define INTEL_LIMIT_IGD_LVDS 10
141#define INTEL_LIMIT_IGDNG_LVDS 11 142#define INTEL_LIMIT_IGDNG_SDVO_DAC 11
143#define INTEL_LIMIT_IGDNG_LVDS 12
142 144
143/*The parameter is for SDVO on G4x platform*/ 145/*The parameter is for SDVO on G4x platform*/
144#define G4X_DOT_SDVO_MIN 25000 146#define G4X_DOT_SDVO_MIN 25000
@@ -218,6 +220,25 @@ struct intel_limit {
218#define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7 220#define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
219#define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0 221#define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
220 222
223/*The parameter is for DISPLAY PORT on G4x platform*/
224#define G4X_DOT_DISPLAY_PORT_MIN 161670
225#define G4X_DOT_DISPLAY_PORT_MAX 227000
226#define G4X_N_DISPLAY_PORT_MIN 1
227#define G4X_N_DISPLAY_PORT_MAX 2
228#define G4X_M_DISPLAY_PORT_MIN 97
229#define G4X_M_DISPLAY_PORT_MAX 108
230#define G4X_M1_DISPLAY_PORT_MIN 0x10
231#define G4X_M1_DISPLAY_PORT_MAX 0x12
232#define G4X_M2_DISPLAY_PORT_MIN 0x05
233#define G4X_M2_DISPLAY_PORT_MAX 0x06
234#define G4X_P_DISPLAY_PORT_MIN 10
235#define G4X_P_DISPLAY_PORT_MAX 20
236#define G4X_P1_DISPLAY_PORT_MIN 1
237#define G4X_P1_DISPLAY_PORT_MAX 2
238#define G4X_P2_DISPLAY_PORT_SLOW 10
239#define G4X_P2_DISPLAY_PORT_FAST 10
240#define G4X_P2_DISPLAY_PORT_LIMIT 0
241
221/* IGDNG */ 242/* IGDNG */
222/* as we calculate clock using (register_value + 2) for 243/* as we calculate clock using (register_value + 2) for
223 N/M1/M2, so here the range value for them is (actual_value-2). 244 N/M1/M2, so here the range value for them is (actual_value-2).
@@ -256,6 +277,10 @@ static bool
256intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 277intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
257 int target, int refclk, intel_clock_t *best_clock); 278 int target, int refclk, intel_clock_t *best_clock);
258 279
280static bool
281intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
282 int target, int refclk, intel_clock_t *best_clock);
283
259static const intel_limit_t intel_limits[] = { 284static const intel_limit_t intel_limits[] = {
260 { /* INTEL_LIMIT_I8XX_DVO_DAC */ 285 { /* INTEL_LIMIT_I8XX_DVO_DAC */
261 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, 286 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
@@ -389,6 +414,28 @@ static const intel_limit_t intel_limits[] = {
389 }, 414 },
390 .find_pll = intel_g4x_find_best_PLL, 415 .find_pll = intel_g4x_find_best_PLL,
391 }, 416 },
417 { /* INTEL_LIMIT_G4X_DISPLAY_PORT */
418 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
419 .max = G4X_DOT_DISPLAY_PORT_MAX },
420 .vco = { .min = G4X_VCO_MIN,
421 .max = G4X_VCO_MAX},
422 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
423 .max = G4X_N_DISPLAY_PORT_MAX },
424 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
425 .max = G4X_M_DISPLAY_PORT_MAX },
426 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
427 .max = G4X_M1_DISPLAY_PORT_MAX },
428 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
429 .max = G4X_M2_DISPLAY_PORT_MAX },
430 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
431 .max = G4X_P_DISPLAY_PORT_MAX },
432 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
433 .max = G4X_P1_DISPLAY_PORT_MAX},
434 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
435 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
436 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
437 .find_pll = intel_find_pll_g4x_dp,
438 },
392 { /* INTEL_LIMIT_IGD_SDVO */ 439 { /* INTEL_LIMIT_IGD_SDVO */
393 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, 440 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
394 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX }, 441 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
@@ -478,6 +525,8 @@ static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
478 limit = &intel_limits[INTEL_LIMIT_G4X_HDMI_DAC]; 525 limit = &intel_limits[INTEL_LIMIT_G4X_HDMI_DAC];
479 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { 526 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
480 limit = &intel_limits[INTEL_LIMIT_G4X_SDVO]; 527 limit = &intel_limits[INTEL_LIMIT_G4X_SDVO];
528 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
529 limit = &intel_limits[INTEL_LIMIT_G4X_DISPLAY_PORT];
481 } else /* The option is for other outputs */ 530 } else /* The option is for other outputs */
482 limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC]; 531 limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
483 532
@@ -764,6 +813,35 @@ out:
764 return found; 813 return found;
765} 814}
766 815
816/* DisplayPort has only two frequencies, 162MHz and 270MHz */
817static bool
818intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
819 int target, int refclk, intel_clock_t *best_clock)
820{
821 intel_clock_t clock;
822 if (target < 200000) {
823 clock.dot = 161670;
824 clock.p = 20;
825 clock.p1 = 2;
826 clock.p2 = 10;
827 clock.n = 0x01;
828 clock.m = 97;
829 clock.m1 = 0x10;
830 clock.m2 = 0x05;
831 } else {
832 clock.dot = 270000;
833 clock.p = 10;
834 clock.p1 = 1;
835 clock.p2 = 10;
836 clock.n = 0x02;
837 clock.m = 108;
838 clock.m1 = 0x12;
839 clock.m2 = 0x06;
840 }
841 memcpy(best_clock, &clock, sizeof(intel_clock_t));
842 return true;
843}
844
767void 845void
768intel_wait_for_vblank(struct drm_device *dev) 846intel_wait_for_vblank(struct drm_device *dev)
769{ 847{
@@ -1541,7 +1619,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
1541 intel_clock_t clock; 1619 intel_clock_t clock;
1542 u32 dpll = 0, fp = 0, dspcntr, pipeconf; 1620 u32 dpll = 0, fp = 0, dspcntr, pipeconf;
1543 bool ok, is_sdvo = false, is_dvo = false; 1621 bool ok, is_sdvo = false, is_dvo = false;
1544 bool is_crt = false, is_lvds = false, is_tv = false; 1622 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
1545 struct drm_mode_config *mode_config = &dev->mode_config; 1623 struct drm_mode_config *mode_config = &dev->mode_config;
1546 struct drm_connector *connector; 1624 struct drm_connector *connector;
1547 const intel_limit_t *limit; 1625 const intel_limit_t *limit;
@@ -1585,6 +1663,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
1585 case INTEL_OUTPUT_ANALOG: 1663 case INTEL_OUTPUT_ANALOG:
1586 is_crt = true; 1664 is_crt = true;
1587 break; 1665 break;
1666 case INTEL_OUTPUT_DISPLAYPORT:
1667 is_dp = true;
1668 break;
1588 } 1669 }
1589 1670
1590 num_outputs++; 1671 num_outputs++;
@@ -1600,6 +1681,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
1600 } else { 1681 } else {
1601 refclk = 48000; 1682 refclk = 48000;
1602 } 1683 }
1684
1603 1685
1604 /* 1686 /*
1605 * Returns a set of divisors for the desired target clock with the given 1687 * Returns a set of divisors for the desired target clock with the given
@@ -1662,6 +1744,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
1662 else if (IS_IGDNG(dev)) 1744 else if (IS_IGDNG(dev))
1663 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 1745 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
1664 } 1746 }
1747 if (is_dp)
1748 dpll |= DPLL_DVO_HIGH_SPEED;
1665 1749
1666 /* compute bitmask from p1 value */ 1750 /* compute bitmask from p1 value */
1667 if (IS_IGD(dev)) 1751 if (IS_IGD(dev))
@@ -1809,6 +1893,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
1809 I915_WRITE(lvds_reg, lvds); 1893 I915_WRITE(lvds_reg, lvds);
1810 I915_READ(lvds_reg); 1894 I915_READ(lvds_reg);
1811 } 1895 }
1896 if (is_dp)
1897 intel_dp_set_m_n(crtc, mode, adjusted_mode);
1812 1898
1813 I915_WRITE(fp_reg, fp); 1899 I915_WRITE(fp_reg, fp);
1814 I915_WRITE(dpll_reg, dpll); 1900 I915_WRITE(dpll_reg, dpll);
@@ -2475,6 +2561,8 @@ static void intel_setup_outputs(struct drm_device *dev)
2475 found = intel_sdvo_init(dev, SDVOB); 2561 found = intel_sdvo_init(dev, SDVOB);
2476 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) 2562 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
2477 intel_hdmi_init(dev, SDVOB); 2563 intel_hdmi_init(dev, SDVOB);
2564 if (!found && SUPPORTS_INTEGRATED_DP(dev))
2565 intel_dp_init(dev, DP_B);
2478 } 2566 }
2479 2567
2480 /* Before G4X SDVOC doesn't have its own detect register */ 2568 /* Before G4X SDVOC doesn't have its own detect register */
@@ -2487,7 +2575,11 @@ static void intel_setup_outputs(struct drm_device *dev)
2487 found = intel_sdvo_init(dev, SDVOC); 2575 found = intel_sdvo_init(dev, SDVOC);
2488 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) 2576 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
2489 intel_hdmi_init(dev, SDVOC); 2577 intel_hdmi_init(dev, SDVOC);
2578 if (!found && SUPPORTS_INTEGRATED_DP(dev))
2579 intel_dp_init(dev, DP_C);
2490 } 2580 }
2581 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
2582 intel_dp_init(dev, DP_D);
2491 } else 2583 } else
2492 intel_dvo_init(dev); 2584 intel_dvo_init(dev);
2493 2585
@@ -2530,6 +2622,11 @@ static void intel_setup_outputs(struct drm_device *dev)
2530 (1 << 1)); 2622 (1 << 1));
2531 clone_mask = (1 << INTEL_OUTPUT_TVOUT); 2623 clone_mask = (1 << INTEL_OUTPUT_TVOUT);
2532 break; 2624 break;
2625 case INTEL_OUTPUT_DISPLAYPORT:
2626 crtc_mask = ((1 << 0) |
2627 (1 << 1));
2628 clone_mask = (1 << INTEL_OUTPUT_DISPLAYPORT);
2629 break;
2533 } 2630 }
2534 encoder->possible_crtcs = crtc_mask; 2631 encoder->possible_crtcs = crtc_mask;
2535 encoder->possible_clones = intel_connector_clones(dev, clone_mask); 2632 encoder->possible_clones = intel_connector_clones(dev, clone_mask);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
new file mode 100644
index 000000000000..c57cdab4f4a6
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -0,0 +1,1098 @@
1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
29#include "drmP.h"
30#include "drm.h"
31#include "drm_crtc.h"
32#include "drm_crtc_helper.h"
33#include "intel_drv.h"
34#include "i915_drm.h"
35#include "i915_drv.h"
36#include "intel_dp.h"
37
38#define DP_LINK_STATUS_SIZE 6
39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41#define DP_LINK_CONFIGURATION_SIZE 9
42
43struct intel_dp_priv {
44 uint32_t output_reg;
45 uint32_t DP;
46 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
47 uint32_t save_DP;
48 uint8_t save_link_configuration[DP_LINK_CONFIGURATION_SIZE];
49 bool has_audio;
50 uint8_t link_bw;
51 uint8_t lane_count;
52 uint8_t dpcd[4];
53 struct intel_output *intel_output;
54 struct i2c_adapter adapter;
55 struct i2c_algo_dp_aux_data algo;
56};
57
58static void
59intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
60 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
61
62static void
63intel_dp_link_down(struct intel_output *intel_output, uint32_t DP);
64
65static int
66intel_dp_max_lane_count(struct intel_output *intel_output)
67{
68 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
69 int max_lane_count = 4;
70
71 if (dp_priv->dpcd[0] >= 0x11) {
72 max_lane_count = dp_priv->dpcd[2] & 0x1f;
73 switch (max_lane_count) {
74 case 1: case 2: case 4:
75 break;
76 default:
77 max_lane_count = 4;
78 }
79 }
80 return max_lane_count;
81}
82
83static int
84intel_dp_max_link_bw(struct intel_output *intel_output)
85{
86 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
87 int max_link_bw = dp_priv->dpcd[1];
88
89 switch (max_link_bw) {
90 case DP_LINK_BW_1_62:
91 case DP_LINK_BW_2_7:
92 break;
93 default:
94 max_link_bw = DP_LINK_BW_1_62;
95 break;
96 }
97 return max_link_bw;
98}
99
100static int
101intel_dp_link_clock(uint8_t link_bw)
102{
103 if (link_bw == DP_LINK_BW_2_7)
104 return 270000;
105 else
106 return 162000;
107}
108
109/* I think this is a fiction */
110static int
111intel_dp_link_required(int pixel_clock)
112{
113 return pixel_clock * 3;
114}
115
116static int
117intel_dp_mode_valid(struct drm_connector *connector,
118 struct drm_display_mode *mode)
119{
120 struct intel_output *intel_output = to_intel_output(connector);
121 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_output));
122 int max_lanes = intel_dp_max_lane_count(intel_output);
123
124 if (intel_dp_link_required(mode->clock) > max_link_clock * max_lanes)
125 return MODE_CLOCK_HIGH;
126
127 if (mode->clock < 10000)
128 return MODE_CLOCK_LOW;
129
130 return MODE_OK;
131}
132
133static uint32_t
134pack_aux(uint8_t *src, int src_bytes)
135{
136 int i;
137 uint32_t v = 0;
138
139 if (src_bytes > 4)
140 src_bytes = 4;
141 for (i = 0; i < src_bytes; i++)
142 v |= ((uint32_t) src[i]) << ((3-i) * 8);
143 return v;
144}
145
146static void
147unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
148{
149 int i;
150 if (dst_bytes > 4)
151 dst_bytes = 4;
152 for (i = 0; i < dst_bytes; i++)
153 dst[i] = src >> ((3-i) * 8);
154}
155
156static int
157intel_dp_aux_ch(struct intel_output *intel_output,
158 uint8_t *send, int send_bytes,
159 uint8_t *recv, int recv_size)
160{
161 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
162 uint32_t output_reg = dp_priv->output_reg;
163 struct drm_device *dev = intel_output->base.dev;
164 struct drm_i915_private *dev_priv = dev->dev_private;
165 uint32_t ch_ctl = output_reg + 0x10;
166 uint32_t ch_data = ch_ctl + 4;
167 int i;
168 int recv_bytes;
169 uint32_t ctl;
170 uint32_t status;
171
172 /* Load the send data into the aux channel data registers */
173 for (i = 0; i < send_bytes; i += 4) {
174 uint32_t d = pack_aux(send + i, send_bytes - i);;
175
176 I915_WRITE(ch_data + i, d);
177 }
178
179 /* The clock divider is based off the hrawclk,
180 * and would like to run at 2MHz. The 133 below assumes
181 * a 266MHz hrawclk; need to figure out how we're supposed
182 * to know what hrawclk is...
183 */
184 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
185 DP_AUX_CH_CTL_TIME_OUT_1600us |
186 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
187 (5 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
188 (133 << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
189 DP_AUX_CH_CTL_TIME_OUT_ERROR |
190 DP_AUX_CH_CTL_RECEIVE_ERROR);
191
192 /* Send the command and wait for it to complete */
193 I915_WRITE(ch_ctl, ctl);
194 (void) I915_READ(ch_ctl);
195 for (;;) {
196 udelay(100);
197 status = I915_READ(ch_ctl);
198 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
199 break;
200 }
201
202 /* Clear done status and any errors */
203 I915_WRITE(ch_ctl, (ctl |
204 DP_AUX_CH_CTL_DONE |
205 DP_AUX_CH_CTL_TIME_OUT_ERROR |
206 DP_AUX_CH_CTL_RECEIVE_ERROR));
207 (void) I915_READ(ch_ctl);
208
209 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
210 printk(KERN_ERR "dp_aux_ch not done status 0x%08x\n", status);
211 return -1;
212 }
213
214 /* Check for timeout or receive error.
215 * Timeouts occur when the sink is not connected
216 */
217 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | DP_AUX_CH_CTL_RECEIVE_ERROR)) {
218 printk(KERN_ERR "dp_aux_ch error status 0x%08x\n", status);
219 return -1;
220 }
221
222 /* Unload any bytes sent back from the other side */
223 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
224 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
225
226 if (recv_bytes > recv_size)
227 recv_bytes = recv_size;
228
229 for (i = 0; i < recv_bytes; i += 4) {
230 uint32_t d = I915_READ(ch_data + i);
231
232 unpack_aux(d, recv + i, recv_bytes - i);
233 }
234
235 return recv_bytes;
236}
237
238/* Write data to the aux channel in native mode */
239static int
240intel_dp_aux_native_write(struct intel_output *intel_output,
241 uint16_t address, uint8_t *send, int send_bytes)
242{
243 int ret;
244 uint8_t msg[20];
245 int msg_bytes;
246 uint8_t ack;
247
248 if (send_bytes > 16)
249 return -1;
250 msg[0] = AUX_NATIVE_WRITE << 4;
251 msg[1] = address >> 8;
252 msg[2] = address;
253 msg[3] = send_bytes - 1;
254 memcpy(&msg[4], send, send_bytes);
255 msg_bytes = send_bytes + 4;
256 for (;;) {
257 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes, &ack, 1);
258 if (ret < 0)
259 return ret;
260 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
261 break;
262 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
263 udelay(100);
264 else
265 return -1;
266 }
267 return send_bytes;
268}
269
270/* Write a single byte to the aux channel in native mode */
271static int
272intel_dp_aux_native_write_1(struct intel_output *intel_output,
273 uint16_t address, uint8_t byte)
274{
275 return intel_dp_aux_native_write(intel_output, address, &byte, 1);
276}
277
278/* read bytes from a native aux channel */
279static int
280intel_dp_aux_native_read(struct intel_output *intel_output,
281 uint16_t address, uint8_t *recv, int recv_bytes)
282{
283 uint8_t msg[4];
284 int msg_bytes;
285 uint8_t reply[20];
286 int reply_bytes;
287 uint8_t ack;
288 int ret;
289
290 msg[0] = AUX_NATIVE_READ << 4;
291 msg[1] = address >> 8;
292 msg[2] = address & 0xff;
293 msg[3] = recv_bytes - 1;
294
295 msg_bytes = 4;
296 reply_bytes = recv_bytes + 1;
297
298 for (;;) {
299 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes,
300 reply, reply_bytes);
301 if (ret <= 0)
302 return ret;
303 ack = reply[0];
304 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
305 memcpy(recv, reply + 1, ret - 1);
306 return ret - 1;
307 }
308 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
309 udelay(100);
310 else
311 return -1;
312 }
313}
314
315static int
316intel_dp_i2c_aux_ch(struct i2c_adapter *adapter,
317 uint8_t *send, int send_bytes,
318 uint8_t *recv, int recv_bytes)
319{
320 struct intel_dp_priv *dp_priv = container_of(adapter,
321 struct intel_dp_priv,
322 adapter);
323 struct intel_output *intel_output = dp_priv->intel_output;
324
325 return intel_dp_aux_ch(intel_output,
326 send, send_bytes, recv, recv_bytes);
327}
328
329static int
330intel_dp_i2c_init(struct intel_output *intel_output, const char *name)
331{
332 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
333
334 DRM_ERROR("i2c_init %s\n", name);
335 dp_priv->algo.running = false;
336 dp_priv->algo.address = 0;
337 dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
338
339 memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
340 dp_priv->adapter.owner = THIS_MODULE;
341 dp_priv->adapter.class = I2C_CLASS_DDC;
342 strncpy (dp_priv->adapter.name, name, sizeof dp_priv->adapter.name - 1);
343 dp_priv->adapter.name[sizeof dp_priv->adapter.name - 1] = '\0';
344 dp_priv->adapter.algo_data = &dp_priv->algo;
345 dp_priv->adapter.dev.parent = &intel_output->base.kdev;
346
347 return i2c_dp_aux_add_bus(&dp_priv->adapter);
348}
349
350static bool
351intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
352 struct drm_display_mode *adjusted_mode)
353{
354 struct intel_output *intel_output = enc_to_intel_output(encoder);
355 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
356 int lane_count, clock;
357 int max_lane_count = intel_dp_max_lane_count(intel_output);
358 int max_clock = intel_dp_max_link_bw(intel_output) == DP_LINK_BW_2_7 ? 1 : 0;
359 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
360
361 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
362 for (clock = 0; clock <= max_clock; clock++) {
363 int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
364
365 if (intel_dp_link_required(mode->clock) <= link_avail) {
366 dp_priv->link_bw = bws[clock];
367 dp_priv->lane_count = lane_count;
368 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
369 printk(KERN_ERR "link bw %02x lane count %d clock %d\n",
370 dp_priv->link_bw, dp_priv->lane_count,
371 adjusted_mode->clock);
372 return true;
373 }
374 }
375 }
376 return false;
377}
378
379struct intel_dp_m_n {
380 uint32_t tu;
381 uint32_t gmch_m;
382 uint32_t gmch_n;
383 uint32_t link_m;
384 uint32_t link_n;
385};
386
387static void
388intel_reduce_ratio(uint32_t *num, uint32_t *den)
389{
390 while (*num > 0xffffff || *den > 0xffffff) {
391 *num >>= 1;
392 *den >>= 1;
393 }
394}
395
396static void
397intel_dp_compute_m_n(int bytes_per_pixel,
398 int nlanes,
399 int pixel_clock,
400 int link_clock,
401 struct intel_dp_m_n *m_n)
402{
403 m_n->tu = 64;
404 m_n->gmch_m = pixel_clock * bytes_per_pixel;
405 m_n->gmch_n = link_clock * nlanes;
406 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
407 m_n->link_m = pixel_clock;
408 m_n->link_n = link_clock;
409 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
410}
411
412void
413intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
414 struct drm_display_mode *adjusted_mode)
415{
416 struct drm_device *dev = crtc->dev;
417 struct drm_mode_config *mode_config = &dev->mode_config;
418 struct drm_connector *connector;
419 struct drm_i915_private *dev_priv = dev->dev_private;
420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
421 int lane_count = 4;
422 struct intel_dp_m_n m_n;
423
424 /*
425 * Find the lane count in the intel_output private
426 */
427 list_for_each_entry(connector, &mode_config->connector_list, head) {
428 struct intel_output *intel_output = to_intel_output(connector);
429 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
430
431 if (!connector->encoder || connector->encoder->crtc != crtc)
432 continue;
433
434 if (intel_output->type == INTEL_OUTPUT_DISPLAYPORT) {
435 lane_count = dp_priv->lane_count;
436 break;
437 }
438 }
439
440 /*
441 * Compute the GMCH and Link ratios. The '3' here is
442 * the number of bytes_per_pixel post-LUT, which we always
443 * set up for 8-bits of R/G/B, or 3 bytes total.
444 */
445 intel_dp_compute_m_n(3, lane_count,
446 mode->clock, adjusted_mode->clock, &m_n);
447
448 if (intel_crtc->pipe == 0) {
449 I915_WRITE(PIPEA_GMCH_DATA_M,
450 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
451 m_n.gmch_m);
452 I915_WRITE(PIPEA_GMCH_DATA_N,
453 m_n.gmch_n);
454 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
455 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
456 } else {
457 I915_WRITE(PIPEB_GMCH_DATA_M,
458 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
459 m_n.gmch_m);
460 I915_WRITE(PIPEB_GMCH_DATA_N,
461 m_n.gmch_n);
462 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
463 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
464 }
465}
466
467static void
468intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
469 struct drm_display_mode *adjusted_mode)
470{
471 struct intel_output *intel_output = enc_to_intel_output(encoder);
472 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
473 struct drm_crtc *crtc = intel_output->enc.crtc;
474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
475
476 dp_priv->DP = (DP_LINK_TRAIN_OFF |
477 DP_VOLTAGE_0_4 |
478 DP_PRE_EMPHASIS_0 |
479 DP_SYNC_VS_HIGH |
480 DP_SYNC_HS_HIGH);
481
482 switch (dp_priv->lane_count) {
483 case 1:
484 dp_priv->DP |= DP_PORT_WIDTH_1;
485 break;
486 case 2:
487 dp_priv->DP |= DP_PORT_WIDTH_2;
488 break;
489 case 4:
490 dp_priv->DP |= DP_PORT_WIDTH_4;
491 break;
492 }
493 if (dp_priv->has_audio)
494 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
495
496 memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
497 dp_priv->link_configuration[0] = dp_priv->link_bw;
498 dp_priv->link_configuration[1] = dp_priv->lane_count;
499
500 /*
501 * Check for DPCD version > 1.1,
502 * enable enahanced frame stuff in that case
503 */
504 if (dp_priv->dpcd[0] >= 0x11) {
505 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
506 dp_priv->DP |= DP_ENHANCED_FRAMING;
507 }
508
509 if (intel_crtc->pipe == 1)
510 dp_priv->DP |= DP_PIPEB_SELECT;
511}
512
513
514static void
515intel_dp_dpms(struct drm_encoder *encoder, int mode)
516{
517 struct intel_output *intel_output = enc_to_intel_output(encoder);
518 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
519 struct drm_device *dev = intel_output->base.dev;
520 struct drm_i915_private *dev_priv = dev->dev_private;
521 uint32_t dp_reg = I915_READ(dp_priv->output_reg);
522
523 if (mode != DRM_MODE_DPMS_ON) {
524 if (dp_reg & DP_PORT_EN)
525 intel_dp_link_down(intel_output, dp_priv->DP);
526 } else {
527 if (!(dp_reg & DP_PORT_EN))
528 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
529 }
530}
531
532/*
533 * Fetch AUX CH registers 0x202 - 0x207 which contain
534 * link status information
535 */
536static bool
537intel_dp_get_link_status(struct intel_output *intel_output,
538 uint8_t link_status[DP_LINK_STATUS_SIZE])
539{
540 int ret;
541
542 ret = intel_dp_aux_native_read(intel_output,
543 DP_LANE0_1_STATUS,
544 link_status, DP_LINK_STATUS_SIZE);
545 if (ret != DP_LINK_STATUS_SIZE)
546 return false;
547 return true;
548}
549
550static uint8_t
551intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
552 int r)
553{
554 return link_status[r - DP_LANE0_1_STATUS];
555}
556
557static void
558intel_dp_save(struct drm_connector *connector)
559{
560 struct intel_output *intel_output = to_intel_output(connector);
561 struct drm_device *dev = intel_output->base.dev;
562 struct drm_i915_private *dev_priv = dev->dev_private;
563 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
564
565 dp_priv->save_DP = I915_READ(dp_priv->output_reg);
566 intel_dp_aux_native_read(intel_output, DP_LINK_BW_SET,
567 dp_priv->save_link_configuration,
568 sizeof (dp_priv->save_link_configuration));
569}
570
571static uint8_t
572intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
573 int lane)
574{
575 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
576 int s = ((lane & 1) ?
577 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
578 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
579 uint8_t l = intel_dp_link_status(link_status, i);
580
581 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
582}
583
584static uint8_t
585intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
586 int lane)
587{
588 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
589 int s = ((lane & 1) ?
590 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
591 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
592 uint8_t l = intel_dp_link_status(link_status, i);
593
594 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
595}
596
597
598#if 0
599static char *voltage_names[] = {
600 "0.4V", "0.6V", "0.8V", "1.2V"
601};
602static char *pre_emph_names[] = {
603 "0dB", "3.5dB", "6dB", "9.5dB"
604};
605static char *link_train_names[] = {
606 "pattern 1", "pattern 2", "idle", "off"
607};
608#endif
609
610/*
611 * These are source-specific values; current Intel hardware supports
612 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
613 */
614#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
615
616static uint8_t
617intel_dp_pre_emphasis_max(uint8_t voltage_swing)
618{
619 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
620 case DP_TRAIN_VOLTAGE_SWING_400:
621 return DP_TRAIN_PRE_EMPHASIS_6;
622 case DP_TRAIN_VOLTAGE_SWING_600:
623 return DP_TRAIN_PRE_EMPHASIS_6;
624 case DP_TRAIN_VOLTAGE_SWING_800:
625 return DP_TRAIN_PRE_EMPHASIS_3_5;
626 case DP_TRAIN_VOLTAGE_SWING_1200:
627 default:
628 return DP_TRAIN_PRE_EMPHASIS_0;
629 }
630}
631
632static void
633intel_get_adjust_train(struct intel_output *intel_output,
634 uint8_t link_status[DP_LINK_STATUS_SIZE],
635 int lane_count,
636 uint8_t train_set[4])
637{
638 uint8_t v = 0;
639 uint8_t p = 0;
640 int lane;
641
642 for (lane = 0; lane < lane_count; lane++) {
643 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
644 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
645
646 if (this_v > v)
647 v = this_v;
648 if (this_p > p)
649 p = this_p;
650 }
651
652 if (v >= I830_DP_VOLTAGE_MAX)
653 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
654
655 if (p >= intel_dp_pre_emphasis_max(v))
656 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
657
658 for (lane = 0; lane < 4; lane++)
659 train_set[lane] = v | p;
660}
661
662static uint32_t
663intel_dp_signal_levels(uint8_t train_set, int lane_count)
664{
665 uint32_t signal_levels = 0;
666
667 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
668 case DP_TRAIN_VOLTAGE_SWING_400:
669 default:
670 signal_levels |= DP_VOLTAGE_0_4;
671 break;
672 case DP_TRAIN_VOLTAGE_SWING_600:
673 signal_levels |= DP_VOLTAGE_0_6;
674 break;
675 case DP_TRAIN_VOLTAGE_SWING_800:
676 signal_levels |= DP_VOLTAGE_0_8;
677 break;
678 case DP_TRAIN_VOLTAGE_SWING_1200:
679 signal_levels |= DP_VOLTAGE_1_2;
680 break;
681 }
682 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
683 case DP_TRAIN_PRE_EMPHASIS_0:
684 default:
685 signal_levels |= DP_PRE_EMPHASIS_0;
686 break;
687 case DP_TRAIN_PRE_EMPHASIS_3_5:
688 signal_levels |= DP_PRE_EMPHASIS_3_5;
689 break;
690 case DP_TRAIN_PRE_EMPHASIS_6:
691 signal_levels |= DP_PRE_EMPHASIS_6;
692 break;
693 case DP_TRAIN_PRE_EMPHASIS_9_5:
694 signal_levels |= DP_PRE_EMPHASIS_9_5;
695 break;
696 }
697 return signal_levels;
698}
699
700static uint8_t
701intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
702 int lane)
703{
704 int i = DP_LANE0_1_STATUS + (lane >> 1);
705 int s = (lane & 1) * 4;
706 uint8_t l = intel_dp_link_status(link_status, i);
707
708 return (l >> s) & 0xf;
709}
710
711/* Check for clock recovery is done on all channels */
712static bool
713intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
714{
715 int lane;
716 uint8_t lane_status;
717
718 for (lane = 0; lane < lane_count; lane++) {
719 lane_status = intel_get_lane_status(link_status, lane);
720 if ((lane_status & DP_LANE_CR_DONE) == 0)
721 return false;
722 }
723 return true;
724}
725
726/* Check to see if channel eq is done on all channels */
727#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
728 DP_LANE_CHANNEL_EQ_DONE|\
729 DP_LANE_SYMBOL_LOCKED)
730static bool
731intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
732{
733 uint8_t lane_align;
734 uint8_t lane_status;
735 int lane;
736
737 lane_align = intel_dp_link_status(link_status,
738 DP_LANE_ALIGN_STATUS_UPDATED);
739 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
740 return false;
741 for (lane = 0; lane < lane_count; lane++) {
742 lane_status = intel_get_lane_status(link_status, lane);
743 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
744 return false;
745 }
746 return true;
747}
748
749static bool
750intel_dp_set_link_train(struct intel_output *intel_output,
751 uint32_t dp_reg_value,
752 uint8_t dp_train_pat,
753 uint8_t train_set[4],
754 bool first)
755{
756 struct drm_device *dev = intel_output->base.dev;
757 struct drm_i915_private *dev_priv = dev->dev_private;
758 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
759 int ret;
760
761 I915_WRITE(dp_priv->output_reg, dp_reg_value);
762 POSTING_READ(dp_priv->output_reg);
763 if (first)
764 intel_wait_for_vblank(dev);
765
766 intel_dp_aux_native_write_1(intel_output,
767 DP_TRAINING_PATTERN_SET,
768 dp_train_pat);
769
770 ret = intel_dp_aux_native_write(intel_output,
771 DP_TRAINING_LANE0_SET, train_set, 4);
772 if (ret != 4)
773 return false;
774
775 return true;
776}
777
778static void
779intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
780 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
781{
782 struct drm_device *dev = intel_output->base.dev;
783 struct drm_i915_private *dev_priv = dev->dev_private;
784 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
785 uint8_t train_set[4];
786 uint8_t link_status[DP_LINK_STATUS_SIZE];
787 int i;
788 uint8_t voltage;
789 bool clock_recovery = false;
790 bool channel_eq = false;
791 bool first = true;
792 int tries;
793
794 /* Write the link configuration data */
795 intel_dp_aux_native_write(intel_output, 0x100,
796 link_configuration, DP_LINK_CONFIGURATION_SIZE);
797
798 DP |= DP_PORT_EN;
799 DP &= ~DP_LINK_TRAIN_MASK;
800 memset(train_set, 0, 4);
801 voltage = 0xff;
802 tries = 0;
803 clock_recovery = false;
804 for (;;) {
805 /* Use train_set[0] to set the voltage and pre emphasis values */
806 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
807 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
808
809 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_1,
810 DP_TRAINING_PATTERN_1, train_set, first))
811 break;
812 first = false;
813 /* Set training pattern 1 */
814
815 udelay(100);
816 if (!intel_dp_get_link_status(intel_output, link_status))
817 break;
818
819 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
820 clock_recovery = true;
821 break;
822 }
823
824 /* Check to see if we've tried the max voltage */
825 for (i = 0; i < dp_priv->lane_count; i++)
826 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
827 break;
828 if (i == dp_priv->lane_count)
829 break;
830
831 /* Check to see if we've tried the same voltage 5 times */
832 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
833 ++tries;
834 if (tries == 5)
835 break;
836 } else
837 tries = 0;
838 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
839
840 /* Compute new train_set as requested by target */
841 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
842 }
843
844 /* channel equalization */
845 tries = 0;
846 channel_eq = false;
847 for (;;) {
848 /* Use train_set[0] to set the voltage and pre emphasis values */
849 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
850 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
851
852 /* channel eq pattern */
853 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_2,
854 DP_TRAINING_PATTERN_2, train_set,
855 false))
856 break;
857
858 udelay(400);
859 if (!intel_dp_get_link_status(intel_output, link_status))
860 break;
861
862 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
863 channel_eq = true;
864 break;
865 }
866
867 /* Try 5 times */
868 if (tries > 5)
869 break;
870
871 /* Compute new train_set as requested by target */
872 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
873 ++tries;
874 }
875
876 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF);
877 POSTING_READ(dp_priv->output_reg);
878 intel_dp_aux_native_write_1(intel_output,
879 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
880}
881
882static void
883intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
884{
885 struct drm_device *dev = intel_output->base.dev;
886 struct drm_i915_private *dev_priv = dev->dev_private;
887 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
888
889 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
890 POSTING_READ(dp_priv->output_reg);
891}
892
893static void
894intel_dp_restore(struct drm_connector *connector)
895{
896 struct intel_output *intel_output = to_intel_output(connector);
897 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
898
899 if (dp_priv->save_DP & DP_PORT_EN)
900 intel_dp_link_train(intel_output, dp_priv->save_DP, dp_priv->save_link_configuration);
901 else
902 intel_dp_link_down(intel_output, dp_priv->save_DP);
903}
904
905#if 0
906/*
907 * According to DP spec
908 * 5.1.2:
909 * 1. Read DPCD
910 * 2. Configure link according to Receiver Capabilities
911 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
912 * 4. Check link status on receipt of hot-plug interrupt
913 */
914
915static void
916intel_dp_check_link_status(struct intel_output *intel_output)
917{
918 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
919 uint8_t link_status[DP_LINK_STATUS_SIZE];
920
921 if (!intel_output->enc.crtc)
922 return;
923
924 if (!intel_dp_get_link_status(intel_output, link_status)) {
925 intel_dp_link_down(intel_output, dp_priv->DP);
926 return;
927 }
928
929 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
930 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
931}
932#endif
933
934/**
935 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
936 *
937 * \return true if DP port is connected.
938 * \return false if DP port is disconnected.
939 */
940static enum drm_connector_status
941intel_dp_detect(struct drm_connector *connector)
942{
943 struct intel_output *intel_output = to_intel_output(connector);
944 struct drm_device *dev = intel_output->base.dev;
945 struct drm_i915_private *dev_priv = dev->dev_private;
946 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
947 uint32_t temp, bit;
948 enum drm_connector_status status;
949
950 dp_priv->has_audio = false;
951
952 temp = I915_READ(PORT_HOTPLUG_EN);
953
954 I915_WRITE(PORT_HOTPLUG_EN,
955 temp |
956 DPB_HOTPLUG_INT_EN |
957 DPC_HOTPLUG_INT_EN |
958 DPD_HOTPLUG_INT_EN);
959
960 POSTING_READ(PORT_HOTPLUG_EN);
961
962 switch (dp_priv->output_reg) {
963 case DP_B:
964 bit = DPB_HOTPLUG_INT_STATUS;
965 break;
966 case DP_C:
967 bit = DPC_HOTPLUG_INT_STATUS;
968 break;
969 case DP_D:
970 bit = DPD_HOTPLUG_INT_STATUS;
971 break;
972 default:
973 return connector_status_unknown;
974 }
975
976 temp = I915_READ(PORT_HOTPLUG_STAT);
977
978 if ((temp & bit) == 0)
979 return connector_status_disconnected;
980
981 status = connector_status_disconnected;
982 if (intel_dp_aux_native_read(intel_output,
983 0x000, dp_priv->dpcd,
984 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
985 {
986 if (dp_priv->dpcd[0] != 0)
987 status = connector_status_connected;
988 }
989 return status;
990}
991
992static int intel_dp_get_modes(struct drm_connector *connector)
993{
994 struct intel_output *intel_output = to_intel_output(connector);
995
996 /* We should parse the EDID data and find out if it has an audio sink
997 */
998
999 return intel_ddc_get_modes(intel_output);
1000}
1001
1002static void
1003intel_dp_destroy (struct drm_connector *connector)
1004{
1005 struct intel_output *intel_output = to_intel_output(connector);
1006
1007 if (intel_output->i2c_bus)
1008 intel_i2c_destroy(intel_output->i2c_bus);
1009 drm_sysfs_connector_remove(connector);
1010 drm_connector_cleanup(connector);
1011 kfree(intel_output);
1012}
1013
1014static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1015 .dpms = intel_dp_dpms,
1016 .mode_fixup = intel_dp_mode_fixup,
1017 .prepare = intel_encoder_prepare,
1018 .mode_set = intel_dp_mode_set,
1019 .commit = intel_encoder_commit,
1020};
1021
1022static const struct drm_connector_funcs intel_dp_connector_funcs = {
1023 .dpms = drm_helper_connector_dpms,
1024 .save = intel_dp_save,
1025 .restore = intel_dp_restore,
1026 .detect = intel_dp_detect,
1027 .fill_modes = drm_helper_probe_single_connector_modes,
1028 .destroy = intel_dp_destroy,
1029};
1030
1031static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1032 .get_modes = intel_dp_get_modes,
1033 .mode_valid = intel_dp_mode_valid,
1034 .best_encoder = intel_best_encoder,
1035};
1036
1037static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1038{
1039 drm_encoder_cleanup(encoder);
1040}
1041
1042static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1043 .destroy = intel_dp_enc_destroy,
1044};
1045
1046void
1047intel_dp_init(struct drm_device *dev, int output_reg)
1048{
1049 struct drm_i915_private *dev_priv = dev->dev_private;
1050 struct drm_connector *connector;
1051 struct intel_output *intel_output;
1052 struct intel_dp_priv *dp_priv;
1053
1054 intel_output = kcalloc(sizeof(struct intel_output) +
1055 sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1056 if (!intel_output)
1057 return;
1058
1059 dp_priv = (struct intel_dp_priv *)(intel_output + 1);
1060
1061 connector = &intel_output->base;
1062 drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1063 DRM_MODE_CONNECTOR_DisplayPort);
1064 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1065
1066 intel_output->type = INTEL_OUTPUT_DISPLAYPORT;
1067
1068 connector->interlace_allowed = true;
1069 connector->doublescan_allowed = 0;
1070
1071 dp_priv->intel_output = intel_output;
1072 dp_priv->output_reg = output_reg;
1073 dp_priv->has_audio = false;
1074 intel_output->dev_priv = dp_priv;
1075
1076 drm_encoder_init(dev, &intel_output->enc, &intel_dp_enc_funcs,
1077 DRM_MODE_ENCODER_TMDS);
1078 drm_encoder_helper_add(&intel_output->enc, &intel_dp_helper_funcs);
1079
1080 drm_mode_connector_attach_encoder(&intel_output->base,
1081 &intel_output->enc);
1082 drm_sysfs_connector_add(connector);
1083
1084 /* Set up the DDC bus. */
1085 intel_dp_i2c_init(intel_output,
1086 (output_reg == DP_B) ? "DPDDC-B" :
1087 (output_reg == DP_C) ? "DPDDC-C" : "DPDDC-D");
1088 intel_output->ddc_bus = &dp_priv->adapter;
1089
1090 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1091 * 0xd. Failure to do so will result in spurious interrupts being
1092 * generated on the port when a cable is not attached.
1093 */
1094 if (IS_G4X(dev) && !IS_GM45(dev)) {
1095 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1096 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1097 }
1098}
diff --git a/drivers/gpu/drm/i915/intel_dp.h b/drivers/gpu/drm/i915/intel_dp.h
new file mode 100644
index 000000000000..2b38054d3b6d
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp.h
@@ -0,0 +1,144 @@
1/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#ifndef _INTEL_DP_H_
24#define _INTEL_DP_H_
25
26/* From the VESA DisplayPort spec */
27
28#define AUX_NATIVE_WRITE 0x8
29#define AUX_NATIVE_READ 0x9
30#define AUX_I2C_WRITE 0x0
31#define AUX_I2C_READ 0x1
32#define AUX_I2C_STATUS 0x2
33#define AUX_I2C_MOT 0x4
34
35#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
36#define AUX_NATIVE_REPLY_NACK (0x1 << 4)
37#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
38#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
39
40#define AUX_I2C_REPLY_ACK (0x0 << 6)
41#define AUX_I2C_REPLY_NACK (0x1 << 6)
42#define AUX_I2C_REPLY_DEFER (0x2 << 6)
43#define AUX_I2C_REPLY_MASK (0x3 << 6)
44
45/* AUX CH addresses */
46#define DP_LINK_BW_SET 0x100
47# define DP_LINK_BW_1_62 0x06
48# define DP_LINK_BW_2_7 0x0a
49
50#define DP_LANE_COUNT_SET 0x101
51# define DP_LANE_COUNT_MASK 0x0f
52# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
53
54#define DP_TRAINING_PATTERN_SET 0x102
55
56# define DP_TRAINING_PATTERN_DISABLE 0
57# define DP_TRAINING_PATTERN_1 1
58# define DP_TRAINING_PATTERN_2 2
59# define DP_TRAINING_PATTERN_MASK 0x3
60
61# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
62# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
63# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
64# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
65# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
66
67# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
68# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
69
70# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
71# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
72# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
73# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
74
75#define DP_TRAINING_LANE0_SET 0x103
76#define DP_TRAINING_LANE1_SET 0x104
77#define DP_TRAINING_LANE2_SET 0x105
78#define DP_TRAINING_LANE3_SET 0x106
79
80# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
81# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
82# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
83# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
84# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
85# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
86# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
87
88# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
89# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
90# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
91# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
92# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
93
94# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
95# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
96
97#define DP_DOWNSPREAD_CTRL 0x107
98# define DP_SPREAD_AMP_0_5 (1 << 4)
99
100#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
101# define DP_SET_ANSI_8B10B (1 << 0)
102
103#define DP_LANE0_1_STATUS 0x202
104#define DP_LANE2_3_STATUS 0x203
105
106# define DP_LANE_CR_DONE (1 << 0)
107# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
108# define DP_LANE_SYMBOL_LOCKED (1 << 2)
109
110#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
111
112#define DP_INTERLANE_ALIGN_DONE (1 << 0)
113#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
114#define DP_LINK_STATUS_UPDATED (1 << 7)
115
116#define DP_SINK_STATUS 0x205
117
118#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
119#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
120
121#define DP_ADJUST_REQUEST_LANE0_1 0x206
122#define DP_ADJUST_REQUEST_LANE2_3 0x207
123
124#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
125#define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
126#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
127#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
128#define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
129#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
130#define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
131#define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
132
133struct i2c_algo_dp_aux_data {
134 bool running;
135 u16 address;
136 int (*aux_ch) (struct i2c_adapter *adapter,
137 uint8_t *send, int send_bytes,
138 uint8_t *recv, int recv_bytes);
139};
140
141int
142i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
143
144#endif /* _INTEL_DP_H_ */
diff --git a/drivers/gpu/drm/i915/intel_dp_i2c.c b/drivers/gpu/drm/i915/intel_dp_i2c.c
new file mode 100644
index 000000000000..4e60f14b1a6d
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp_i2c.c
@@ -0,0 +1,272 @@
1/*
2 * Copyright © 2009 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
27#include <linux/init.h>
28#include <linux/errno.h>
29#include <linux/sched.h>
30#include <linux/i2c.h>
31#include "intel_dp.h"
32
33/* Run a single AUX_CH I2C transaction, writing/reading data as necessary */
34
35#define MODE_I2C_START 1
36#define MODE_I2C_WRITE 2
37#define MODE_I2C_READ 4
38#define MODE_I2C_STOP 8
39
40static int
41i2c_algo_dp_aux_transaction(struct i2c_adapter *adapter, int mode,
42 uint8_t write_byte, uint8_t *read_byte)
43{
44 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
45 uint16_t address = algo_data->address;
46 uint8_t msg[5];
47 uint8_t reply[2];
48 int msg_bytes;
49 int reply_bytes;
50 int ret;
51
52 /* Set up the command byte */
53 if (mode & MODE_I2C_READ)
54 msg[0] = AUX_I2C_READ << 4;
55 else
56 msg[0] = AUX_I2C_WRITE << 4;
57
58 if (!(mode & MODE_I2C_STOP))
59 msg[0] |= AUX_I2C_MOT << 4;
60
61 msg[1] = address >> 8;
62 msg[2] = address;
63
64 switch (mode) {
65 case MODE_I2C_WRITE:
66 msg[3] = 0;
67 msg[4] = write_byte;
68 msg_bytes = 5;
69 reply_bytes = 1;
70 break;
71 case MODE_I2C_READ:
72 msg[3] = 0;
73 msg_bytes = 4;
74 reply_bytes = 2;
75 break;
76 default:
77 msg_bytes = 3;
78 reply_bytes = 1;
79 break;
80 }
81
82 for (;;) {
83 ret = (*algo_data->aux_ch)(adapter,
84 msg, msg_bytes,
85 reply, reply_bytes);
86 if (ret < 0) {
87 printk(KERN_ERR "aux_ch failed %d\n", ret);
88 return ret;
89 }
90 switch (reply[0] & AUX_I2C_REPLY_MASK) {
91 case AUX_I2C_REPLY_ACK:
92 if (mode == MODE_I2C_READ) {
93 *read_byte = reply[1];
94 }
95 return reply_bytes - 1;
96 case AUX_I2C_REPLY_NACK:
97 printk(KERN_ERR "aux_ch nack\n");
98 return -EREMOTEIO;
99 case AUX_I2C_REPLY_DEFER:
100 printk(KERN_ERR "aux_ch defer\n");
101 udelay(100);
102 break;
103 default:
104 printk(KERN_ERR "aux_ch invalid reply 0x%02x\n", reply[0]);
105 return -EREMOTEIO;
106 }
107 }
108}
109
110/*
111 * I2C over AUX CH
112 */
113
114/*
115 * Send the address. If the I2C link is running, this 'restarts'
116 * the connection with the new address, this is used for doing
117 * a write followed by a read (as needed for DDC)
118 */
119static int
120i2c_algo_dp_aux_address(struct i2c_adapter *adapter, u16 address, bool reading)
121{
122 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
123 int mode = MODE_I2C_START;
124 int ret;
125
126 if (reading)
127 mode |= MODE_I2C_READ;
128 else
129 mode |= MODE_I2C_WRITE;
130 algo_data->address = address;
131 algo_data->running = true;
132 ret = i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
133 return ret;
134}
135
136/*
137 * Stop the I2C transaction. This closes out the link, sending
138 * a bare address packet with the MOT bit turned off
139 */
140static void
141i2c_algo_dp_aux_stop(struct i2c_adapter *adapter, bool reading)
142{
143 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
144 int mode = MODE_I2C_STOP;
145
146 if (reading)
147 mode |= MODE_I2C_READ;
148 else
149 mode |= MODE_I2C_WRITE;
150 if (algo_data->running) {
151 (void) i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
152 algo_data->running = false;
153 }
154}
155
156/*
157 * Write a single byte to the current I2C address, the
158 * the I2C link must be running or this returns -EIO
159 */
160static int
161i2c_algo_dp_aux_put_byte(struct i2c_adapter *adapter, u8 byte)
162{
163 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
164 int ret;
165
166 if (!algo_data->running)
167 return -EIO;
168
169 ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_WRITE, byte, NULL);
170 return ret;
171}
172
173/*
174 * Read a single byte from the current I2C address, the
175 * I2C link must be running or this returns -EIO
176 */
177static int
178i2c_algo_dp_aux_get_byte(struct i2c_adapter *adapter, u8 *byte_ret)
179{
180 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
181 int ret;
182
183 if (!algo_data->running)
184 return -EIO;
185
186 ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_READ, 0, byte_ret);
187 return ret;
188}
189
190static int
191i2c_algo_dp_aux_xfer(struct i2c_adapter *adapter,
192 struct i2c_msg *msgs,
193 int num)
194{
195 int ret = 0;
196 bool reading = false;
197 int m;
198 int b;
199
200 for (m = 0; m < num; m++) {
201 u16 len = msgs[m].len;
202 u8 *buf = msgs[m].buf;
203 reading = (msgs[m].flags & I2C_M_RD) != 0;
204 ret = i2c_algo_dp_aux_address(adapter, msgs[m].addr, reading);
205 if (ret < 0)
206 break;
207 if (reading) {
208 for (b = 0; b < len; b++) {
209 ret = i2c_algo_dp_aux_get_byte(adapter, &buf[b]);
210 if (ret < 0)
211 break;
212 }
213 } else {
214 for (b = 0; b < len; b++) {
215 ret = i2c_algo_dp_aux_put_byte(adapter, buf[b]);
216 if (ret < 0)
217 break;
218 }
219 }
220 if (ret < 0)
221 break;
222 }
223 if (ret >= 0)
224 ret = num;
225 i2c_algo_dp_aux_stop(adapter, reading);
226 printk(KERN_ERR "dp_aux_xfer return %d\n", ret);
227 return ret;
228}
229
230static u32
231i2c_algo_dp_aux_functionality(struct i2c_adapter *adapter)
232{
233 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
234 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
235 I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
236 I2C_FUNC_10BIT_ADDR;
237}
238
239static const struct i2c_algorithm i2c_dp_aux_algo = {
240 .master_xfer = i2c_algo_dp_aux_xfer,
241 .functionality = i2c_algo_dp_aux_functionality,
242};
243
244static void
245i2c_dp_aux_reset_bus(struct i2c_adapter *adapter)
246{
247 (void) i2c_algo_dp_aux_address(adapter, 0, false);
248 (void) i2c_algo_dp_aux_stop(adapter, false);
249
250}
251
252static int
253i2c_dp_aux_prepare_bus(struct i2c_adapter *adapter)
254{
255 adapter->algo = &i2c_dp_aux_algo;
256 adapter->retries = 3;
257 i2c_dp_aux_reset_bus(adapter);
258 return 0;
259}
260
261int
262i2c_dp_aux_add_bus(struct i2c_adapter *adapter)
263{
264 int error;
265
266 error = i2c_dp_aux_prepare_bus(adapter);
267 if (error)
268 return error;
269 error = i2c_add_adapter(adapter);
270 return error;
271}
272EXPORT_SYMBOL(i2c_dp_aux_add_bus);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c5858792c806..004541c935a8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -54,6 +54,7 @@
54#define INTEL_OUTPUT_LVDS 4 54#define INTEL_OUTPUT_LVDS 4
55#define INTEL_OUTPUT_TVOUT 5 55#define INTEL_OUTPUT_TVOUT 5
56#define INTEL_OUTPUT_HDMI 6 56#define INTEL_OUTPUT_HDMI 6
57#define INTEL_OUTPUT_DISPLAYPORT 7
57 58
58#define INTEL_DVO_CHIP_NONE 0 59#define INTEL_DVO_CHIP_NONE 0
59#define INTEL_DVO_CHIP_LVDS 1 60#define INTEL_DVO_CHIP_LVDS 1
@@ -116,6 +117,10 @@ extern bool intel_sdvo_init(struct drm_device *dev, int output_device);
116extern void intel_dvo_init(struct drm_device *dev); 117extern void intel_dvo_init(struct drm_device *dev);
117extern void intel_tv_init(struct drm_device *dev); 118extern void intel_tv_init(struct drm_device *dev);
118extern void intel_lvds_init(struct drm_device *dev); 119extern void intel_lvds_init(struct drm_device *dev);
120extern void intel_dp_init(struct drm_device *dev, int dp_reg);
121void
122intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
123 struct drm_display_mode *adjusted_mode);
119 124
120extern void intel_crtc_load_lut(struct drm_crtc *crtc); 125extern void intel_crtc_load_lut(struct drm_crtc *crtc);
121extern void intel_encoder_prepare (struct drm_encoder *encoder); 126extern void intel_encoder_prepare (struct drm_encoder *encoder);
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-27 18:11:12 -0400