diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2010-11-30 19:11:45 -0500 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2010-11-30 21:13:10 -0500 |
| commit | 0ec80d645661dda50acd417bdfcb33df2e5dd31e (patch) | |
| tree | b87d6dab03b0185d7e556666874cfa83d03cae52 /drivers/gpu | |
| parent | 150f8815bbd15c1a91f74033c048fadcd5f3c715 (diff) | |
drm/radeon/kms: fix typos in disabled vbios code
6xx/7xx was hitting the wrong BUS_CNTL reg and bits.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Cc: stable@kernel.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/radeon/r600_reg.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_bios.c | 13 |
2 files changed, 8 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/r600_reg.h b/drivers/gpu/drm/radeon/r600_reg.h index d84612ae47e0..33cda016b083 100644 --- a/drivers/gpu/drm/radeon/r600_reg.h +++ b/drivers/gpu/drm/radeon/r600_reg.h | |||
| @@ -86,6 +86,7 @@ | |||
| 86 | #define R600_HDP_NONSURFACE_BASE 0x2c04 | 86 | #define R600_HDP_NONSURFACE_BASE 0x2c04 |
| 87 | 87 | ||
| 88 | #define R600_BUS_CNTL 0x5420 | 88 | #define R600_BUS_CNTL 0x5420 |
| 89 | # define R600_BIOS_ROM_DIS (1 << 1) | ||
| 89 | #define R600_CONFIG_CNTL 0x5424 | 90 | #define R600_CONFIG_CNTL 0x5424 |
| 90 | #define R600_CONFIG_MEMSIZE 0x5428 | 91 | #define R600_CONFIG_MEMSIZE 0x5428 |
| 91 | #define R600_CONFIG_F0_BASE 0x542C | 92 | #define R600_CONFIG_F0_BASE 0x542C |
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c index 654787ec43f4..8f2c7b50dcf5 100644 --- a/drivers/gpu/drm/radeon/radeon_bios.c +++ b/drivers/gpu/drm/radeon/radeon_bios.c | |||
| @@ -130,6 +130,7 @@ static bool radeon_atrm_get_bios(struct radeon_device *rdev) | |||
| 130 | } | 130 | } |
| 131 | return true; | 131 | return true; |
| 132 | } | 132 | } |
| 133 | |||
| 133 | static bool r700_read_disabled_bios(struct radeon_device *rdev) | 134 | static bool r700_read_disabled_bios(struct radeon_device *rdev) |
| 134 | { | 135 | { |
| 135 | uint32_t viph_control; | 136 | uint32_t viph_control; |
| @@ -143,7 +144,7 @@ static bool r700_read_disabled_bios(struct radeon_device *rdev) | |||
| 143 | bool r; | 144 | bool r; |
| 144 | 145 | ||
| 145 | viph_control = RREG32(RADEON_VIPH_CONTROL); | 146 | viph_control = RREG32(RADEON_VIPH_CONTROL); |
| 146 | bus_cntl = RREG32(RADEON_BUS_CNTL); | 147 | bus_cntl = RREG32(R600_BUS_CNTL); |
| 147 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); | 148 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
| 148 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); | 149 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); |
| 149 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); | 150 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); |
| @@ -152,7 +153,7 @@ static bool r700_read_disabled_bios(struct radeon_device *rdev) | |||
| 152 | /* disable VIP */ | 153 | /* disable VIP */ |
| 153 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); | 154 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
| 154 | /* enable the rom */ | 155 | /* enable the rom */ |
| 155 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); | 156 | WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); |
| 156 | /* Disable VGA mode */ | 157 | /* Disable VGA mode */ |
| 157 | WREG32(AVIVO_D1VGA_CONTROL, | 158 | WREG32(AVIVO_D1VGA_CONTROL, |
| 158 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | 159 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
| @@ -191,7 +192,7 @@ static bool r700_read_disabled_bios(struct radeon_device *rdev) | |||
| 191 | cg_spll_status = RREG32(R600_CG_SPLL_STATUS); | 192 | cg_spll_status = RREG32(R600_CG_SPLL_STATUS); |
| 192 | } | 193 | } |
| 193 | WREG32(RADEON_VIPH_CONTROL, viph_control); | 194 | WREG32(RADEON_VIPH_CONTROL, viph_control); |
| 194 | WREG32(RADEON_BUS_CNTL, bus_cntl); | 195 | WREG32(R600_BUS_CNTL, bus_cntl); |
| 195 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); | 196 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
| 196 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); | 197 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); |
| 197 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); | 198 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); |
| @@ -216,7 +217,7 @@ static bool r600_read_disabled_bios(struct radeon_device *rdev) | |||
| 216 | bool r; | 217 | bool r; |
| 217 | 218 | ||
| 218 | viph_control = RREG32(RADEON_VIPH_CONTROL); | 219 | viph_control = RREG32(RADEON_VIPH_CONTROL); |
| 219 | bus_cntl = RREG32(RADEON_BUS_CNTL); | 220 | bus_cntl = RREG32(R600_BUS_CNTL); |
| 220 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); | 221 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
| 221 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); | 222 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); |
| 222 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); | 223 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); |
| @@ -231,7 +232,7 @@ static bool r600_read_disabled_bios(struct radeon_device *rdev) | |||
| 231 | /* disable VIP */ | 232 | /* disable VIP */ |
| 232 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); | 233 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
| 233 | /* enable the rom */ | 234 | /* enable the rom */ |
| 234 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); | 235 | WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); |
| 235 | /* Disable VGA mode */ | 236 | /* Disable VGA mode */ |
| 236 | WREG32(AVIVO_D1VGA_CONTROL, | 237 | WREG32(AVIVO_D1VGA_CONTROL, |
| 237 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | 238 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
| @@ -262,7 +263,7 @@ static bool r600_read_disabled_bios(struct radeon_device *rdev) | |||
| 262 | 263 | ||
| 263 | /* restore regs */ | 264 | /* restore regs */ |
| 264 | WREG32(RADEON_VIPH_CONTROL, viph_control); | 265 | WREG32(RADEON_VIPH_CONTROL, viph_control); |
| 265 | WREG32(RADEON_BUS_CNTL, bus_cntl); | 266 | WREG32(R600_BUS_CNTL, bus_cntl); |
| 266 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); | 267 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
| 267 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); | 268 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); |
| 268 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); | 269 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); |
