drm/nouveau: give a slightly larger pci(e)gart aperture on all chipsets

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

2 files changed, 4 insertions, 8 deletions

diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
index 27aac9ada73a..38483a042bc2 100644
--- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
@@ -341,10 +341,10 @@ nouveau_sgdma_init(struct drm_device *dev)
         u32 aper_size, align;
         int ret;
 
-        if (dev_priv->card_type >= NV_40 && pci_is_pcie(dev->pdev))
+        if (dev_priv->card_type >= NV_40)
                 aper_size = 512 * 1024 * 1024;
         else
-                aper_size = 64 * 1024 * 1024;
+                aper_size = 128 * 1024 * 1024;
 
         /* Dear NVIDIA, NV44+ would like proper present bits in PTEs for
          * christmas.  The cards before it have them, the cards after
diff --git a/drivers/gpu/drm/nouveau/nv04_instmem.c b/drivers/gpu/drm/nouveau/nv04_instmem.c
index c1248e0740a3..1acc626f74b0 100644
--- a/drivers/gpu/drm/nouveau/nv04_instmem.c
+++ b/drivers/gpu/drm/nouveau/nv04_instmem.c
@@ -41,12 +41,8 @@ int nv04_instmem_init(struct drm_device *dev)
                 rsvd += 16 * 1024;
                 rsvd *= dev_priv->engine.fifo.channels;
 
-                /* pciegart table */
-                if (pci_is_pcie(dev->pdev))
-                        rsvd += 512 * 1024;
-
-                /* object storage */
-                rsvd += 512 * 1024;
+                rsvd += 512 * 1024; /* pci(e)gart table */
+                rsvd += 512 * 1024; /* object storage */
 
                 dev_priv->ramin_rsvd_vram = round_up(rsvd, 4096);
         } else {