Merge remote branch 'nouveau/drm-nouveau-fixes' of /ssd/git/drm-nouveau-next into drm-fixes

* 'nouveau/drm-nouveau-fixes' of /ssd/git/drm-nouveau-next:
  drm/nvc0: improve vm flush function
  drm/nv50-nvc0: remove some code that doesn't belong here
  drm/nv50: use "nv86" tlb flush method on everything except 0x50/0xac
  drm/nouveau: quirk for XFX GT-240X-YA
  drm/nv50-nvc0: work around an evo channel hang that some people see
  drm/nouveau: implement init table opcode 0x5c
  drm/nouveau: fix oops on unload with disabled LVDS panel
  nv30: Fix parsing of perf table
  drm/nouveau: correct memtiming table parsing for nv4x

10 files changed, 129 insertions, 59 deletions

diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 8314a49b6b9a..90aef64b76f2 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -269,7 +269,7 @@ struct init_tbl_entry {
         int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
 };
 
-static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *);
+static int parse_init_table(struct nvbios *, uint16_t, struct init_exec *);
 
 #define MACRO_INDEX_SIZE        2
 #define MACRO_SIZE              8
@@ -2011,6 +2011,27 @@ init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 }
 
 static int
+init_jump(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
+{
+        /*
+         * INIT_JUMP   opcode: 0x5C ('\')
+         *
+         * offset      (8  bit): opcode
+         * offset + 1  (16 bit): offset (in bios)
+         *
+         * Continue execution of init table from 'offset'
+         */
+
+        uint16_t jmp_offset = ROM16(bios->data[offset + 1]);
+
+        if (!iexec->execute)
+                return 3;
+
+        BIOSLOG(bios, "0x%04X: Jump to 0x%04X\n", offset, jmp_offset);
+        return jmp_offset - offset;
+}
+
+static int
 init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
@@ -3659,6 +3680,7 @@ static struct init_tbl_entry itbl_entry[] = {
         { "INIT_ZM_REG_SEQUENCE"              , 0x58, init_zm_reg_sequence            },
         /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
         { "INIT_SUB_DIRECT"                   , 0x5B, init_sub_direct                 },
+        { "INIT_JUMP"                         , 0x5C, init_jump                       },
         { "INIT_I2C_IF"                       , 0x5E, init_i2c_if                     },
         { "INIT_COPY_NV_REG"                  , 0x5F, init_copy_nv_reg                },
         { "INIT_ZM_INDEX_IO"                  , 0x62, init_zm_index_io                },
@@ -3700,8 +3722,7 @@ static struct init_tbl_entry itbl_entry[] = {
 #define MAX_TABLE_OPS 1000
 
 static int
-parse_init_table(struct nvbios *bios, unsigned int offset,
-                 struct init_exec *iexec)
+parse_init_table(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
 {
         /*
          * Parses all commands in an init table.
@@ -6333,6 +6354,32 @@ apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
                 }
         }
 
+        /* XFX GT-240X-YA
+         *
+         * So many things wrong here, replace the entire encoder table..
+         */
+        if (nv_match_device(dev, 0x0ca3, 0x1682, 0x3003)) {
+                if (idx == 0) {
+                        *conn = 0x02001300; /* VGA, connector 1 */
+                        *conf = 0x00000028;
+                } else
+                if (idx == 1) {
+                        *conn = 0x01010312; /* DVI, connector 0 */
+                        *conf = 0x00020030;
+                } else
+                if (idx == 2) {
+                        *conn = 0x01010310; /* VGA, connector 0 */
+                        *conf = 0x00000028;
+                } else
+                if (idx == 3) {
+                        *conn = 0x02022362; /* HDMI, connector 2 */
+                        *conf = 0x00020010;
+                } else {
+                        *conn = 0x0000000e; /* EOL */
+                        *conf = 0x00000000;
+                }
+        }
+
         return true;
 }
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 57e5302503db..856d56a98d1e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -1190,7 +1190,7 @@ extern int  nv50_graph_load_context(struct nouveau_channel *);
 extern int  nv50_graph_unload_context(struct drm_device *);
 extern int  nv50_grctx_init(struct nouveau_grctx *);
 extern void nv50_graph_tlb_flush(struct drm_device *dev);
-extern void nv86_graph_tlb_flush(struct drm_device *dev);
+extern void nv84_graph_tlb_flush(struct drm_device *dev);
 extern struct nouveau_enum nv50_data_error_names[];
 
 /* nvc0_graph.c */
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 2683377f4131..78f467fe30be 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -552,6 +552,7 @@ nouveau_mem_timing_init(struct drm_device *dev)
         u8 tRC;         /* Byte 9 */
         u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14;
         u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21;
+        u8 magic_number = 0; /* Yeah... sorry*/
         u8 *mem = NULL, *entry;
         int i, recordlen, entries;
 
@@ -596,6 +597,12 @@ nouveau_mem_timing_init(struct drm_device *dev)
         if (!memtimings->timing)
                 return;
 
+        /* Get "some number" from the timing reg for NV_40
+         * Used in calculations later */
+        if(dev_priv->card_type == NV_40) {
+                magic_number = (nv_rd32(dev,0x100228) & 0x0f000000) >> 24;
+        }
+
         entry = mem + mem[1];
         for (i = 0; i < entries; i++, entry += recordlen) {
                 struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i];
@@ -635,36 +642,51 @@ nouveau_mem_timing_init(struct drm_device *dev)
 
                 /* XXX: I don't trust the -1's and +1's... they must come
                  *      from somewhere! */
-                timing->reg_100224 = ((tUNK_0 + tUNK_19 + 1) << 24 |
+                timing->reg_100224 = (tUNK_0 + tUNK_19 + 1 + magic_number) << 24 |
                                       tUNK_18 << 16 |
-                                      (tUNK_1 + tUNK_19 + 1) << 8 |
-                                      (tUNK_2 - 1));
+                                      (tUNK_1 + tUNK_19 + 1 + magic_number) << 8;
+                if(dev_priv->chipset == 0xa8) {
+                        timing->reg_100224 |= (tUNK_2 - 1);
+                } else {
+                        timing->reg_100224 |= (tUNK_2 + 2 - magic_number);
+                }
 
                 timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10);
-                if(recordlen > 19) {
-                        timing->reg_100228 += (tUNK_19 - 1) << 24;
-                }/* I cannot back-up this else-statement right now
-                         else {
-                        timing->reg_100228 += tUNK_12 << 24;
-                }*/
-
-                /* XXX: reg_10022c */
-                timing->reg_10022c = tUNK_2 - 1;
-
-                timing->reg_100230 = (tUNK_20 << 24 | tUNK_21 << 16 |
-                                      tUNK_13 << 8  | tUNK_13);
-
-                /* XXX: +6? */
-                timing->reg_100234 = (tRAS << 24 | (tUNK_19 + 6) << 8 | tRC);
-                timing->reg_100234 += max(tUNK_10,tUNK_11) << 16;
-
-                /* XXX; reg_100238, reg_10023c
-                 * reg: 0x00??????
-                 * reg_10023c:
-                 *      0 for pre-NV50 cards
-                 *      0x????0202 for NV50+ cards (empirical evidence) */
-                if(dev_priv->card_type >= NV_50) {
+                if(dev_priv->chipset >= 0xa3 && dev_priv->chipset < 0xaa) {
+                        timing->reg_100228 |= (tUNK_19 - 1) << 24;
+                }
+
+                if(dev_priv->card_type == NV_40) {
+                        /* NV40: don't know what the rest of the regs are..
+                         * And don't need to know either */
+                        timing->reg_100228 |= 0x20200000 | magic_number << 24;
+                } else if(dev_priv->card_type >= NV_50) {
+                        /* XXX: reg_10022c */
+                        timing->reg_10022c = tUNK_2 - 1;
+
+                        timing->reg_100230 = (tUNK_20 << 24 | tUNK_21 << 16 |
+                                                  tUNK_13 << 8  | tUNK_13);
+
+                        timing->reg_100234 = (tRAS << 24 | tRC);
+                        timing->reg_100234 += max(tUNK_10,tUNK_11) << 16;
+
+                        if(dev_priv->chipset < 0xa3) {
+                                timing->reg_100234 |= (tUNK_2 + 2) << 8;
+                        } else {
+                                /* XXX: +6? */
+                                timing->reg_100234 |= (tUNK_19 + 6) << 8;
+                        }
+
+                        /* XXX; reg_100238, reg_10023c
+                         * reg_100238: 0x00??????
+                         * reg_10023c: 0x!!??0202 for NV50+ cards (empirical evidence) */
                         timing->reg_10023c = 0x202;
+                        if(dev_priv->chipset < 0xa3) {
+                                timing->reg_10023c |= 0x4000000 | (tUNK_2 - 1) << 16;
+                        } else {
+                                /* currently unknown
+                                 * 10023c seen as 06xxxxxx, 0bxxxxxx or 0fxxxxxx */
+                        }
                 }
 
                 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", i,
@@ -675,7 +697,7 @@ nouveau_mem_timing_init(struct drm_device *dev)
                          timing->reg_100238, timing->reg_10023c);
         }
 
-        memtimings->nr_timing  = entries;
+        memtimings->nr_timing = entries;
         memtimings->supported = true;
 }
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_perf.c b/drivers/gpu/drm/nouveau/nouveau_perf.c
index ac62a1b8c4fc..670e3cb697ec 100644
--- a/drivers/gpu/drm/nouveau/nouveau_perf.c
+++ b/drivers/gpu/drm/nouveau/nouveau_perf.c
@@ -134,7 +134,7 @@ nouveau_perf_init(struct drm_device *dev)
                 case 0x13:
                 case 0x15:
                         perflvl->fanspeed = entry[55];
-                        perflvl->voltage = entry[56];
+                        perflvl->voltage = (recordlen > 56) ? entry[56] : 0;
                         perflvl->core = ROM32(entry[1]) * 10;
                         perflvl->memory = ROM32(entry[5]) * 20;
                         break;
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 5bb2859001e2..6e2b1a6caa2d 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -376,15 +376,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
                 engine->graph.destroy_context   = nv50_graph_destroy_context;
                 engine->graph.load_context      = nv50_graph_load_context;
                 engine->graph.unload_context    = nv50_graph_unload_context;
-                if (dev_priv->chipset != 0x86)
+                if (dev_priv->chipset == 0x50 ||
+                    dev_priv->chipset == 0xac)
                         engine->graph.tlb_flush = nv50_graph_tlb_flush;
-                else {
-                        /* from what i can see nvidia do this on every
-                         * pre-NVA3 board except NVAC, but, we've only
-                         * ever seen problems on NV86
-                         */
-                        engine->graph.tlb_flush = nv86_graph_tlb_flush;
-                }
+                else
+                        engine->graph.tlb_flush = nv84_graph_tlb_flush;
                 engine->fifo.channels           = 128;
                 engine->fifo.init               = nv50_fifo_init;
                 engine->fifo.takedown           = nv50_fifo_takedown;
diff --git a/drivers/gpu/drm/nouveau/nv04_dfp.c b/drivers/gpu/drm/nouveau/nv04_dfp.c
index c82db37d9f41..12098bf839c4 100644
--- a/drivers/gpu/drm/nouveau/nv04_dfp.c
+++ b/drivers/gpu/drm/nouveau/nv04_dfp.c
@@ -581,12 +581,13 @@ static void nv04_dfp_restore(struct drm_encoder *encoder)
         int head = nv_encoder->restore.head;
 
         if (nv_encoder->dcb->type == OUTPUT_LVDS) {
-                struct drm_display_mode *native_mode = nouveau_encoder_connector_get(nv_encoder)->native_mode;
-                if (native_mode)
-                        call_lvds_script(dev, nv_encoder->dcb, head, LVDS_PANEL_ON,
-                                         native_mode->clock);
-                else
-                        NV_ERROR(dev, "Not restoring LVDS without native mode\n");
+                struct nouveau_connector *connector =
+                        nouveau_encoder_connector_get(nv_encoder);
+
+                if (connector && connector->native_mode)
+                        call_lvds_script(dev, nv_encoder->dcb, head,
+                                         LVDS_PANEL_ON,
+                                         connector->native_mode->clock);
 
         } else if (nv_encoder->dcb->type == OUTPUT_TMDS) {
                 int clock = nouveau_hw_pllvals_to_clk
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c
index 2b9984027f41..a19ccaa025b3 100644
--- a/drivers/gpu/drm/nouveau/nv50_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c
@@ -469,9 +469,6 @@ nv50_crtc_wait_complete(struct drm_crtc *crtc)
 
         start = ptimer->read(dev);
         do {
-                nv_wr32(dev, 0x61002c, 0x370);
-                nv_wr32(dev, 0x000140, 1);
-
                 if (nv_ro32(disp->ntfy, 0x000))
                         return 0;
         } while (ptimer->read(dev) - start < 2000000000ULL);
diff --git a/drivers/gpu/drm/nouveau/nv50_evo.c b/drivers/gpu/drm/nouveau/nv50_evo.c
index a2cfaa691e9b..c8e83c1a4de8 100644
--- a/drivers/gpu/drm/nouveau/nv50_evo.c
+++ b/drivers/gpu/drm/nouveau/nv50_evo.c
@@ -186,6 +186,7 @@ nv50_evo_channel_init(struct nouveau_channel *evo)
         nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << id);
 
         evo->dma.max = (4096/4) - 2;
+        evo->dma.max &= ~7;
         evo->dma.put = 0;
         evo->dma.cur = evo->dma.put;
         evo->dma.free = evo->dma.max - evo->dma.cur;
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c
index 8675b00caf18..b02a5b1e7d37 100644
--- a/drivers/gpu/drm/nouveau/nv50_graph.c
+++ b/drivers/gpu/drm/nouveau/nv50_graph.c
@@ -503,7 +503,7 @@ nv50_graph_tlb_flush(struct drm_device *dev)
 }
 
 void
-nv86_graph_tlb_flush(struct drm_device *dev)
+nv84_graph_tlb_flush(struct drm_device *dev)
 {
         struct drm_nouveau_private *dev_priv = dev->dev_private;
         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
diff --git a/drivers/gpu/drm/nouveau/nvc0_vm.c b/drivers/gpu/drm/nouveau/nvc0_vm.c
index 69af0ba7edd3..a0a2a0277f73 100644
--- a/drivers/gpu/drm/nouveau/nvc0_vm.c
+++ b/drivers/gpu/drm/nouveau/nvc0_vm.c
@@ -104,20 +104,26 @@ nvc0_vm_flush(struct nouveau_vm *vm)
         struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
         struct drm_device *dev = vm->dev;
         struct nouveau_vm_pgd *vpgd;
-        u32 r100c80, engine;
+        u32 engine = (dev_priv->chan_vm == vm) ? 1 : 5;
 
         pinstmem->flush(vm->dev);
 
-        if (vm == dev_priv->chan_vm)
-                engine = 1;
-        else
-                engine = 5;
-
+        spin_lock(&dev_priv->ramin_lock);
         list_for_each_entry(vpgd, &vm->pgd_list, head) {
-                r100c80 = nv_rd32(dev, 0x100c80);
+                /* looks like maybe a "free flush slots" counter, the
+                 * faster you write to 0x100cbc to more it decreases
+                 */
+                if (!nv_wait_ne(dev, 0x100c80, 0x00ff0000, 0x00000000)) {
+                        NV_ERROR(dev, "vm timeout 0: 0x%08x %d\n",
+                                 nv_rd32(dev, 0x100c80), engine);
+                }
                 nv_wr32(dev, 0x100cb8, vpgd->obj->vinst >> 8);
                 nv_wr32(dev, 0x100cbc, 0x80000000 | engine);
-                if (!nv_wait(dev, 0x100c80, 0xffffffff, r100c80))
-                        NV_ERROR(dev, "vm flush timeout eng %d\n", engine);
+                /* wait for flush to be queued? */
+                if (!nv_wait(dev, 0x100c80, 0x00008000, 0x00008000)) {
+                        NV_ERROR(dev, "vm timeout 1: 0x%08x %d\n",
+                                 nv_rd32(dev, 0x100c80), engine);
+                }
         }
+        spin_unlock(&dev_priv->ramin_lock);
 }