drm/radeon/kms: rework texture cache flush in r6xx+ blit code

Move the TC flush before the texture setup to match mesa and
the ddx. Also, move the TC flush into the texture setup
function.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

3 files changed, 10 insertions, 7 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
index dcf11bbc06d9..879f7335029e 100644
--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
@@ -174,7 +174,7 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
 static void
 set_tex_resource(struct radeon_device *rdev,
                  int format, int w, int h, int pitch,
-                 u64 gpu_addr)
+                 u64 gpu_addr, u32 size)
 {
         u32 sq_tex_resource_word0, sq_tex_resource_word1;
         u32 sq_tex_resource_word4, sq_tex_resource_word7;
@@ -196,6 +196,9 @@ set_tex_resource(struct radeon_device *rdev,
         sq_tex_resource_word7 = format |
                 S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_TEXTURE);
 
+        cp_set_surface_sync(rdev,
+                            PACKET3_TC_ACTION_ENA, size, gpu_addr);
+
         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
         radeon_ring_write(rdev, 0);
         radeon_ring_write(rdev, sq_tex_resource_word0);
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index c4cf1308d4a1..ff36532734b7 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -201,7 +201,7 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
 static void
 set_tex_resource(struct radeon_device *rdev,
                  int format, int w, int h, int pitch,
-                 u64 gpu_addr)
+                 u64 gpu_addr, u32 size)
 {
         uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
 
@@ -222,6 +222,9 @@ set_tex_resource(struct radeon_device *rdev,
                 S_038010_DST_SEL_Z(SQ_SEL_Z) |
                 S_038010_DST_SEL_W(SQ_SEL_W);
 
+        cp_set_surface_sync(rdev,
+                            PACKET3_TC_ACTION_ENA, size, gpu_addr);
+
         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
         radeon_ring_write(rdev, 0);
         radeon_ring_write(rdev, sq_tex_resource_word0);
@@ -760,10 +763,7 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
                 vb[11] = i2f(h);
 
                 rdev->r600_blit.primitives.set_tex_resource(rdev, FMT_8_8_8_8,
-                                                            w, h, w, src_gpu_addr);
-                rdev->r600_blit.primitives.cp_set_surface_sync(rdev,
-                                                               PACKET3_TC_ACTION_ENA,
-                                                               size_in_bytes, src_gpu_addr);
+                                                            w, h, w, src_gpu_addr, size_in_bytes);
                 rdev->r600_blit.primitives.set_render_target(rdev, COLOR_8_8_8_8,
                                                              w, h, dst_gpu_addr);
                 rdev->r600_blit.primitives.set_scissors(rdev, 0, 0, w, h);
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index e3170c794c1d..3a78f8666fa7 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -533,7 +533,7 @@ struct r600_blit_cp_primitives {
         void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
         void (*set_tex_resource)(struct radeon_device *rdev,
                                  int format, int w, int h, int pitch,
-                                 u64 gpu_addr);
+                                 u64 gpu_addr, u32 size);
         void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
                              int x2, int y2);
         void (*draw_auto)(struct radeon_device *rdev);