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authorJesse Barnes <jbarnes@virtuousgeek.org>2009-07-22 15:54:59 -0400
committerEric Anholt <eric@anholt.net>2009-07-29 18:17:28 -0400
commitf360132626b11d0dc60814033873ca0e3111677c (patch)
tree151ce60f5d0ff41342a772b9361f06c12d8e1720 /drivers/gpu
parent67941da28d59cca6817d35823fcb1e3e4eed030e (diff)
drm/i915: fix 845G FIFO size & burst length
I had one report of flicker due to FIFO underruns on 845G. Scott was kind enough to test a few patches and report success with this one. Looks like 845G measures FIFO size slightly differently than other chips, and we were also clobbering the FIFO burst length. Fixing both of those issues gives him a healthy machine again. Note that we still only adjust plane A's watermark in the 830/845 case. If someone is willing to test we could support a bigger variety of dual-head 830/845 configurations with a bit more code. Fixes fdo bug #19304 (again). Reported-by: Scott Hansen <scottandchrystie@comcast.net> Tested-by: Scott Hansen <scottandchrystie@comcast.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a9f1307d32d8..1da7b0b9ed31 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2026,6 +2026,9 @@ static int intel_get_fifo_size(struct drm_device *dev, int plane)
2026 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - 2026 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2027 (dsparb & 0x1ff); 2027 (dsparb & 0x1ff);
2028 size >>= 1; /* Convert to cachelines */ 2028 size >>= 1; /* Convert to cachelines */
2029 } else if (IS_845G(dev)) {
2030 size = dsparb & 0x7f;
2031 size >>= 2; /* Convert to cachelines */
2029 } else { 2032 } else {
2030 size = dsparb & 0x7f; 2033 size = dsparb & 0x7f;
2031 size >>= 1; /* Convert to cachelines */ 2034 size >>= 1; /* Convert to cachelines */
@@ -2125,14 +2128,16 @@ static void i830_update_wm(struct drm_device *dev, int planea_clock,
2125 int pixel_size) 2128 int pixel_size)
2126{ 2129{
2127 struct drm_i915_private *dev_priv = dev->dev_private; 2130 struct drm_i915_private *dev_priv = dev->dev_private;
2128 uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK; 2131 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2129 int planea_wm; 2132 int planea_wm;
2130 2133
2131 i830_wm_info.fifo_size = intel_get_fifo_size(dev, 0); 2134 i830_wm_info.fifo_size = intel_get_fifo_size(dev, 0);
2132 2135
2133 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info, 2136 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2134 pixel_size, latency_ns); 2137 pixel_size, latency_ns);
2135 fwater_lo = fwater_lo | planea_wm; 2138 fwater_lo |= (3<<8) | planea_wm;
2139
2140 DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
2136 2141
2137 I915_WRITE(FW_BLC, fwater_lo); 2142 I915_WRITE(FW_BLC, fwater_lo);
2138} 2143}