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authorAlex Deucher <alexdeucher@gmail.com>2011-05-03 19:28:02 -0400
committerDave Airlie <airlied@redhat.com>2011-05-03 20:16:40 -0400
commit8aeb96f80232e9a701b5c4715504f4c9173978bd (patch)
tree59852e4f90221689eef0ed0ae8b7ff51e598b90a /drivers/gpu
parent498548ec69c6897fe4376b2ca90758762fa0b817 (diff)
drm/radeon/kms: fix gart setup on fusion parts (v2)
Out of the entire GART/VM subsystem, the hw designers changed the location of 3 regs. v2: airlied: add parameter for userspace to work from. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c17
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h5
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c3
3 files changed, 17 insertions, 8 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index e9bc135d9189..c20eac3379e6 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -862,9 +862,15 @@ int evergreen_pcie_gart_enable(struct radeon_device *rdev)
862 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 862 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
863 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 863 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
864 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 864 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
865 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 865 if (rdev->flags & RADEON_IS_IGP) {
866 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 866 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
867 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 867 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
868 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
869 } else {
870 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
871 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
872 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
873 }
868 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 874 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
869 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 875 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
870 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 876 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
@@ -2923,11 +2929,6 @@ static int evergreen_startup(struct radeon_device *rdev)
2923 rdev->asic->copy = NULL; 2929 rdev->asic->copy = NULL;
2924 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 2930 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2925 } 2931 }
2926 /* XXX: ontario has problems blitting to gart at the moment */
2927 if (rdev->family == CHIP_PALM) {
2928 rdev->asic->copy = NULL;
2929 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2930 }
2931 2932
2932 /* allocate wb buffer */ 2933 /* allocate wb buffer */
2933 r = radeon_wb_init(rdev); 2934 r = radeon_wb_init(rdev);
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 9aaa3f0c9372..94533849927e 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -221,6 +221,11 @@
221#define MC_VM_MD_L1_TLB0_CNTL 0x2654 221#define MC_VM_MD_L1_TLB0_CNTL 0x2654
222#define MC_VM_MD_L1_TLB1_CNTL 0x2658 222#define MC_VM_MD_L1_TLB1_CNTL 0x2658
223#define MC_VM_MD_L1_TLB2_CNTL 0x265C 223#define MC_VM_MD_L1_TLB2_CNTL 0x265C
224
225#define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C
226#define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660
227#define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664
228
224#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 229#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
225#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 230#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
226#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 231#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 871df0376b1c..bd58af658581 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -234,6 +234,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
234 return -EINVAL; 234 return -EINVAL;
235 } 235 }
236 break; 236 break;
237 case RADEON_INFO_FUSION_GART_WORKING:
238 value = 1;
239 break;
237 default: 240 default:
238 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 241 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
239 return -EINVAL; 242 return -EINVAL;