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authorDaniel Vetter <daniel.vetter@ffwll.ch>2010-02-11 08:14:43 -0500
committerEric Anholt <eric@anholt.net>2010-02-22 11:54:40 -0500
commit4f8a567c4666c73284832240db89fdadb2c50bd5 (patch)
treebbed0451e99c316293ac88f0f006188ad8a341ec /drivers/gpu
parent4667a4a52ffc3789c45f46096cdffb053591a8e1 (diff)
drm/i915: overlay: drop superflous gpu flushes
Cache-coherency is maintained by gem. Drop these leftover MI_FLUSH commands from the userspace code. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/intel_overlay.c20
1 files changed, 5 insertions, 15 deletions
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 1257dc3cb474..f3086fd4773f 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -220,9 +220,7 @@ static int intel_overlay_on(struct intel_overlay *overlay)
220 overlay->active = 1; 220 overlay->active = 1;
221 overlay->hw_wedged = NEEDS_WAIT_FOR_FLIP; 221 overlay->hw_wedged = NEEDS_WAIT_FOR_FLIP;
222 222
223 BEGIN_LP_RING(6); 223 BEGIN_LP_RING(4);
224 OUT_RING(MI_FLUSH);
225 OUT_RING(MI_NOOP);
226 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON); 224 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
227 OUT_RING(overlay->flip_addr | OFC_UPDATE); 225 OUT_RING(overlay->flip_addr | OFC_UPDATE);
228 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); 226 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
@@ -262,9 +260,7 @@ static void intel_overlay_continue(struct intel_overlay *overlay,
262 if (tmp & (1 << 17)) 260 if (tmp & (1 << 17))
263 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp); 261 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
264 262
265 BEGIN_LP_RING(4); 263 BEGIN_LP_RING(2);
266 OUT_RING(MI_FLUSH);
267 OUT_RING(MI_NOOP);
268 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE); 264 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
269 OUT_RING(flip_addr); 265 OUT_RING(flip_addr);
270 ADVANCE_LP_RING(); 266 ADVANCE_LP_RING();
@@ -333,9 +329,7 @@ static int intel_overlay_off(struct intel_overlay *overlay)
333 /* wait for overlay to go idle */ 329 /* wait for overlay to go idle */
334 overlay->hw_wedged = SWITCH_OFF_STAGE_1; 330 overlay->hw_wedged = SWITCH_OFF_STAGE_1;
335 331
336 BEGIN_LP_RING(6); 332 BEGIN_LP_RING(4);
337 OUT_RING(MI_FLUSH);
338 OUT_RING(MI_NOOP);
339 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE); 333 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
340 OUT_RING(flip_addr); 334 OUT_RING(flip_addr);
341 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); 335 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
@@ -353,9 +347,7 @@ static int intel_overlay_off(struct intel_overlay *overlay)
353 /* turn overlay off */ 347 /* turn overlay off */
354 overlay->hw_wedged = SWITCH_OFF_STAGE_2; 348 overlay->hw_wedged = SWITCH_OFF_STAGE_2;
355 349
356 BEGIN_LP_RING(6); 350 BEGIN_LP_RING(4);
357 OUT_RING(MI_FLUSH);
358 OUT_RING(MI_NOOP);
359 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF); 351 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
360 OUT_RING(flip_addr); 352 OUT_RING(flip_addr);
361 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); 353 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
@@ -430,9 +422,7 @@ int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
430 422
431 overlay->hw_wedged = SWITCH_OFF_STAGE_2; 423 overlay->hw_wedged = SWITCH_OFF_STAGE_2;
432 424
433 BEGIN_LP_RING(6); 425 BEGIN_LP_RING(4);
434 OUT_RING(MI_FLUSH);
435 OUT_RING(MI_NOOP);
436 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF); 426 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
437 OUT_RING(flip_addr); 427 OUT_RING(flip_addr);
438 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); 428 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);