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authorLinus Torvalds <torvalds@linux-foundation.org>2011-08-15 22:14:18 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-08-15 22:14:18 -0400
commit291b63c86aea8a571ddf913d41ab5156b8314dad (patch)
tree6820ee79cde6a1ffd6a82cd265de826ff17f8732 /drivers/gpu
parentcedf03bd9aa54d1d7a9065dddc9e76505f476b12 (diff)
parent92b79f4322b8a2506bdd862f554a2a81ff0a2dad (diff)
Merge branch 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/keithp/linux-2.6
* 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/keithp/linux-2.6: drm/i915: Cannot set clock gating under UMS drm/i915: Can't do accurate vblank timestamps with UMS Not all systems expose a firmware or platform mechanism for changing the backlight intensity on i915, so add native driver support. drm/i915: split out PCH refclk update code drm/i915: show interrupt info on IVB drm/i915: Remove unused 'reg' argument to dp_pipe_enabled drm/i915: Fix PCH port pipe select in CPT disable paths drm/i915: Leave LVDS registers unlocked drm/i915: Wait for LVDS panel power sequence
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c2
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h4
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c6
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h13
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c3
-rw-r--r--drivers/gpu/drm/i915/intel_display.c187
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c7
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h3
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c82
-rw-r--r--drivers/gpu/drm/i915/intel_opregion.c1
-rw-r--r--drivers/gpu/drm/i915/intel_panel.c72
11 files changed, 264 insertions, 116 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a8ab6263e0d7..3c395a59da35 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -499,7 +499,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
499 seq_printf(m, "Interrupts received: %d\n", 499 seq_printf(m, "Interrupts received: %d\n",
500 atomic_read(&dev_priv->irq_received)); 500 atomic_read(&dev_priv->irq_received));
501 for (i = 0; i < I915_NUM_RINGS; i++) { 501 for (i = 0; i < I915_NUM_RINGS; i++) {
502 if (IS_GEN6(dev)) { 502 if (IS_GEN6(dev) || IS_GEN7(dev)) {
503 seq_printf(m, "Graphics Interrupt mask (%s): %08x\n", 503 seq_printf(m, "Graphics Interrupt mask (%s): %08x\n",
504 dev_priv->ring[i].name, 504 dev_priv->ring[i].name,
505 I915_READ_IMR(&dev_priv->ring[i])); 505 I915_READ_IMR(&dev_priv->ring[i]));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index feb4f164fd1b..7916bd97d5c1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -36,6 +36,7 @@
36#include <linux/io-mapping.h> 36#include <linux/io-mapping.h>
37#include <linux/i2c.h> 37#include <linux/i2c.h>
38#include <drm/intel-gtt.h> 38#include <drm/intel-gtt.h>
39#include <linux/backlight.h>
39 40
40/* General customization: 41/* General customization:
41 */ 42 */
@@ -690,6 +691,7 @@ typedef struct drm_i915_private {
690 int child_dev_num; 691 int child_dev_num;
691 struct child_device_config *child_dev; 692 struct child_device_config *child_dev;
692 struct drm_connector *int_lvds_connector; 693 struct drm_connector *int_lvds_connector;
694 struct drm_connector *int_edp_connector;
693 695
694 bool mchbar_need_disable; 696 bool mchbar_need_disable;
695 697
@@ -723,6 +725,8 @@ typedef struct drm_i915_private {
723 /* list of fbdev register on this device */ 725 /* list of fbdev register on this device */
724 struct intel_fbdev *fbdev; 726 struct intel_fbdev *fbdev;
725 727
728 struct backlight_device *backlight;
729
726 struct drm_property *broadcast_rgb_property; 730 struct drm_property *broadcast_rgb_property;
727 struct drm_property *force_audio_property; 731 struct drm_property *force_audio_property;
728 732
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 02f96fd0d52d..9cbb0cd8f46a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2058,8 +2058,10 @@ void intel_irq_init(struct drm_device *dev)
2058 dev->driver->get_vblank_counter = gm45_get_vblank_counter; 2058 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2059 } 2059 }
2060 2060
2061 2061 if (drm_core_check_feature(dev, DRIVER_MODESET))
2062 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; 2062 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2063 else
2064 dev->driver->get_vblank_timestamp = NULL;
2063 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; 2065 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2064 2066
2065 if (IS_IVYBRIDGE(dev)) { 2067 if (IS_IVYBRIDGE(dev)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d1331f771e2f..5baaef4a0c5d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1318,6 +1318,7 @@
1318#define ADPA_PIPE_SELECT_MASK (1<<30) 1318#define ADPA_PIPE_SELECT_MASK (1<<30)
1319#define ADPA_PIPE_A_SELECT 0 1319#define ADPA_PIPE_A_SELECT 0
1320#define ADPA_PIPE_B_SELECT (1<<30) 1320#define ADPA_PIPE_B_SELECT (1<<30)
1321#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
1321#define ADPA_USE_VGA_HVPOLARITY (1<<15) 1322#define ADPA_USE_VGA_HVPOLARITY (1<<15)
1322#define ADPA_SETS_HVPOLARITY 0 1323#define ADPA_SETS_HVPOLARITY 0
1323#define ADPA_VSYNC_CNTL_DISABLE (1<<11) 1324#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
@@ -1460,6 +1461,7 @@
1460/* Selects pipe B for LVDS data. Must be set on pre-965. */ 1461/* Selects pipe B for LVDS data. Must be set on pre-965. */
1461#define LVDS_PIPEB_SELECT (1 << 30) 1462#define LVDS_PIPEB_SELECT (1 << 30)
1462#define LVDS_PIPE_MASK (1 << 30) 1463#define LVDS_PIPE_MASK (1 << 30)
1464#define LVDS_PIPE(pipe) ((pipe) << 30)
1463/* LVDS dithering flag on 965/g4x platform */ 1465/* LVDS dithering flag on 965/g4x platform */
1464#define LVDS_ENABLE_DITHER (1 << 25) 1466#define LVDS_ENABLE_DITHER (1 << 25)
1465/* LVDS sync polarity flags. Set to invert (i.e. negative) */ 1467/* LVDS sync polarity flags. Set to invert (i.e. negative) */
@@ -1499,9 +1501,6 @@
1499#define LVDS_B0B3_POWER_DOWN (0 << 2) 1501#define LVDS_B0B3_POWER_DOWN (0 << 2)
1500#define LVDS_B0B3_POWER_UP (3 << 2) 1502#define LVDS_B0B3_POWER_UP (3 << 2)
1501 1503
1502#define LVDS_PIPE_ENABLED(V, P) \
1503 (((V) & (LVDS_PIPE_MASK | LVDS_PORT_EN)) == ((P) << 30 | LVDS_PORT_EN))
1504
1505/* Video Data Island Packet control */ 1504/* Video Data Island Packet control */
1506#define VIDEO_DIP_DATA 0x61178 1505#define VIDEO_DIP_DATA 0x61178
1507#define VIDEO_DIP_CTL 0x61170 1506#define VIDEO_DIP_CTL 0x61170
@@ -3256,14 +3255,12 @@
3256#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 3255#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
3257#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 3256#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
3258 3257
3259#define ADPA_PIPE_ENABLED(V, P) \
3260 (((V) & (ADPA_TRANS_SELECT_MASK | ADPA_DAC_ENABLE)) == ((P) << 30 | ADPA_DAC_ENABLE))
3261
3262/* or SDVOB */ 3258/* or SDVOB */
3263#define HDMIB 0xe1140 3259#define HDMIB 0xe1140
3264#define PORT_ENABLE (1 << 31) 3260#define PORT_ENABLE (1 << 31)
3265#define TRANSCODER_A (0) 3261#define TRANSCODER_A (0)
3266#define TRANSCODER_B (1 << 30) 3262#define TRANSCODER_B (1 << 30)
3263#define TRANSCODER(pipe) ((pipe) << 30)
3267#define TRANSCODER_MASK (1 << 30) 3264#define TRANSCODER_MASK (1 << 30)
3268#define COLOR_FORMAT_8bpc (0) 3265#define COLOR_FORMAT_8bpc (0)
3269#define COLOR_FORMAT_12bpc (3 << 26) 3266#define COLOR_FORMAT_12bpc (3 << 26)
@@ -3280,9 +3277,6 @@
3280#define HSYNC_ACTIVE_HIGH (1 << 3) 3277#define HSYNC_ACTIVE_HIGH (1 << 3)
3281#define PORT_DETECTED (1 << 2) 3278#define PORT_DETECTED (1 << 2)
3282 3279
3283#define HDMI_PIPE_ENABLED(V, P) \
3284 (((V) & (TRANSCODER_MASK | PORT_ENABLE)) == ((P) << 30 | PORT_ENABLE))
3285
3286/* PCH SDVOB multiplex with HDMIB */ 3280/* PCH SDVOB multiplex with HDMIB */
3287#define PCH_SDVOB HDMIB 3281#define PCH_SDVOB HDMIB
3288 3282
@@ -3349,6 +3343,7 @@
3349#define PORT_TRANS_B_SEL_CPT (1<<29) 3343#define PORT_TRANS_B_SEL_CPT (1<<29)
3350#define PORT_TRANS_C_SEL_CPT (2<<29) 3344#define PORT_TRANS_C_SEL_CPT (2<<29)
3351#define PORT_TRANS_SEL_MASK (3<<29) 3345#define PORT_TRANS_SEL_MASK (3<<29)
3346#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
3352 3347
3353#define TRANS_DP_CTL_A 0xe0300 3348#define TRANS_DP_CTL_A 0xe0300
3354#define TRANS_DP_CTL_B 0xe1300 3349#define TRANS_DP_CTL_B 0xe1300
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 87677d60d0df..f10742359ec9 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -871,7 +871,8 @@ int i915_restore_state(struct drm_device *dev)
871 } 871 }
872 mutex_unlock(&dev->struct_mutex); 872 mutex_unlock(&dev->struct_mutex);
873 873
874 intel_init_clock_gating(dev); 874 if (drm_core_check_feature(dev, DRIVER_MODESET))
875 intel_init_clock_gating(dev);
875 876
876 if (IS_IRONLAKE_M(dev)) { 877 if (IS_IRONLAKE_M(dev)) {
877 ironlake_enable_drps(dev); 878 ironlake_enable_drps(dev);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 35364e68a091..ee1d701317f7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -980,8 +980,8 @@ static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
980 pipe_name(pipe)); 980 pipe_name(pipe));
981} 981}
982 982
983static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, enum pipe pipe, 983static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
984 int reg, u32 port_sel, u32 val) 984 enum pipe pipe, u32 port_sel, u32 val)
985{ 985{
986 if ((val & DP_PORT_EN) == 0) 986 if ((val & DP_PORT_EN) == 0)
987 return false; 987 return false;
@@ -998,11 +998,58 @@ static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, enum pipe pipe,
998 return true; 998 return true;
999} 999}
1000 1000
1001static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe, u32 val)
1003{
1004 if ((val & PORT_ENABLE) == 0)
1005 return false;
1006
1007 if (HAS_PCH_CPT(dev_priv->dev)) {
1008 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1009 return false;
1010 } else {
1011 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1012 return false;
1013 }
1014 return true;
1015}
1016
1017static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1018 enum pipe pipe, u32 val)
1019{
1020 if ((val & LVDS_PORT_EN) == 0)
1021 return false;
1022
1023 if (HAS_PCH_CPT(dev_priv->dev)) {
1024 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1025 return false;
1026 } else {
1027 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1028 return false;
1029 }
1030 return true;
1031}
1032
1033static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1034 enum pipe pipe, u32 val)
1035{
1036 if ((val & ADPA_DAC_ENABLE) == 0)
1037 return false;
1038 if (HAS_PCH_CPT(dev_priv->dev)) {
1039 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1040 return false;
1041 } else {
1042 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1043 return false;
1044 }
1045 return true;
1046}
1047
1001static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, 1048static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe, int reg, u32 port_sel) 1049 enum pipe pipe, int reg, u32 port_sel)
1003{ 1050{
1004 u32 val = I915_READ(reg); 1051 u32 val = I915_READ(reg);
1005 WARN(dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val), 1052 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1006 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", 1053 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1007 reg, pipe_name(pipe)); 1054 reg, pipe_name(pipe));
1008} 1055}
@@ -1011,7 +1058,7 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1011 enum pipe pipe, int reg) 1058 enum pipe pipe, int reg)
1012{ 1059{
1013 u32 val = I915_READ(reg); 1060 u32 val = I915_READ(reg);
1014 WARN(HDMI_PIPE_ENABLED(val, pipe), 1061 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1015 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", 1062 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1016 reg, pipe_name(pipe)); 1063 reg, pipe_name(pipe));
1017} 1064}
@@ -1028,13 +1075,13 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1028 1075
1029 reg = PCH_ADPA; 1076 reg = PCH_ADPA;
1030 val = I915_READ(reg); 1077 val = I915_READ(reg);
1031 WARN(ADPA_PIPE_ENABLED(val, pipe), 1078 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1032 "PCH VGA enabled on transcoder %c, should be disabled\n", 1079 "PCH VGA enabled on transcoder %c, should be disabled\n",
1033 pipe_name(pipe)); 1080 pipe_name(pipe));
1034 1081
1035 reg = PCH_LVDS; 1082 reg = PCH_LVDS;
1036 val = I915_READ(reg); 1083 val = I915_READ(reg);
1037 WARN(LVDS_PIPE_ENABLED(val, pipe), 1084 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1038 "PCH LVDS enabled on transcoder %c, should be disabled\n", 1085 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1039 pipe_name(pipe)); 1086 pipe_name(pipe));
1040 1087
@@ -1360,7 +1407,7 @@ static void disable_pch_dp(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, int reg, u32 port_sel) 1407 enum pipe pipe, int reg, u32 port_sel)
1361{ 1408{
1362 u32 val = I915_READ(reg); 1409 u32 val = I915_READ(reg);
1363 if (dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val)) { 1410 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1364 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe); 1411 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1365 I915_WRITE(reg, val & ~DP_PORT_EN); 1412 I915_WRITE(reg, val & ~DP_PORT_EN);
1366 } 1413 }
@@ -1370,7 +1417,7 @@ static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1370 enum pipe pipe, int reg) 1417 enum pipe pipe, int reg)
1371{ 1418{
1372 u32 val = I915_READ(reg); 1419 u32 val = I915_READ(reg);
1373 if (HDMI_PIPE_ENABLED(val, pipe)) { 1420 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1374 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n", 1421 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1375 reg, pipe); 1422 reg, pipe);
1376 I915_WRITE(reg, val & ~PORT_ENABLE); 1423 I915_WRITE(reg, val & ~PORT_ENABLE);
@@ -1392,12 +1439,13 @@ static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1392 1439
1393 reg = PCH_ADPA; 1440 reg = PCH_ADPA;
1394 val = I915_READ(reg); 1441 val = I915_READ(reg);
1395 if (ADPA_PIPE_ENABLED(val, pipe)) 1442 if (adpa_pipe_enabled(dev_priv, val, pipe))
1396 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE); 1443 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1397 1444
1398 reg = PCH_LVDS; 1445 reg = PCH_LVDS;
1399 val = I915_READ(reg); 1446 val = I915_READ(reg);
1400 if (LVDS_PIPE_ENABLED(val, pipe)) { 1447 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1448 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1401 I915_WRITE(reg, val & ~LVDS_PORT_EN); 1449 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1402 POSTING_READ(reg); 1450 POSTING_READ(reg);
1403 udelay(100); 1451 udelay(100);
@@ -5049,6 +5097,81 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5049 return ret; 5097 return ret;
5050} 5098}
5051 5099
5100static void ironlake_update_pch_refclk(struct drm_device *dev)
5101{
5102 struct drm_i915_private *dev_priv = dev->dev_private;
5103 struct drm_mode_config *mode_config = &dev->mode_config;
5104 struct drm_crtc *crtc;
5105 struct intel_encoder *encoder;
5106 struct intel_encoder *has_edp_encoder = NULL;
5107 u32 temp;
5108 bool has_lvds = false;
5109
5110 /* We need to take the global config into account */
5111 list_for_each_entry(crtc, &mode_config->crtc_list, head) {
5112 if (!crtc->enabled)
5113 continue;
5114
5115 list_for_each_entry(encoder, &mode_config->encoder_list,
5116 base.head) {
5117 if (encoder->base.crtc != crtc)
5118 continue;
5119
5120 switch (encoder->type) {
5121 case INTEL_OUTPUT_LVDS:
5122 has_lvds = true;
5123 case INTEL_OUTPUT_EDP:
5124 has_edp_encoder = encoder;
5125 break;
5126 }
5127 }
5128 }
5129
5130 /* Ironlake: try to setup display ref clock before DPLL
5131 * enabling. This is only under driver's control after
5132 * PCH B stepping, previous chipset stepping should be
5133 * ignoring this setting.
5134 */
5135 temp = I915_READ(PCH_DREF_CONTROL);
5136 /* Always enable nonspread source */
5137 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5138 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5139 temp &= ~DREF_SSC_SOURCE_MASK;
5140 temp |= DREF_SSC_SOURCE_ENABLE;
5141 I915_WRITE(PCH_DREF_CONTROL, temp);
5142
5143 POSTING_READ(PCH_DREF_CONTROL);
5144 udelay(200);
5145
5146 if (has_edp_encoder) {
5147 if (intel_panel_use_ssc(dev_priv)) {
5148 temp |= DREF_SSC1_ENABLE;
5149 I915_WRITE(PCH_DREF_CONTROL, temp);
5150
5151 POSTING_READ(PCH_DREF_CONTROL);
5152 udelay(200);
5153 }
5154 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5155
5156 /* Enable CPU source on CPU attached eDP */
5157 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5158 if (intel_panel_use_ssc(dev_priv))
5159 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5160 else
5161 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5162 } else {
5163 /* Enable SSC on PCH eDP if needed */
5164 if (intel_panel_use_ssc(dev_priv)) {
5165 DRM_ERROR("enabling SSC on PCH\n");
5166 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
5167 }
5168 }
5169 I915_WRITE(PCH_DREF_CONTROL, temp);
5170 POSTING_READ(PCH_DREF_CONTROL);
5171 udelay(200);
5172 }
5173}
5174
5052static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 5175static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5053 struct drm_display_mode *mode, 5176 struct drm_display_mode *mode,
5054 struct drm_display_mode *adjusted_mode, 5177 struct drm_display_mode *adjusted_mode,
@@ -5244,49 +5367,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5244 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, 5367 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5245 &m_n); 5368 &m_n);
5246 5369
5247 /* Ironlake: try to setup display ref clock before DPLL 5370 ironlake_update_pch_refclk(dev);
5248 * enabling. This is only under driver's control after
5249 * PCH B stepping, previous chipset stepping should be
5250 * ignoring this setting.
5251 */
5252 temp = I915_READ(PCH_DREF_CONTROL);
5253 /* Always enable nonspread source */
5254 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5255 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5256 temp &= ~DREF_SSC_SOURCE_MASK;
5257 temp |= DREF_SSC_SOURCE_ENABLE;
5258 I915_WRITE(PCH_DREF_CONTROL, temp);
5259
5260 POSTING_READ(PCH_DREF_CONTROL);
5261 udelay(200);
5262
5263 if (has_edp_encoder) {
5264 if (intel_panel_use_ssc(dev_priv)) {
5265 temp |= DREF_SSC1_ENABLE;
5266 I915_WRITE(PCH_DREF_CONTROL, temp);
5267
5268 POSTING_READ(PCH_DREF_CONTROL);
5269 udelay(200);
5270 }
5271 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5272
5273 /* Enable CPU source on CPU attached eDP */
5274 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5275 if (intel_panel_use_ssc(dev_priv))
5276 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5277 else
5278 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5279 } else {
5280 /* Enable SSC on PCH eDP if needed */
5281 if (intel_panel_use_ssc(dev_priv)) {
5282 DRM_ERROR("enabling SSC on PCH\n");
5283 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
5284 }
5285 }
5286 I915_WRITE(PCH_DREF_CONTROL, temp);
5287 POSTING_READ(PCH_DREF_CONTROL);
5288 udelay(200);
5289 }
5290 5371
5291 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; 5372 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5292 if (has_reduced_clock) 5373 if (has_reduced_clock)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0feae908bb37..44fef5e1c490 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1841,6 +1841,11 @@ done:
1841static void 1841static void
1842intel_dp_destroy (struct drm_connector *connector) 1842intel_dp_destroy (struct drm_connector *connector)
1843{ 1843{
1844 struct drm_device *dev = connector->dev;
1845
1846 if (intel_dpd_is_edp(dev))
1847 intel_panel_destroy_backlight(dev);
1848
1844 drm_sysfs_connector_remove(connector); 1849 drm_sysfs_connector_remove(connector);
1845 drm_connector_cleanup(connector); 1850 drm_connector_cleanup(connector);
1846 kfree(connector); 1851 kfree(connector);
@@ -2072,6 +2077,8 @@ intel_dp_init(struct drm_device *dev, int output_reg)
2072 DRM_MODE_TYPE_PREFERRED; 2077 DRM_MODE_TYPE_PREFERRED;
2073 } 2078 }
2074 } 2079 }
2080 dev_priv->int_edp_connector = connector;
2081 intel_panel_setup_backlight(dev);
2075 } 2082 }
2076 2083
2077 intel_dp_add_properties(intel_dp, connector); 2084 intel_dp_add_properties(intel_dp, connector);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7b330e76a435..0b2ee9d39980 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -297,9 +297,10 @@ extern void intel_pch_panel_fitting(struct drm_device *dev,
297extern u32 intel_panel_get_max_backlight(struct drm_device *dev); 297extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
298extern u32 intel_panel_get_backlight(struct drm_device *dev); 298extern u32 intel_panel_get_backlight(struct drm_device *dev);
299extern void intel_panel_set_backlight(struct drm_device *dev, u32 level); 299extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
300extern void intel_panel_setup_backlight(struct drm_device *dev); 300extern int intel_panel_setup_backlight(struct drm_device *dev);
301extern void intel_panel_enable_backlight(struct drm_device *dev); 301extern void intel_panel_enable_backlight(struct drm_device *dev);
302extern void intel_panel_disable_backlight(struct drm_device *dev); 302extern void intel_panel_disable_backlight(struct drm_device *dev);
303extern void intel_panel_destroy_backlight(struct drm_device *dev);
303extern enum drm_connector_status intel_panel_detect(struct drm_device *dev); 304extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
304 305
305extern void intel_crtc_load_lut(struct drm_crtc *crtc); 306extern void intel_crtc_load_lut(struct drm_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 2e8ddfcba40c..31da77f5c051 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -72,14 +72,16 @@ static void intel_lvds_enable(struct intel_lvds *intel_lvds)
72{ 72{
73 struct drm_device *dev = intel_lvds->base.base.dev; 73 struct drm_device *dev = intel_lvds->base.base.dev;
74 struct drm_i915_private *dev_priv = dev->dev_private; 74 struct drm_i915_private *dev_priv = dev->dev_private;
75 u32 ctl_reg, lvds_reg; 75 u32 ctl_reg, lvds_reg, stat_reg;
76 76
77 if (HAS_PCH_SPLIT(dev)) { 77 if (HAS_PCH_SPLIT(dev)) {
78 ctl_reg = PCH_PP_CONTROL; 78 ctl_reg = PCH_PP_CONTROL;
79 lvds_reg = PCH_LVDS; 79 lvds_reg = PCH_LVDS;
80 stat_reg = PCH_PP_STATUS;
80 } else { 81 } else {
81 ctl_reg = PP_CONTROL; 82 ctl_reg = PP_CONTROL;
82 lvds_reg = LVDS; 83 lvds_reg = LVDS;
84 stat_reg = PP_STATUS;
83 } 85 }
84 86
85 I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN); 87 I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN);
@@ -94,17 +96,16 @@ static void intel_lvds_enable(struct intel_lvds *intel_lvds)
94 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n", 96 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
95 intel_lvds->pfit_control, 97 intel_lvds->pfit_control,
96 intel_lvds->pfit_pgm_ratios); 98 intel_lvds->pfit_pgm_ratios);
97 if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000)) { 99
98 DRM_ERROR("timed out waiting for panel to power off\n"); 100 I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios);
99 } else { 101 I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control);
100 I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios); 102 intel_lvds->pfit_dirty = false;
101 I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control);
102 intel_lvds->pfit_dirty = false;
103 }
104 } 103 }
105 104
106 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); 105 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
107 POSTING_READ(lvds_reg); 106 POSTING_READ(lvds_reg);
107 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
108 DRM_ERROR("timed out waiting for panel to power on\n");
108 109
109 intel_panel_enable_backlight(dev); 110 intel_panel_enable_backlight(dev);
110} 111}
@@ -113,24 +114,25 @@ static void intel_lvds_disable(struct intel_lvds *intel_lvds)
113{ 114{
114 struct drm_device *dev = intel_lvds->base.base.dev; 115 struct drm_device *dev = intel_lvds->base.base.dev;
115 struct drm_i915_private *dev_priv = dev->dev_private; 116 struct drm_i915_private *dev_priv = dev->dev_private;
116 u32 ctl_reg, lvds_reg; 117 u32 ctl_reg, lvds_reg, stat_reg;
117 118
118 if (HAS_PCH_SPLIT(dev)) { 119 if (HAS_PCH_SPLIT(dev)) {
119 ctl_reg = PCH_PP_CONTROL; 120 ctl_reg = PCH_PP_CONTROL;
120 lvds_reg = PCH_LVDS; 121 lvds_reg = PCH_LVDS;
122 stat_reg = PCH_PP_STATUS;
121 } else { 123 } else {
122 ctl_reg = PP_CONTROL; 124 ctl_reg = PP_CONTROL;
123 lvds_reg = LVDS; 125 lvds_reg = LVDS;
126 stat_reg = PP_STATUS;
124 } 127 }
125 128
126 intel_panel_disable_backlight(dev); 129 intel_panel_disable_backlight(dev);
127 130
128 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); 131 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
132 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
133 DRM_ERROR("timed out waiting for panel to power off\n");
129 134
130 if (intel_lvds->pfit_control) { 135 if (intel_lvds->pfit_control) {
131 if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000))
132 DRM_ERROR("timed out waiting for panel to power off\n");
133
134 I915_WRITE(PFIT_CONTROL, 0); 136 I915_WRITE(PFIT_CONTROL, 0);
135 intel_lvds->pfit_dirty = true; 137 intel_lvds->pfit_dirty = true;
136 } 138 }
@@ -398,53 +400,21 @@ out:
398 400
399static void intel_lvds_prepare(struct drm_encoder *encoder) 401static void intel_lvds_prepare(struct drm_encoder *encoder)
400{ 402{
401 struct drm_device *dev = encoder->dev;
402 struct drm_i915_private *dev_priv = dev->dev_private;
403 struct intel_lvds *intel_lvds = to_intel_lvds(encoder); 403 struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
404 404
405 /* We try to do the minimum that is necessary in order to unlock 405 /*
406 * the registers for mode setting.
407 *
408 * On Ironlake, this is quite simple as we just set the unlock key
409 * and ignore all subtleties. (This may cause some issues...)
410 *
411 * Prior to Ironlake, we must disable the pipe if we want to adjust 406 * Prior to Ironlake, we must disable the pipe if we want to adjust
412 * the panel fitter. However at all other times we can just reset 407 * the panel fitter. However at all other times we can just reset
413 * the registers regardless. 408 * the registers regardless.
414 */ 409 */
415 410 if (!HAS_PCH_SPLIT(encoder->dev) && intel_lvds->pfit_dirty)
416 if (HAS_PCH_SPLIT(dev)) { 411 intel_lvds_disable(intel_lvds);
417 I915_WRITE(PCH_PP_CONTROL,
418 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
419 } else if (intel_lvds->pfit_dirty) {
420 I915_WRITE(PP_CONTROL,
421 (I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS)
422 & ~POWER_TARGET_ON);
423 } else {
424 I915_WRITE(PP_CONTROL,
425 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
426 }
427} 412}
428 413
429static void intel_lvds_commit(struct drm_encoder *encoder) 414static void intel_lvds_commit(struct drm_encoder *encoder)
430{ 415{
431 struct drm_device *dev = encoder->dev;
432 struct drm_i915_private *dev_priv = dev->dev_private;
433 struct intel_lvds *intel_lvds = to_intel_lvds(encoder); 416 struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
434 417
435 /* Undo any unlocking done in prepare to prevent accidental
436 * adjustment of the registers.
437 */
438 if (HAS_PCH_SPLIT(dev)) {
439 u32 val = I915_READ(PCH_PP_CONTROL);
440 if ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)
441 I915_WRITE(PCH_PP_CONTROL, val & 0x3);
442 } else {
443 u32 val = I915_READ(PP_CONTROL);
444 if ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)
445 I915_WRITE(PP_CONTROL, val & 0x3);
446 }
447
448 /* Always do a full power on as we do not know what state 418 /* Always do a full power on as we do not know what state
449 * we were left in. 419 * we were left in.
450 */ 420 */
@@ -582,6 +552,8 @@ static void intel_lvds_destroy(struct drm_connector *connector)
582 struct drm_device *dev = connector->dev; 552 struct drm_device *dev = connector->dev;
583 struct drm_i915_private *dev_priv = dev->dev_private; 553 struct drm_i915_private *dev_priv = dev->dev_private;
584 554
555 intel_panel_destroy_backlight(dev);
556
585 if (dev_priv->lid_notifier.notifier_call) 557 if (dev_priv->lid_notifier.notifier_call)
586 acpi_lid_notifier_unregister(&dev_priv->lid_notifier); 558 acpi_lid_notifier_unregister(&dev_priv->lid_notifier);
587 drm_sysfs_connector_remove(connector); 559 drm_sysfs_connector_remove(connector);
@@ -1040,6 +1012,19 @@ out:
1040 pwm = I915_READ(BLC_PWM_PCH_CTL1); 1012 pwm = I915_READ(BLC_PWM_PCH_CTL1);
1041 pwm |= PWM_PCH_ENABLE; 1013 pwm |= PWM_PCH_ENABLE;
1042 I915_WRITE(BLC_PWM_PCH_CTL1, pwm); 1014 I915_WRITE(BLC_PWM_PCH_CTL1, pwm);
1015 /*
1016 * Unlock registers and just
1017 * leave them unlocked
1018 */
1019 I915_WRITE(PCH_PP_CONTROL,
1020 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1021 } else {
1022 /*
1023 * Unlock registers and just
1024 * leave them unlocked
1025 */
1026 I915_WRITE(PP_CONTROL,
1027 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
1043 } 1028 }
1044 dev_priv->lid_notifier.notifier_call = intel_lid_notify; 1029 dev_priv->lid_notifier.notifier_call = intel_lid_notify;
1045 if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) { 1030 if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) {
@@ -1049,6 +1034,9 @@ out:
1049 /* keep the LVDS connector */ 1034 /* keep the LVDS connector */
1050 dev_priv->int_lvds_connector = connector; 1035 dev_priv->int_lvds_connector = connector;
1051 drm_sysfs_connector_add(connector); 1036 drm_sysfs_connector_add(connector);
1037
1038 intel_panel_setup_backlight(dev);
1039
1052 return true; 1040 return true;
1053 1041
1054failed: 1042failed:
diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
index b7c5ddb564d1..b8e8158bb16e 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -227,7 +227,6 @@ void intel_opregion_asle_intr(struct drm_device *dev)
227 asle->aslc = asle_stat; 227 asle->aslc = asle_stat;
228} 228}
229 229
230/* Only present on Ironlake+ */
231void intel_opregion_gse_intr(struct drm_device *dev) 230void intel_opregion_gse_intr(struct drm_device *dev)
232{ 231{
233 struct drm_i915_private *dev_priv = dev->dev_private; 232 struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 05f500cd9c24..a9e0c7bcd317 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -277,7 +277,7 @@ void intel_panel_enable_backlight(struct drm_device *dev)
277 dev_priv->backlight_enabled = true; 277 dev_priv->backlight_enabled = true;
278} 278}
279 279
280void intel_panel_setup_backlight(struct drm_device *dev) 280static void intel_panel_init_backlight(struct drm_device *dev)
281{ 281{
282 struct drm_i915_private *dev_priv = dev->dev_private; 282 struct drm_i915_private *dev_priv = dev->dev_private;
283 283
@@ -309,3 +309,73 @@ intel_panel_detect(struct drm_device *dev)
309 309
310 return connector_status_unknown; 310 return connector_status_unknown;
311} 311}
312
313#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
314static int intel_panel_update_status(struct backlight_device *bd)
315{
316 struct drm_device *dev = bl_get_data(bd);
317 intel_panel_set_backlight(dev, bd->props.brightness);
318 return 0;
319}
320
321static int intel_panel_get_brightness(struct backlight_device *bd)
322{
323 struct drm_device *dev = bl_get_data(bd);
324 return intel_panel_get_backlight(dev);
325}
326
327static const struct backlight_ops intel_panel_bl_ops = {
328 .update_status = intel_panel_update_status,
329 .get_brightness = intel_panel_get_brightness,
330};
331
332int intel_panel_setup_backlight(struct drm_device *dev)
333{
334 struct drm_i915_private *dev_priv = dev->dev_private;
335 struct backlight_properties props;
336 struct drm_connector *connector;
337
338 intel_panel_init_backlight(dev);
339
340 if (dev_priv->int_lvds_connector)
341 connector = dev_priv->int_lvds_connector;
342 else if (dev_priv->int_edp_connector)
343 connector = dev_priv->int_edp_connector;
344 else
345 return -ENODEV;
346
347 props.type = BACKLIGHT_RAW;
348 props.max_brightness = intel_panel_get_max_backlight(dev);
349 dev_priv->backlight =
350 backlight_device_register("intel_backlight",
351 &connector->kdev, dev,
352 &intel_panel_bl_ops, &props);
353
354 if (IS_ERR(dev_priv->backlight)) {
355 DRM_ERROR("Failed to register backlight: %ld\n",
356 PTR_ERR(dev_priv->backlight));
357 dev_priv->backlight = NULL;
358 return -ENODEV;
359 }
360 dev_priv->backlight->props.brightness = intel_panel_get_backlight(dev);
361 return 0;
362}
363
364void intel_panel_destroy_backlight(struct drm_device *dev)
365{
366 struct drm_i915_private *dev_priv = dev->dev_private;
367 if (dev_priv->backlight)
368 backlight_device_unregister(dev_priv->backlight);
369}
370#else
371int intel_panel_setup_backlight(struct drm_device *dev)
372{
373 intel_panel_init_backlight(dev);
374 return 0;
375}
376
377void intel_panel_destroy_backlight(struct drm_device *dev)
378{
379 return;
380}
381#endif