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authorZhenyu Wang <zhenyuw@linux.intel.com>2009-11-02 02:52:29 -0500
committerEric Anholt <eric@anholt.net>2009-11-05 17:00:32 -0500
commit4bfe6b6876a036d26a960320f1ab0bbd752c19bf (patch)
treea148753cbfea2eee98989d253b9ca572a7873023 /drivers/gpu
parentba86bf8bfc1add5f515db8cf1d6042bb9396a299 (diff)
drm/i915: Fix and cleanup DPLL calculation for Ironlake
When the ideal error range can't be reached, this will safely use a most closed one. Clean up some dumb codes in DPLL function too. This fixes DPLL clock issue against one monitor at 1680x1050@60hz. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c15
1 files changed, 6 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3ba6546b7c7f..099f420de57a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -863,10 +863,8 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
863 struct drm_device *dev = crtc->dev; 863 struct drm_device *dev = crtc->dev;
864 struct drm_i915_private *dev_priv = dev->dev_private; 864 struct drm_i915_private *dev_priv = dev->dev_private;
865 intel_clock_t clock; 865 intel_clock_t clock;
866 int max_n;
867 bool found;
868 int err_most = 47; 866 int err_most = 47;
869 found = false; 867 int err_min = 10000;
870 868
871 /* eDP has only 2 clock choice, no n/m/p setting */ 869 /* eDP has only 2 clock choice, no n/m/p setting */
872 if (HAS_eDP) 870 if (HAS_eDP)
@@ -890,10 +888,9 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
890 } 888 }
891 889
892 memset(best_clock, 0, sizeof(*best_clock)); 890 memset(best_clock, 0, sizeof(*best_clock));
893 max_n = limit->n.max;
894 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 891 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
895 /* based on hardware requriment prefer smaller n to precision */ 892 /* based on hardware requriment prefer smaller n to precision */
896 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 893 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
897 /* based on hardware requirment prefere larger m1,m2 */ 894 /* based on hardware requirment prefere larger m1,m2 */
898 for (clock.m1 = limit->m1.max; 895 for (clock.m1 = limit->m1.max;
899 clock.m1 >= limit->m1.min; clock.m1--) { 896 clock.m1 >= limit->m1.min; clock.m1--) {
@@ -907,18 +904,18 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
907 this_err = abs((10000 - (target*10000/clock.dot))); 904 this_err = abs((10000 - (target*10000/clock.dot)));
908 if (this_err < err_most) { 905 if (this_err < err_most) {
909 *best_clock = clock; 906 *best_clock = clock;
910 err_most = this_err;
911 max_n = clock.n;
912 found = true;
913 /* found on first matching */ 907 /* found on first matching */
914 goto out; 908 goto out;
909 } else if (this_err < err_min) {
910 *best_clock = clock;
911 err_min = this_err;
915 } 912 }
916 } 913 }
917 } 914 }
918 } 915 }
919 } 916 }
920out: 917out:
921 return found; 918 return true;
922} 919}
923 920
924/* DisplayPort has only two frequencies, 162MHz and 270MHz */ 921/* DisplayPort has only two frequencies, 162MHz and 270MHz */