diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2009-06-06 04:46:02 -0400 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2009-06-09 17:51:18 -0400 |
commit | 21d509e339565c82887733c02465bb7f5866c8f5 (patch) | |
tree | 71ced4feec07b21a43137c3f207cbf1c77e2df4a /drivers/gpu | |
parent | b1ce786cb85280490ca3c29a62ddf8608826b414 (diff) |
drm/i915: use I915_GEM_GPU_DOMAINS
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem.c | 22 |
1 files changed, 9 insertions, 13 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 744bf9803ea3..cf5dc08b6fa8 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c | |||
@@ -989,10 +989,10 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |||
989 | return -ENODEV; | 989 | return -ENODEV; |
990 | 990 | ||
991 | /* Only handle setting domains to types used by the CPU. */ | 991 | /* Only handle setting domains to types used by the CPU. */ |
992 | if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) | 992 | if (write_domain & I915_GEM_GPU_DOMAINS) |
993 | return -EINVAL; | 993 | return -EINVAL; |
994 | 994 | ||
995 | if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) | 995 | if (read_domains & I915_GEM_GPU_DOMAINS) |
996 | return -EINVAL; | 996 | return -EINVAL; |
997 | 997 | ||
998 | /* Having something in the write domain implies it's in the read | 998 | /* Having something in the write domain implies it's in the read |
@@ -1769,8 +1769,7 @@ i915_gem_flush(struct drm_device *dev, | |||
1769 | if (flush_domains & I915_GEM_DOMAIN_CPU) | 1769 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
1770 | drm_agp_chipset_flush(dev); | 1770 | drm_agp_chipset_flush(dev); |
1771 | 1771 | ||
1772 | if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU | | 1772 | if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { |
1773 | I915_GEM_DOMAIN_GTT)) { | ||
1774 | /* | 1773 | /* |
1775 | * read/write caches: | 1774 | * read/write caches: |
1776 | * | 1775 | * |
@@ -2424,8 +2423,8 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) | |||
2424 | * wasn't in the GTT, there shouldn't be any way it could have been in | 2423 | * wasn't in the GTT, there shouldn't be any way it could have been in |
2425 | * a GPU cache | 2424 | * a GPU cache |
2426 | */ | 2425 | */ |
2427 | BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)); | 2426 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2428 | BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)); | 2427 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); |
2429 | 2428 | ||
2430 | return 0; | 2429 | return 0; |
2431 | } | 2430 | } |
@@ -3568,8 +3567,7 @@ i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) | |||
3568 | atomic_inc(&dev->pin_count); | 3567 | atomic_inc(&dev->pin_count); |
3569 | atomic_add(obj->size, &dev->pin_memory); | 3568 | atomic_add(obj->size, &dev->pin_memory); |
3570 | if (!obj_priv->active && | 3569 | if (!obj_priv->active && |
3571 | (obj->write_domain & ~(I915_GEM_DOMAIN_CPU | | 3570 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 && |
3572 | I915_GEM_DOMAIN_GTT)) == 0 && | ||
3573 | !list_empty(&obj_priv->list)) | 3571 | !list_empty(&obj_priv->list)) |
3574 | list_del_init(&obj_priv->list); | 3572 | list_del_init(&obj_priv->list); |
3575 | } | 3573 | } |
@@ -3596,8 +3594,7 @@ i915_gem_object_unpin(struct drm_gem_object *obj) | |||
3596 | */ | 3594 | */ |
3597 | if (obj_priv->pin_count == 0) { | 3595 | if (obj_priv->pin_count == 0) { |
3598 | if (!obj_priv->active && | 3596 | if (!obj_priv->active && |
3599 | (obj->write_domain & ~(I915_GEM_DOMAIN_CPU | | 3597 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
3600 | I915_GEM_DOMAIN_GTT)) == 0) | ||
3601 | list_move_tail(&obj_priv->list, | 3598 | list_move_tail(&obj_priv->list, |
3602 | &dev_priv->mm.inactive_list); | 3599 | &dev_priv->mm.inactive_list); |
3603 | atomic_dec(&dev->pin_count); | 3600 | atomic_dec(&dev->pin_count); |
@@ -3847,9 +3844,8 @@ i915_gem_idle(struct drm_device *dev) | |||
3847 | 3844 | ||
3848 | /* Flush the GPU along with all non-CPU write domains | 3845 | /* Flush the GPU along with all non-CPU write domains |
3849 | */ | 3846 | */ |
3850 | i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT), | 3847 | i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
3851 | ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)); | 3848 | seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS); |
3852 | seqno = i915_add_request(dev, NULL, ~I915_GEM_DOMAIN_CPU); | ||
3853 | 3849 | ||
3854 | if (seqno == 0) { | 3850 | if (seqno == 0) { |
3855 | mutex_unlock(&dev->struct_mutex); | 3851 | mutex_unlock(&dev->struct_mutex); |