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authorChris Wilson <chris@chris-wilson.co.uk>2011-01-12 12:04:08 -0500
committerChris Wilson <chris@chris-wilson.co.uk>2011-01-13 11:05:58 -0500
commita76150302d6e7ebc43e1a1ddaee7fd51db8da3b3 (patch)
tree18237da2f01fa732d5dfc9c567d17209ca6b418c /drivers/gpu
parentc8303e7f3f3093c16ef0fa5f73280637c89d4368 (diff)
drm/i915: Add a module option to override the use of SSC
In order to workaround the issue with LVDS not working on the Lenovo U160 apparently due to using the wrong SSC frequency, add an option to disable SSC. Suggested-by: Lukács, Árpád <lukacs.arpad@gmail.com> Bugzillla: https://bugs.freedesktop.org/show_bug.cgi?id=32748 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c3
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h1
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c17
-rw-r--r--drivers/gpu/drm/i915/intel_display.c17
4 files changed, 21 insertions, 17 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0de75a23f8e7..72fea2bcfc4f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,9 @@ module_param_named(powersave, i915_powersave, int, 0600);
49unsigned int i915_lvds_downclock = 0; 49unsigned int i915_lvds_downclock = 0;
50module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); 50module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
51 51
52unsigned int i915_panel_use_ssc = 1;
53module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
54
52bool i915_try_reset = true; 55bool i915_try_reset = true;
53module_param_named(reset, i915_try_reset, bool, 0600); 56module_param_named(reset, i915_try_reset, bool, 0600);
54 57
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 385fc7ec39d3..5969f46ac2d6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -954,6 +954,7 @@ extern int i915_max_ioctl;
954extern unsigned int i915_fbpercrtc; 954extern unsigned int i915_fbpercrtc;
955extern unsigned int i915_powersave; 955extern unsigned int i915_powersave;
956extern unsigned int i915_lvds_downclock; 956extern unsigned int i915_lvds_downclock;
957extern unsigned int i915_panel_use_ssc;
957 958
958extern int i915_suspend(struct drm_device *dev, pm_message_t state); 959extern int i915_suspend(struct drm_device *dev, pm_message_t state);
959extern int i915_resume(struct drm_device *dev); 960extern int i915_resume(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index b0b1200ed650..0b44956c336b 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -264,17 +264,12 @@ parse_general_features(struct drm_i915_private *dev_priv,
264 dev_priv->int_crt_support = general->int_crt_support; 264 dev_priv->int_crt_support = general->int_crt_support;
265 dev_priv->lvds_use_ssc = general->enable_ssc; 265 dev_priv->lvds_use_ssc = general->enable_ssc;
266 266
267 if (dev_priv->lvds_use_ssc) { 267 if (IS_I85X(dev))
268 if (IS_I85X(dev)) 268 dev_priv->lvds_ssc_freq = general->ssc_freq ? 66 : 48;
269 dev_priv->lvds_ssc_freq = 269 else if (IS_GEN5(dev) || IS_GEN6(dev))
270 general->ssc_freq ? 66 : 48; 270 dev_priv->lvds_ssc_freq = general->ssc_freq ? 100 : 120;
271 else if (IS_GEN5(dev) || IS_GEN6(dev)) 271 else
272 dev_priv->lvds_ssc_freq = 272 dev_priv->lvds_ssc_freq = general->ssc_freq ? 100 : 96;
273 general->ssc_freq ? 100 : 120;
274 else
275 dev_priv->lvds_ssc_freq =
276 general->ssc_freq ? 100 : 96;
277 }
278 } 273 }
279} 274}
280 275
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 25d96889d7d2..98967f3b7724 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3822,6 +3822,11 @@ static void intel_update_watermarks(struct drm_device *dev)
3822 sr_hdisplay, sr_htotal, pixel_size); 3822 sr_hdisplay, sr_htotal, pixel_size);
3823} 3823}
3824 3824
3825static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3826{
3827 return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
3828}
3829
3825static int intel_crtc_mode_set(struct drm_crtc *crtc, 3830static int intel_crtc_mode_set(struct drm_crtc *crtc,
3826 struct drm_display_mode *mode, 3831 struct drm_display_mode *mode,
3827 struct drm_display_mode *adjusted_mode, 3832 struct drm_display_mode *adjusted_mode,
@@ -3884,7 +3889,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3884 num_connectors++; 3889 num_connectors++;
3885 } 3890 }
3886 3891
3887 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) { 3892 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3888 refclk = dev_priv->lvds_ssc_freq * 1000; 3893 refclk = dev_priv->lvds_ssc_freq * 1000;
3889 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", 3894 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3890 refclk / 1000); 3895 refclk / 1000);
@@ -4059,7 +4064,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4059 udelay(200); 4064 udelay(200);
4060 4065
4061 if (has_edp_encoder) { 4066 if (has_edp_encoder) {
4062 if (dev_priv->lvds_use_ssc) { 4067 if (intel_panel_use_ssc(dev_priv)) {
4063 temp |= DREF_SSC1_ENABLE; 4068 temp |= DREF_SSC1_ENABLE;
4064 I915_WRITE(PCH_DREF_CONTROL, temp); 4069 I915_WRITE(PCH_DREF_CONTROL, temp);
4065 4070
@@ -4070,13 +4075,13 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4070 4075
4071 /* Enable CPU source on CPU attached eDP */ 4076 /* Enable CPU source on CPU attached eDP */
4072 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 4077 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4073 if (dev_priv->lvds_use_ssc) 4078 if (intel_panel_use_ssc(dev_priv))
4074 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; 4079 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4075 else 4080 else
4076 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; 4081 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4077 } else { 4082 } else {
4078 /* Enable SSC on PCH eDP if needed */ 4083 /* Enable SSC on PCH eDP if needed */
4079 if (dev_priv->lvds_use_ssc) { 4084 if (intel_panel_use_ssc(dev_priv)) {
4080 DRM_ERROR("enabling SSC on PCH\n"); 4085 DRM_ERROR("enabling SSC on PCH\n");
4081 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE; 4086 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4082 } 4087 }
@@ -4104,7 +4109,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4104 int factor = 21; 4109 int factor = 21;
4105 4110
4106 if (is_lvds) { 4111 if (is_lvds) {
4107 if ((dev_priv->lvds_use_ssc && 4112 if ((intel_panel_use_ssc(dev_priv) &&
4108 dev_priv->lvds_ssc_freq == 100) || 4113 dev_priv->lvds_ssc_freq == 100) ||
4109 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) 4114 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4110 factor = 25; 4115 factor = 25;
@@ -4183,7 +4188,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4183 /* XXX: just matching BIOS for now */ 4188 /* XXX: just matching BIOS for now */
4184 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 4189 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4185 dpll |= 3; 4190 dpll |= 3;
4186 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) 4191 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4187 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 4192 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4188 else 4193 else
4189 dpll |= PLL_REF_INPUT_DREFCLK; 4194 dpll |= PLL_REF_INPUT_DREFCLK;