diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2009-10-15 01:33:35 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2009-10-15 01:33:46 -0400 |
commit | 1b4d7d75ccff38008ccd40f8e2d74e33a087caaa (patch) | |
tree | 115c2aff76fc4805f63c511a41bbf48268ba5c08 /drivers/gpu | |
parent | 8c2a6d730400e14bf28ccfa11b9bbf453db775ec (diff) |
drm/radeon/kms: fix internal tmds setup on legacy display engine
- crtc 0 routing was wrong
- need to clear various timing bits in FP_GEN_CNTL
- need to set FP_H/V2_SYNC_STRT_WID regs for crtc 1
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_legacy_encoders.c | 10 |
2 files changed, 12 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c index d22a195cf152..8d0b7aa87fa4 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c | |||
@@ -668,6 +668,9 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod | |||
668 | 668 | ||
669 | WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); | 669 | WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); |
670 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); | 670 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
671 | |||
672 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid); | ||
673 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid); | ||
671 | } else { | 674 | } else { |
672 | uint32_t crtc_gen_cntl; | 675 | uint32_t crtc_gen_cntl; |
673 | uint32_t crtc_ext_cntl; | 676 | uint32_t crtc_ext_cntl; |
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c index 3a75b5b6009b..00382122869b 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c | |||
@@ -542,6 +542,14 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder, | |||
542 | 542 | ||
543 | fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); | 543 | fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); |
544 | 544 | ||
545 | fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN | | ||
546 | RADEON_FP_DFP_SYNC_SEL | | ||
547 | RADEON_FP_CRT_SYNC_SEL | | ||
548 | RADEON_FP_CRTC_LOCK_8DOT | | ||
549 | RADEON_FP_USE_SHADOW_EN | | ||
550 | RADEON_FP_CRTC_USE_SHADOW_VEND | | ||
551 | RADEON_FP_CRT_SYNC_ALT); | ||
552 | |||
545 | if (1) /* FIXME rgbBits == 8 */ | 553 | if (1) /* FIXME rgbBits == 8 */ |
546 | fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ | 554 | fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ |
547 | else | 555 | else |
@@ -555,7 +563,7 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder, | |||
555 | else | 563 | else |
556 | fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; | 564 | fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; |
557 | } else | 565 | } else |
558 | fp_gen_cntl |= RADEON_FP_SEL_CRTC1; | 566 | fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2; |
559 | } else { | 567 | } else { |
560 | if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { | 568 | if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { |
561 | fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; | 569 | fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; |