diff options
author | Dave Airlie <airlied@redhat.com> | 2015-02-11 00:35:26 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2015-02-11 00:35:26 -0500 |
commit | 85840c76d8ad18d978da44e8d2f27bb35b7159af (patch) | |
tree | c54f837e30c81d4f30aa8eb6c9f6b764734dcd1b /drivers/gpu/ipu-v3 | |
parent | 79a44c16b155b799421f5497ae888985a5d7f80c (diff) | |
parent | a49e7c0d079610062048a4ed1cff2bb09436127c (diff) |
Merge tag 'imx-drm-fixes-2015-01-28' of git://git.pengutronix.de/git/pza/linux into drm-next
imx-drm fixes for IPUv3 DC and i.MX5 IPUv3 IC and TVE
- Corrected handling of wait_for_completion_timeout return value
when disabling IPUv3 DC channels
- Fixed error return value propagation in TVE mode_set
- Fixed IPUv3 register offsets for IC module on i.MX51 and i.MX53
* tag 'imx-drm-fixes-2015-01-28' of git://git.pengutronix.de/git/pza/linux:
gpu: ipu-v3: Fix IC control register offset
drm: imx: imx-tve: Check and propagate the errors
gpu: ipu-v3: wait_for_completion_timeout does not return negative status
Diffstat (limited to 'drivers/gpu/ipu-v3')
-rw-r--r-- | drivers/gpu/ipu-v3/ipu-common.c | 4 | ||||
-rw-r--r-- | drivers/gpu/ipu-v3/ipu-dc.c | 5 |
2 files changed, 5 insertions, 4 deletions
diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c index f707d25ae78f..67bab5c36056 100644 --- a/drivers/gpu/ipu-v3/ipu-common.c +++ b/drivers/gpu/ipu-v3/ipu-common.c | |||
@@ -742,7 +742,7 @@ static struct ipu_devtype ipu_type_imx51 = { | |||
742 | .tpm_ofs = 0x1f060000, | 742 | .tpm_ofs = 0x1f060000, |
743 | .csi0_ofs = 0x1f030000, | 743 | .csi0_ofs = 0x1f030000, |
744 | .csi1_ofs = 0x1f038000, | 744 | .csi1_ofs = 0x1f038000, |
745 | .ic_ofs = 0x1f020000, | 745 | .ic_ofs = 0x1e020000, |
746 | .disp0_ofs = 0x1e040000, | 746 | .disp0_ofs = 0x1e040000, |
747 | .disp1_ofs = 0x1e048000, | 747 | .disp1_ofs = 0x1e048000, |
748 | .dc_tmpl_ofs = 0x1f080000, | 748 | .dc_tmpl_ofs = 0x1f080000, |
@@ -758,7 +758,7 @@ static struct ipu_devtype ipu_type_imx53 = { | |||
758 | .tpm_ofs = 0x07060000, | 758 | .tpm_ofs = 0x07060000, |
759 | .csi0_ofs = 0x07030000, | 759 | .csi0_ofs = 0x07030000, |
760 | .csi1_ofs = 0x07038000, | 760 | .csi1_ofs = 0x07038000, |
761 | .ic_ofs = 0x07020000, | 761 | .ic_ofs = 0x06020000, |
762 | .disp0_ofs = 0x06040000, | 762 | .disp0_ofs = 0x06040000, |
763 | .disp1_ofs = 0x06048000, | 763 | .disp1_ofs = 0x06048000, |
764 | .dc_tmpl_ofs = 0x07080000, | 764 | .dc_tmpl_ofs = 0x07080000, |
diff --git a/drivers/gpu/ipu-v3/ipu-dc.c b/drivers/gpu/ipu-v3/ipu-dc.c index 323203d0503a..4864f8300797 100644 --- a/drivers/gpu/ipu-v3/ipu-dc.c +++ b/drivers/gpu/ipu-v3/ipu-dc.c | |||
@@ -277,7 +277,8 @@ static irqreturn_t dc_irq_handler(int irq, void *dev_id) | |||
277 | void ipu_dc_disable_channel(struct ipu_dc *dc) | 277 | void ipu_dc_disable_channel(struct ipu_dc *dc) |
278 | { | 278 | { |
279 | struct ipu_dc_priv *priv = dc->priv; | 279 | struct ipu_dc_priv *priv = dc->priv; |
280 | int irq, ret; | 280 | int irq; |
281 | unsigned long ret; | ||
281 | u32 val; | 282 | u32 val; |
282 | 283 | ||
283 | /* TODO: Handle MEM_FG_SYNC differently from MEM_BG_SYNC */ | 284 | /* TODO: Handle MEM_FG_SYNC differently from MEM_BG_SYNC */ |
@@ -292,7 +293,7 @@ void ipu_dc_disable_channel(struct ipu_dc *dc) | |||
292 | enable_irq(irq); | 293 | enable_irq(irq); |
293 | ret = wait_for_completion_timeout(&priv->comp, msecs_to_jiffies(50)); | 294 | ret = wait_for_completion_timeout(&priv->comp, msecs_to_jiffies(50)); |
294 | disable_irq(irq); | 295 | disable_irq(irq); |
295 | if (ret <= 0) { | 296 | if (ret == 0) { |
296 | dev_warn(priv->dev, "DC stop timeout after 50 ms\n"); | 297 | dev_warn(priv->dev, "DC stop timeout after 50 ms\n"); |
297 | 298 | ||
298 | val = readl(dc->base + DC_WR_CH_CONF); | 299 | val = readl(dc->base + DC_WR_CH_CONF); |