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authorDave Airlie <airlied@redhat.com>2015-04-13 03:28:57 -0400
committerDave Airlie <airlied@redhat.com>2015-04-13 03:28:57 -0400
commit1d2add28edd268a8290801ccf46b37f6d5239cdb (patch)
tree534e967b692f816434c00de0893e1089d425ae92 /drivers/gpu/ipu-v3
parentbb1dc08c94ead1b98e750caf535422f79363c1a2 (diff)
parent5e501ed7253b369a8a9ec553c35238a3d6808f28 (diff)
Merge tag 'imx-drm-next-2015-03-31' of git://git.pengutronix.de/git/pza/linux into drm-next
imx-drm changes to use media bus formats and LDB drm_panel support - Add media bus formats needed by imx-drm - Switch to use media bus formats to describe the pixel format on the internal parallel bus between display interface and encoders - Some preparations for TV Output via TVEv2 on i.MX5 - Add drm_panel support to the i.MX LVDS driver, allow to determine the bus pixel format from the panel descriptor. * tag 'imx-drm-next-2015-03-31' of git://git.pengutronix.de/git/pza/linux: drm/imx: imx-ldb: allow to determine bus format from the connected panel drm/imx: imx-ldb: reset display clock input when disabling LVDS drm/imx: imx-ldb: add drm_panel support drm/imx: consolidate bus format variable names drm/imx: switch to use media bus formats Add RGB666_1X24_CPADHI media bus format Add YUV8_1X24 media bus format Add BGR888_1X24 and GBR888_1X24 media bus formats Add LVDS RGB media bus formats Add RGB444_1X12 and RGB565_1X16 media bus formats drm/imx: ipuv3-crtc: Allow to divide DI clock from TVEv2 drm/imx: Add support for interlaced scanout
Diffstat (limited to 'drivers/gpu/ipu-v3')
-rw-r--r--drivers/gpu/ipu-v3/ipu-dc.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/ipu-v3/ipu-dc.c b/drivers/gpu/ipu-v3/ipu-dc.c
index 4864f8300797..9ef2e1f54ca4 100644
--- a/drivers/gpu/ipu-v3/ipu-dc.c
+++ b/drivers/gpu/ipu-v3/ipu-dc.c
@@ -147,20 +147,20 @@ static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
147 writel(reg2, priv->dc_tmpl_reg + word * 8 + 4); 147 writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
148} 148}
149 149
150static int ipu_pixfmt_to_map(u32 fmt) 150static int ipu_bus_format_to_map(u32 fmt)
151{ 151{
152 switch (fmt) { 152 switch (fmt) {
153 case V4L2_PIX_FMT_RGB24: 153 case MEDIA_BUS_FMT_RGB888_1X24:
154 return IPU_DC_MAP_RGB24; 154 return IPU_DC_MAP_RGB24;
155 case V4L2_PIX_FMT_RGB565: 155 case MEDIA_BUS_FMT_RGB565_1X16:
156 return IPU_DC_MAP_RGB565; 156 return IPU_DC_MAP_RGB565;
157 case IPU_PIX_FMT_GBR24: 157 case MEDIA_BUS_FMT_GBR888_1X24:
158 return IPU_DC_MAP_GBR24; 158 return IPU_DC_MAP_GBR24;
159 case V4L2_PIX_FMT_BGR666: 159 case MEDIA_BUS_FMT_RGB666_1X18:
160 return IPU_DC_MAP_BGR666; 160 return IPU_DC_MAP_BGR666;
161 case v4l2_fourcc('L', 'V', 'D', '6'): 161 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
162 return IPU_DC_MAP_LVDS666; 162 return IPU_DC_MAP_LVDS666;
163 case V4L2_PIX_FMT_BGR24: 163 case MEDIA_BUS_FMT_BGR888_1X24:
164 return IPU_DC_MAP_BGR24; 164 return IPU_DC_MAP_BGR24;
165 default: 165 default:
166 return -EINVAL; 166 return -EINVAL;
@@ -168,7 +168,7 @@ static int ipu_pixfmt_to_map(u32 fmt)
168} 168}
169 169
170int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced, 170int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
171 u32 pixel_fmt, u32 width) 171 u32 bus_format, u32 width)
172{ 172{
173 struct ipu_dc_priv *priv = dc->priv; 173 struct ipu_dc_priv *priv = dc->priv;
174 u32 reg = 0; 174 u32 reg = 0;
@@ -176,7 +176,7 @@ int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
176 176
177 dc->di = ipu_di_get_num(di); 177 dc->di = ipu_di_get_num(di);
178 178
179 map = ipu_pixfmt_to_map(pixel_fmt); 179 map = ipu_bus_format_to_map(bus_format);
180 if (map < 0) { 180 if (map < 0) {
181 dev_dbg(priv->dev, "IPU_DISP: No MAP\n"); 181 dev_dbg(priv->dev, "IPU_DISP: No MAP\n");
182 return map; 182 return map;