Merge branch 'mfd/wm8994' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc into for-3.3

52 files changed, 1021 insertions, 666 deletions

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 785127cb281b..1368826ef284 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -9,7 +9,6 @@ menuconfig DRM
         depends on (AGP || AGP=n) && !EMULATED_CMPXCHG && MMU
         select I2C
         select I2C_ALGOBIT
-        select SLOW_WORK
         help
           Kernel-level support for the Direct Rendering Infrastructure (DRI)
           introduced in XFree86 4.0. If you say Y here, you need to select
@@ -96,6 +95,7 @@ config DRM_I915
         select FB_CFB_IMAGEBLIT
         # i915 depends on ACPI_VIDEO when ACPI is enabled
         # but for select to work, need to select ACPI_VIDEO's dependencies, ick
+        select BACKLIGHT_LCD_SUPPORT if ACPI
         select BACKLIGHT_CLASS_DEVICE if ACPI
         select VIDEO_OUTPUT_CONTROL if ACPI
         select INPUT if ACPI
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 9a2e2a14b3bb..8323fc389840 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -1873,6 +1873,10 @@ int drm_mode_dirtyfb_ioctl(struct drm_device *dev,
         }
 
         if (num_clips && clips_ptr) {
+                if (num_clips < 0 || num_clips > DRM_MODE_FB_DIRTY_MAX_CLIPS) {
+                        ret = -EINVAL;
+                        goto out_err1;
+                }
                 clips = kzalloc(num_clips * sizeof(*clips), GFP_KERNEL);
                 if (!clips) {
                         ret = -ENOMEM;
@@ -2118,8 +2122,10 @@ struct drm_property *drm_property_create(struct drm_device *dev, int flags,
         property->num_values = num_values;
         INIT_LIST_HEAD(&property->enum_blob_list);
 
-        if (name)
+        if (name) {
                 strncpy(property->name, name, DRM_PROP_NAME_LEN);
+                property->name[DRM_PROP_NAME_LEN-1] = '\0';
+        }
 
         list_add_tail(&property->head, &dev->mode_config.property_list);
         return property;
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index 2957636161e8..3969f7553fe7 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -484,6 +484,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
         struct drm_connector *save_connectors, *connector;
         int count = 0, ro, fail = 0;
         struct drm_crtc_helper_funcs *crtc_funcs;
+        struct drm_mode_set save_set;
         int ret = 0;
         int i;
 
@@ -556,6 +557,12 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
                 save_connectors[count++] = *connector;
         }
 
+        save_set.crtc = set->crtc;
+        save_set.mode = &set->crtc->mode;
+        save_set.x = set->crtc->x;
+        save_set.y = set->crtc->y;
+        save_set.fb = set->crtc->fb;
+
         /* We should be able to check here if the fb has the same properties
          * and then just flip_or_move it */
         if (set->crtc->fb != set->fb) {
@@ -721,6 +728,12 @@ fail:
                 *connector = save_connectors[count++];
         }
 
+        /* Try to restore the config */
+        if (mode_changed &&
+            !drm_crtc_helper_set_mode(save_set.crtc, save_set.mode, save_set.x,
+                                      save_set.y, save_set.fb))
+                DRM_ERROR("failed to restore config after modeset failure\n");
+
         kfree(save_connectors);
         kfree(save_encoders);
         kfree(save_crtcs);
diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c
index d067c12ba940..1c7a1c0d3edd 100644
--- a/drivers/gpu/drm/drm_debugfs.c
+++ b/drivers/gpu/drm/drm_debugfs.c
@@ -118,7 +118,10 @@ int drm_debugfs_create_files(struct drm_info_list *files, int count,
                 tmp->minor = minor;
                 tmp->dent = ent;
                 tmp->info_ent = &files[i];
-                list_add(&(tmp->list), &(minor->debugfs_nodes.list));
+
+                mutex_lock(&minor->debugfs_lock);
+                list_add(&tmp->list, &minor->debugfs_list);
+                mutex_unlock(&minor->debugfs_lock);
         }
         return 0;
 
@@ -146,7 +149,8 @@ int drm_debugfs_init(struct drm_minor *minor, int minor_id,
         char name[64];
         int ret;
 
-        INIT_LIST_HEAD(&minor->debugfs_nodes.list);
+        INIT_LIST_HEAD(&minor->debugfs_list);
+        mutex_init(&minor->debugfs_lock);
         sprintf(name, "%d", minor_id);
         minor->debugfs_root = debugfs_create_dir(name, root);
         if (!minor->debugfs_root) {
@@ -192,8 +196,9 @@ int drm_debugfs_remove_files(struct drm_info_list *files, int count,
         struct drm_info_node *tmp;
         int i;
 
+        mutex_lock(&minor->debugfs_lock);
         for (i = 0; i < count; i++) {
-                list_for_each_safe(pos, q, &minor->debugfs_nodes.list) {
+                list_for_each_safe(pos, q, &minor->debugfs_list) {
                         tmp = list_entry(pos, struct drm_info_node, list);
                         if (tmp->info_ent == &files[i]) {
                                 debugfs_remove(tmp->dent);
@@ -202,6 +207,7 @@ int drm_debugfs_remove_files(struct drm_info_list *files, int count,
                         }
                 }
         }
+        mutex_unlock(&minor->debugfs_lock);
         return 0;
 }
 EXPORT_SYMBOL(drm_debugfs_remove_files);
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index fc81af9dbf42..40c187c60f44 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -125,7 +125,7 @@ static struct drm_ioctl_desc drm_ioctls[] = {
         DRM_IOCTL_DEF(DRM_IOCTL_SG_ALLOC, drm_sg_alloc_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
         DRM_IOCTL_DEF(DRM_IOCTL_SG_FREE, drm_sg_free, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 
-        DRM_IOCTL_DEF(DRM_IOCTL_WAIT_VBLANK, drm_wait_vblank, 0),
+        DRM_IOCTL_DEF(DRM_IOCTL_WAIT_VBLANK, drm_wait_vblank, DRM_UNLOCKED),
 
         DRM_IOCTL_DEF(DRM_IOCTL_MODESET_CTL, drm_modeset_ctl, 0),
 
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index cb3794a00f98..44a5d0ad8b7c 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -110,10 +110,7 @@ static void vblank_disable_and_save(struct drm_device *dev, int crtc)
         /* Prevent vblank irq processing while disabling vblank irqs,
          * so no updates of timestamps or count can happen after we've
          * disabled. Needed to prevent races in case of delayed irq's.
-         * Disable preemption, so vblank_time_lock is held as short as
-         * possible, even under a kernel with PREEMPT_RT patches.
          */
-        preempt_disable();
         spin_lock_irqsave(&dev->vblank_time_lock, irqflags);
 
         dev->driver->disable_vblank(dev, crtc);
@@ -164,7 +161,6 @@ static void vblank_disable_and_save(struct drm_device *dev, int crtc)
         clear_vblank_timestamps(dev, crtc);
 
         spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags);
-        preempt_enable();
 }
 
 static void vblank_disable_fn(unsigned long arg)
@@ -407,13 +403,16 @@ int drm_irq_uninstall(struct drm_device *dev)
         /*
          * Wake up any waiters so they don't hang.
          */
-        spin_lock_irqsave(&dev->vbl_lock, irqflags);
-        for (i = 0; i < dev->num_crtcs; i++) {
-                DRM_WAKEUP(&dev->vbl_queue[i]);
-                dev->vblank_enabled[i] = 0;
-                dev->last_vblank[i] = dev->driver->get_vblank_counter(dev, i);
+        if (dev->num_crtcs) {
+                spin_lock_irqsave(&dev->vbl_lock, irqflags);
+                for (i = 0; i < dev->num_crtcs; i++) {
+                        DRM_WAKEUP(&dev->vbl_queue[i]);
+                        dev->vblank_enabled[i] = 0;
+                        dev->last_vblank[i] =
+                                dev->driver->get_vblank_counter(dev, i);
+                }
+                spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
         }
-        spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
 
         if (!irq_enabled)
                 return -EINVAL;
@@ -886,10 +885,6 @@ int drm_vblank_get(struct drm_device *dev, int crtc)
         spin_lock_irqsave(&dev->vbl_lock, irqflags);
         /* Going from 0->1 means we have to enable interrupts again */
         if (atomic_add_return(1, &dev->vblank_refcount[crtc]) == 1) {
-                /* Disable preemption while holding vblank_time_lock. Do
-                 * it explicitely to guard against PREEMPT_RT kernel.
-                 */
-                preempt_disable();
                 spin_lock_irqsave(&dev->vblank_time_lock, irqflags2);
                 if (!dev->vblank_enabled[crtc]) {
                         /* Enable vblank irqs under vblank_time_lock protection.
@@ -909,7 +904,6 @@ int drm_vblank_get(struct drm_device *dev, int crtc)
                         }
                 }
                 spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags2);
-                preempt_enable();
         } else {
                 if (!dev->vblank_enabled[crtc]) {
                         atomic_dec(&dev->vblank_refcount[crtc]);
@@ -1125,6 +1119,7 @@ static int drm_queue_vblank_event(struct drm_device *dev, int pipe,
                 trace_drm_vblank_event_delivered(current->pid, pipe,
                                                  vblwait->request.sequence);
         } else {
+                /* drm_handle_vblank_events will call drm_vblank_put */
                 list_add_tail(&e->base.link, &dev->vblank_event_list);
                 vblwait->reply.sequence = vblwait->request.sequence;
         }
@@ -1205,8 +1200,12 @@ int drm_wait_vblank(struct drm_device *dev, void *data,
                 goto done;
         }
 
-        if (flags & _DRM_VBLANK_EVENT)
+        if (flags & _DRM_VBLANK_EVENT) {
+                /* must hold on to the vblank ref until the event fires
+                 * drm_vblank_put will be called asynchronously
+                 */
                 return drm_queue_vblank_event(dev, crtc, vblwait, file_priv);
+        }
 
         if ((flags & _DRM_VBLANK_NEXTONMISS) &&
             (seq - vblwait->request.sequence) <= (1<<23)) {
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d14b44e13f51..d09a6e02dc95 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -636,11 +636,16 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data)
         struct drm_device *dev = node->minor->dev;
         drm_i915_private_t *dev_priv = dev->dev_private;
         struct intel_ring_buffer *ring;
+        int ret;
 
         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
         if (ring->size == 0)
                 return 0;
 
+        ret = mutex_lock_interruptible(&dev->struct_mutex);
+        if (ret)
+                return ret;
+
         seq_printf(m, "Ring %s:\n", ring->name);
         seq_printf(m, "  Head :    %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);
         seq_printf(m, "  Tail :    %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);
@@ -654,6 +659,8 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data)
         seq_printf(m, "  Control : %08x\n", I915_READ_CTL(ring));
         seq_printf(m, "  Start :   %08x\n", I915_READ_START(ring));
 
+        mutex_unlock(&dev->struct_mutex);
+
         return 0;
 }
 
@@ -842,7 +849,16 @@ static int i915_rstdby_delays(struct seq_file *m, void *unused)
         struct drm_info_node *node = (struct drm_info_node *) m->private;
         struct drm_device *dev = node->minor->dev;
         drm_i915_private_t *dev_priv = dev->dev_private;
-        u16 crstanddelay = I915_READ16(CRSTANDVID);
+        u16 crstanddelay;
+        int ret;
+
+        ret = mutex_lock_interruptible(&dev->struct_mutex);
+        if (ret)
+                return ret;
+
+        crstanddelay = I915_READ16(CRSTANDVID);
+
+        mutex_unlock(&dev->struct_mutex);
 
         seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
 
@@ -940,7 +956,11 @@ static int i915_delayfreq_table(struct seq_file *m, void *unused)
         struct drm_device *dev = node->minor->dev;
         drm_i915_private_t *dev_priv = dev->dev_private;
         u32 delayfreq;
-        int i;
+        int ret, i;
+
+        ret = mutex_lock_interruptible(&dev->struct_mutex);
+        if (ret)
+                return ret;
 
         for (i = 0; i < 16; i++) {
                 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
@@ -948,6 +968,8 @@ static int i915_delayfreq_table(struct seq_file *m, void *unused)
                            (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
         }
 
+        mutex_unlock(&dev->struct_mutex);
+
         return 0;
 }
 
@@ -962,13 +984,19 @@ static int i915_inttoext_table(struct seq_file *m, void *unused)
         struct drm_device *dev = node->minor->dev;
         drm_i915_private_t *dev_priv = dev->dev_private;
         u32 inttoext;
-        int i;
+        int ret, i;
+
+        ret = mutex_lock_interruptible(&dev->struct_mutex);
+        if (ret)
+                return ret;
 
         for (i = 1; i <= 32; i++) {
                 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
                 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
         }
 
+        mutex_unlock(&dev->struct_mutex);
+
         return 0;
 }
 
@@ -977,9 +1005,19 @@ static int i915_drpc_info(struct seq_file *m, void *unused)
         struct drm_info_node *node = (struct drm_info_node *) m->private;
         struct drm_device *dev = node->minor->dev;
         drm_i915_private_t *dev_priv = dev->dev_private;
-        u32 rgvmodectl = I915_READ(MEMMODECTL);
-        u32 rstdbyctl = I915_READ(RSTDBYCTL);
-        u16 crstandvid = I915_READ16(CRSTANDVID);
+        u32 rgvmodectl, rstdbyctl;
+        u16 crstandvid;
+        int ret;
+
+        ret = mutex_lock_interruptible(&dev->struct_mutex);
+        if (ret)
+                return ret;
+
+        rgvmodectl = I915_READ(MEMMODECTL);
+        rstdbyctl = I915_READ(RSTDBYCTL);
+        crstandvid = I915_READ16(CRSTANDVID);
+
+        mutex_unlock(&dev->struct_mutex);
 
         seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
                    "yes" : "no");
@@ -1167,9 +1205,16 @@ static int i915_gfxec(struct seq_file *m, void *unused)
         struct drm_info_node *node = (struct drm_info_node *) m->private;
         struct drm_device *dev = node->minor->dev;
         drm_i915_private_t *dev_priv = dev->dev_private;
+        int ret;
+
+        ret = mutex_lock_interruptible(&dev->struct_mutex);
+        if (ret)
+                return ret;
 
         seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
 
+        mutex_unlock(&dev->struct_mutex);
+
         return 0;
 }
 
@@ -1506,7 +1551,10 @@ drm_add_fake_info_node(struct drm_minor *minor,
         node->minor = minor;
         node->dent = ent;
         node->info_ent = (void *) key;
-        list_add(&node->list, &minor->debugfs_nodes.list);
+
+        mutex_lock(&minor->debugfs_lock);
+        list_add(&node->list, &minor->debugfs_list);
+        mutex_unlock(&minor->debugfs_lock);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index cc531bb59c26..15bfa9145d2b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -68,7 +68,7 @@ module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
 MODULE_PARM_DESC(i915_enable_rc6,
                 "Enable power-saving render C-state 6 (default: true)");
 
-unsigned int i915_enable_fbc __read_mostly = -1;
+int i915_enable_fbc __read_mostly = -1;
 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
 MODULE_PARM_DESC(i915_enable_fbc,
                 "Enable frame buffer compression for power savings "
@@ -80,7 +80,7 @@ MODULE_PARM_DESC(lvds_downclock,
                 "Use panel (LVDS/eDP) downclocking for power savings "
                 "(default: false)");
 
-unsigned int i915_panel_use_ssc __read_mostly = -1;
+int i915_panel_use_ssc __read_mostly = -1;
 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
 MODULE_PARM_DESC(lvds_use_ssc,
                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
@@ -107,7 +107,7 @@ static struct drm_driver driver;
 extern int intel_agp_enabled;
 
 #define INTEL_VGA_DEVICE(id, info) {            \
-        .class = PCI_CLASS_DISPLAY_VGA << 8,    \
+        .class = PCI_BASE_CLASS_DISPLAY << 16,  \
         .class_mask = 0xff0000,                 \
         .vendor = 0x8086,                       \
         .device = id,                           \
@@ -789,8 +789,8 @@ static struct vm_operations_struct i915_gem_vm_ops = {
 };
 
 static struct drm_driver driver = {
-        /* don't use mtrr's here, the Xserver or user space app should
-         * deal with them for intel hardware.
+        /* Don't use MTRRs here; the Xserver or userspace app should
+         * deal with them for Intel hardware.
          */
         .driver_features =
             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 06a37f4fd74b..4a9c1b979804 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -126,6 +126,9 @@ struct drm_i915_master_private {
         struct _drm_i915_sarea *sarea_priv;
 };
 #define I915_FENCE_REG_NONE -1
+#define I915_MAX_NUM_FENCES 16
+/* 16 fences + sign bit for FENCE_REG_NONE */
+#define I915_MAX_NUM_FENCE_BITS 5
 
 struct drm_i915_fence_reg {
         struct list_head lru_list;
@@ -168,7 +171,7 @@ struct drm_i915_error_state {
         u32 instdone1;
         u32 seqno;
         u64 bbaddr;
-        u64 fence[16];
+        u64 fence[I915_MAX_NUM_FENCES];
         struct timeval time;
         struct drm_i915_error_object {
                 int page_count;
@@ -182,7 +185,7 @@ struct drm_i915_error_state {
                 u32 gtt_offset;
                 u32 read_domains;
                 u32 write_domain;
-                s32 fence_reg:5;
+                s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
                 s32 pinned:2;
                 u32 tiling:2;
                 u32 dirty:1;
@@ -375,7 +378,7 @@ typedef struct drm_i915_private {
         struct notifier_block lid_notifier;
 
         int crt_ddc_pin;
-        struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
+        struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 
@@ -506,7 +509,7 @@ typedef struct drm_i915_private {
         u8 saveAR[21];
         u8 saveDACMASK;
         u8 saveCR[37];
-        uint64_t saveFENCE[16];
+        uint64_t saveFENCE[I915_MAX_NUM_FENCES];
         u32 saveCURACNTR;
         u32 saveCURAPOS;
         u32 saveCURABASE;
@@ -777,10 +780,8 @@ struct drm_i915_gem_object {
          * Fence register bits (if any) for this object.  Will be set
          * as needed when mapped into the GTT.
          * Protected by dev->struct_mutex.
-         *
-         * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
          */
-        signed int fence_reg:5;
+        signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
 
         /**
          * Advice: are the backing pages purgeable?
@@ -999,10 +1000,10 @@ extern int i915_panel_ignore_lid __read_mostly;
 extern unsigned int i915_powersave __read_mostly;
 extern unsigned int i915_semaphores __read_mostly;
 extern unsigned int i915_lvds_downclock __read_mostly;
-extern unsigned int i915_panel_use_ssc __read_mostly;
+extern int i915_panel_use_ssc __read_mostly;
 extern int i915_vbt_sdvo_panel_type __read_mostly;
 extern unsigned int i915_enable_rc6 __read_mostly;
-extern unsigned int i915_enable_fbc __read_mostly;
+extern int i915_enable_fbc __read_mostly;
 extern bool i915_enable_hangcheck __read_mostly;
 
 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6651c36b6e8a..8359dc777041 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1396,7 +1396,7 @@ i915_gem_mmap_gtt(struct drm_file *file,
 
         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
                 ret = -E2BIG;
-                goto unlock;
+                goto out;
         }
 
         if (obj->madv != I915_MADV_WILLNEED) {
@@ -1745,7 +1745,7 @@ static void i915_gem_reset_fences(struct drm_device *dev)
         struct drm_i915_private *dev_priv = dev->dev_private;
         int i;
 
-        for (i = 0; i < 16; i++) {
+        for (i = 0; i < dev_priv->num_fence_regs; i++) {
                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
                 struct drm_i915_gem_object *obj = reg->obj;
 
@@ -3512,9 +3512,11 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
                          * so emit a request to do so.
                          */
                         request = kzalloc(sizeof(*request), GFP_KERNEL);
-                        if (request)
+                        if (request) {
                                 ret = i915_add_request(obj->ring, NULL, request);
-                        else
+                                if (ret)
+                                        kfree(request);
+                        } else
                                 ret = -ENOMEM;
                 }
 
@@ -3613,7 +3615,7 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
 
-        if (IS_GEN6(dev)) {
+        if (IS_GEN6(dev) || IS_GEN7(dev)) {
                 /* On Gen6, we can have the GPU use the LLC (the CPU
                  * cache) for about a 10% performance improvement
                  * compared to uncached.  Graphics requests other than
@@ -3877,7 +3879,7 @@ i915_gem_load(struct drm_device *dev)
         INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
         for (i = 0; i < I915_NUM_RINGS; i++)
                 init_ring_lists(&dev_priv->ring[i]);
-        for (i = 0; i < 16; i++)
+        for (i = 0; i < I915_MAX_NUM_FENCES; i++)
                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
                           i915_gem_retire_work_handler);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9ee2729fe5c6..b40004b55977 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -824,6 +824,7 @@ static void i915_gem_record_fences(struct drm_device *dev,
 
         /* Fences */
         switch (INTEL_INFO(dev)->gen) {
+        case 7:
         case 6:
                 for (i = 0; i < 16; i++)
                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5a09416e611f..b080cc824001 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1553,12 +1553,21 @@
  */
 #define   PP_READY              (1 << 30)
 #define   PP_SEQUENCE_NONE      (0 << 28)
-#define   PP_SEQUENCE_ON        (1 << 28)
-#define   PP_SEQUENCE_OFF       (2 << 28)
-#define   PP_SEQUENCE_MASK      0x30000000
+#define   PP_SEQUENCE_POWER_UP  (1 << 28)
+#define   PP_SEQUENCE_POWER_DOWN (2 << 28)
+#define   PP_SEQUENCE_MASK      (3 << 28)
+#define   PP_SEQUENCE_SHIFT     28
 #define   PP_CYCLE_DELAY_ACTIVE (1 << 27)
-#define   PP_SEQUENCE_STATE_ON_IDLE (1 << 3)
 #define   PP_SEQUENCE_STATE_MASK 0x0000000f
+#define   PP_SEQUENCE_STATE_OFF_IDLE    (0x0 << 0)
+#define   PP_SEQUENCE_STATE_OFF_S0_1    (0x1 << 0)
+#define   PP_SEQUENCE_STATE_OFF_S0_2    (0x2 << 0)
+#define   PP_SEQUENCE_STATE_OFF_S0_3    (0x3 << 0)
+#define   PP_SEQUENCE_STATE_ON_IDLE     (0x8 << 0)
+#define   PP_SEQUENCE_STATE_ON_S1_0     (0x9 << 0)
+#define   PP_SEQUENCE_STATE_ON_S1_2     (0xa << 0)
+#define   PP_SEQUENCE_STATE_ON_S1_3     (0xb << 0)
+#define   PP_SEQUENCE_STATE_RESET       (0xf << 0)
 #define PP_CONTROL      0x61204
 #define   POWER_TARGET_ON       (1 << 0)
 #define PP_ON_DELAYS    0x61208
@@ -3444,6 +3453,10 @@
 #define  GT_FIFO_FREE_ENTRIES                   0x120008
 #define    GT_FIFO_NUM_RESERVED_ENTRIES         20
 
+#define GEN6_UCGCTL2                            0x9404
+# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE               (1 << 12)
+# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE                (1 << 11)
+
 #define GEN6_RPNSWREQ                           0xA008
 #define   GEN6_TURBO_DISABLE                    (1<<31)
 #define   GEN6_FREQUENCY(x)                     ((x)<<25)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index f8f602d76650..7886e4fb60e3 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -370,6 +370,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
 
         /* Fences */
         switch (INTEL_INFO(dev)->gen) {
+        case 7:
         case 6:
                 for (i = 0; i < 16; i++)
                         dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
@@ -404,6 +405,7 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
 
         /* Fences */
         switch (INTEL_INFO(dev)->gen) {
+        case 7:
         case 6:
                 for (i = 0; i < 16; i++)
                         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 981b1f1c04d8..e77a863a3833 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2933,7 +2933,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 
         /* For PCH DP, enable TRANS_DP_CTL */
         if (HAS_PCH_CPT(dev) &&
-            intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
+            (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
+             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
                 reg = TRANS_DP_CTL(pipe);
                 temp = I915_READ(reg);
@@ -4711,7 +4712,7 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
                                 lvds_bpc = 6;
 
                         if (lvds_bpc < display_bpc) {
-                                DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
+                                DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
                                 display_bpc = lvds_bpc;
                         }
                         continue;
@@ -4722,7 +4723,7 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
 
                         if (edp_bpc < display_bpc) {
-                                DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
+                                DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
                                 display_bpc = edp_bpc;
                         }
                         continue;
@@ -4737,7 +4738,7 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
                         /* Don't use an invalid EDID bpc value */
                         if (connector->display_info.bpc &&
                             connector->display_info.bpc < display_bpc) {
-                                DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
+                                DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
                                 display_bpc = connector->display_info.bpc;
                         }
                 }
@@ -4748,10 +4749,10 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
                  */
                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
                         if (display_bpc > 8 && display_bpc < 12) {
-                                DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
+                                DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
                                 display_bpc = 12;
                         } else {
-                                DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
+                                DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
                                 display_bpc = 8;
                         }
                 }
@@ -4789,8 +4790,8 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
 
         display_bpc = min(display_bpc, bpc);
 
-        DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
-                         bpc, display_bpc);
+        DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
+                      bpc, display_bpc);
 
         *pipe_bpp = display_bpc * 3;
 
@@ -5671,7 +5672,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
         if ((is_lvds && dev_priv->lvds_dither) || dither) {
                 pipeconf |= PIPECONF_DITHER_EN;
-                pipeconf |= PIPECONF_DITHER_TYPE_ST1;
+                pipeconf |= PIPECONF_DITHER_TYPE_SP;
         }
         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
@@ -8148,6 +8149,20 @@ static void gen6_init_clock_gating(struct drm_device *dev)
         I915_WRITE(WM2_LP_ILK, 0);
         I915_WRITE(WM1_LP_ILK, 0);
 
+        /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
+         * gating disable must be set.  Failure to set it results in
+         * flickering pixels due to Z write ordering failures after
+         * some amount of runtime in the Mesa "fire" demo, and Unigine
+         * Sanctuary and Tropics, and apparently anything else with
+         * alpha test or pixel discard.
+         *
+         * According to the spec, bit 11 (RCCUNIT) must also be set,
+         * but we didn't debug actual testcases to find it out.
+         */
+        I915_WRITE(GEN6_UCGCTL2,
+                   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
+                   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
+
         /*
          * According to the spec the following bits should be
          * set in order to enable memory self-refresh and fbc:
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 09b318b0227f..4d0358fad937 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -59,7 +59,6 @@ struct intel_dp {
         struct i2c_algo_dp_aux_data algo;
         bool is_pch_edp;
         uint8_t train_set[4];
-        uint8_t link_status[DP_LINK_STATUS_SIZE];
         int panel_power_up_delay;
         int panel_power_down_delay;
         int panel_power_cycle_delay;
@@ -68,7 +67,6 @@ struct intel_dp {
         struct drm_display_mode *panel_fixed_mode;  /* for eDP */
         struct delayed_work panel_vdd_work;
         bool want_panel_vdd;
-        unsigned long panel_off_jiffies;
 };
 
 /**
@@ -157,16 +155,12 @@ intel_edp_link_config(struct intel_encoder *intel_encoder,
 static int
 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 {
-        int max_lane_count = 4;
-
-        if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
-                max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
-                switch (max_lane_count) {
-                case 1: case 2: case 4:
-                        break;
-                default:
-                        max_lane_count = 4;
-                }
+        int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
+        switch (max_lane_count) {
+        case 1: case 2: case 4:
+                break;
+        default:
+                max_lane_count = 4;
         }
         return max_lane_count;
 }
@@ -768,12 +762,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
                         continue;
 
                 intel_dp = enc_to_intel_dp(encoder);
-                if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
+                if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
+                    intel_dp->base.type == INTEL_OUTPUT_EDP)
+                {
                         lane_count = intel_dp->lane_count;
                         break;
-                } else if (is_edp(intel_dp)) {
-                        lane_count = dev_priv->edp.lanes;
-                        break;
                 }
         }
 
@@ -810,6 +803,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
                   struct drm_display_mode *adjusted_mode)
 {
         struct drm_device *dev = encoder->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
         struct drm_crtc *crtc = intel_dp->base.base.crtc;
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -822,18 +816,31 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
                         ironlake_edp_pll_off(encoder);
         }
 
-        intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
-        intel_dp->DP |= intel_dp->color_range;
+        /*
+         * There are three kinds of DP registers:
+         *
+         *      IBX PCH
+         *      CPU
+         *      CPT PCH
+         *
+         * IBX PCH and CPU are the same for almost everything,
+         * except that the CPU DP PLL is configured in this
+         * register
+         *
+         * CPT PCH is quite different, having many bits moved
+         * to the TRANS_DP_CTL register instead. That
+         * configuration happens (oddly) in ironlake_pch_enable
+         */
 
-        if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
-                intel_dp->DP |= DP_SYNC_HS_HIGH;
-        if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
-                intel_dp->DP |= DP_SYNC_VS_HIGH;
+        /* Preserve the BIOS-computed detected bit. This is
+         * supposed to be read-only.
+         */
+        intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
+        intel_dp->DP |=  DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 
-        if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
-                intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
-        else
-                intel_dp->DP |= DP_LINK_TRAIN_OFF;
+        /* Handle DP bits in common between all three register formats */
+
+        intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 
         switch (intel_dp->lane_count) {
         case 1:
@@ -852,59 +859,106 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
                 intel_write_eld(encoder, adjusted_mode);
         }
-
         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
         intel_dp->link_configuration[0] = intel_dp->link_bw;
         intel_dp->link_configuration[1] = intel_dp->lane_count;
         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
-
         /*
          * Check for DPCD version > 1.1 and enhanced framing support
          */
         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
-                intel_dp->DP |= DP_ENHANCED_FRAMING;
         }
 
-        /* CPT DP's pipe select is decided in TRANS_DP_CTL */
-        if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
-                intel_dp->DP |= DP_PIPEB_SELECT;
+        /* Split out the IBX/CPU vs CPT settings */
 
-        if (is_cpu_edp(intel_dp)) {
-                /* don't miss out required setting for eDP */
-                intel_dp->DP |= DP_PLL_ENABLE;
-                if (adjusted_mode->clock < 200000)
-                        intel_dp->DP |= DP_PLL_FREQ_160MHZ;
-                else
-                        intel_dp->DP |= DP_PLL_FREQ_270MHZ;
+        if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
+                intel_dp->DP |= intel_dp->color_range;
+
+                if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+                        intel_dp->DP |= DP_SYNC_HS_HIGH;
+                if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+                        intel_dp->DP |= DP_SYNC_VS_HIGH;
+                intel_dp->DP |= DP_LINK_TRAIN_OFF;
+
+                if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
+                        intel_dp->DP |= DP_ENHANCED_FRAMING;
+
+                if (intel_crtc->pipe == 1)
+                        intel_dp->DP |= DP_PIPEB_SELECT;
+
+                if (is_cpu_edp(intel_dp)) {
+                        /* don't miss out required setting for eDP */
+                        intel_dp->DP |= DP_PLL_ENABLE;
+                        if (adjusted_mode->clock < 200000)
+                                intel_dp->DP |= DP_PLL_FREQ_160MHZ;
+                        else
+                                intel_dp->DP |= DP_PLL_FREQ_270MHZ;
+                }
+        } else {
+                intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
         }
 }
 
-static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
+#define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
+#define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
+
+#define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
+#define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
+
+#define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
+#define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
+
+static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
+                                       u32 mask,
+                                       u32 value)
 {
-        unsigned long   off_time;
-        unsigned long   delay;
+        struct drm_device *dev = intel_dp->base.base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
 
-        DRM_DEBUG_KMS("Wait for panel power off time\n");
+        DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
+                      mask, value,
+                      I915_READ(PCH_PP_STATUS),
+                      I915_READ(PCH_PP_CONTROL));
 
-        if (ironlake_edp_have_panel_power(intel_dp) ||
-            ironlake_edp_have_panel_vdd(intel_dp))
-        {
-                DRM_DEBUG_KMS("Panel still on, no delay needed\n");
-                return;
+        if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
+                DRM_ERROR("Panel status timeout: status %08x control %08x\n",
+                          I915_READ(PCH_PP_STATUS),
+                          I915_READ(PCH_PP_CONTROL));
         }
+}
 
-        off_time = intel_dp->panel_off_jiffies + msecs_to_jiffies(intel_dp->panel_power_down_delay);
-        if (time_after(jiffies, off_time)) {
-                DRM_DEBUG_KMS("Time already passed");
-                return;
-        }
-        delay = jiffies_to_msecs(off_time - jiffies);
-        if (delay > intel_dp->panel_power_down_delay)
-                delay = intel_dp->panel_power_down_delay;
-        DRM_DEBUG_KMS("Waiting an additional %ld ms\n", delay);
-        msleep(delay);
+static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
+{
+        DRM_DEBUG_KMS("Wait for panel power on\n");
+        ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
+}
+
+static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
+{
+        DRM_DEBUG_KMS("Wait for panel power off time\n");
+        ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
+}
+
+static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
+{
+        DRM_DEBUG_KMS("Wait for panel power cycle\n");
+        ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
+}
+
+
+/* Read the current pp_control value, unlocking the register if it
+ * is locked
+ */
+
+static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
+{
+        u32     control = I915_READ(PCH_PP_CONTROL);
+
+        control &= ~PANEL_UNLOCK_MASK;
+        control |= PANEL_UNLOCK_REGS;
+        return control;
 }
 
 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
@@ -921,15 +975,16 @@ static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
              "eDP VDD already requested on\n");
 
         intel_dp->want_panel_vdd = true;
+
         if (ironlake_edp_have_panel_vdd(intel_dp)) {
                 DRM_DEBUG_KMS("eDP VDD already on\n");
                 return;
         }
 
-        ironlake_wait_panel_off(intel_dp);
-        pp = I915_READ(PCH_PP_CONTROL);
-        pp &= ~PANEL_UNLOCK_MASK;
-        pp |= PANEL_UNLOCK_REGS;
+        if (!ironlake_edp_have_panel_power(intel_dp))
+                ironlake_wait_panel_power_cycle(intel_dp);
+
+        pp = ironlake_get_pp_control(dev_priv);
         pp |= EDP_FORCE_VDD;
         I915_WRITE(PCH_PP_CONTROL, pp);
         POSTING_READ(PCH_PP_CONTROL);
@@ -952,9 +1007,7 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
         u32 pp;
 
         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
-                pp = I915_READ(PCH_PP_CONTROL);
-                pp &= ~PANEL_UNLOCK_MASK;
-                pp |= PANEL_UNLOCK_REGS;
+                pp = ironlake_get_pp_control(dev_priv);
                 pp &= ~EDP_FORCE_VDD;
                 I915_WRITE(PCH_PP_CONTROL, pp);
                 POSTING_READ(PCH_PP_CONTROL);
@@ -962,7 +1015,8 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
                 /* Make sure sequencer is idle before allowing subsequent activity */
                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
-                intel_dp->panel_off_jiffies = jiffies;
+
+                msleep(intel_dp->panel_power_down_delay);
         }
 }
 
@@ -972,9 +1026,9 @@ static void ironlake_panel_vdd_work(struct work_struct *__work)
                                                  struct intel_dp, panel_vdd_work);
         struct drm_device *dev = intel_dp->base.base.dev;
 
-        mutex_lock(&dev->struct_mutex);
+        mutex_lock(&dev->mode_config.mutex);
         ironlake_panel_vdd_off_sync(intel_dp);
-        mutex_unlock(&dev->struct_mutex);
+        mutex_unlock(&dev->mode_config.mutex);
 }
 
 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
@@ -984,7 +1038,7 @@ static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
 
         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
-        
+
         intel_dp->want_panel_vdd = false;
 
         if (sync) {
@@ -1000,23 +1054,25 @@ static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
         }
 }
 
-/* Returns true if the panel was already on when called */
 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
 {
         struct drm_device *dev = intel_dp->base.base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
-        u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
+        u32 pp;
 
         if (!is_edp(intel_dp))
                 return;
-        if (ironlake_edp_have_panel_power(intel_dp))
+
+        DRM_DEBUG_KMS("Turn eDP power on\n");
+
+        if (ironlake_edp_have_panel_power(intel_dp)) {
+                DRM_DEBUG_KMS("eDP power already on\n");
                 return;
+        }
 
-        ironlake_wait_panel_off(intel_dp);
-        pp = I915_READ(PCH_PP_CONTROL);
-        pp &= ~PANEL_UNLOCK_MASK;
-        pp |= PANEL_UNLOCK_REGS;
+        ironlake_wait_panel_power_cycle(intel_dp);
 
+        pp = ironlake_get_pp_control(dev_priv);
         if (IS_GEN5(dev)) {
                 /* ILK workaround: disable reset around power sequence */
                 pp &= ~PANEL_POWER_RESET;
@@ -1025,13 +1081,13 @@ static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
         }
 
         pp |= POWER_TARGET_ON;
+        if (!IS_GEN5(dev))
+                pp |= PANEL_POWER_RESET;
+
         I915_WRITE(PCH_PP_CONTROL, pp);
         POSTING_READ(PCH_PP_CONTROL);
 
-        if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
-                     5000))
-                DRM_ERROR("panel on wait timed out: 0x%08x\n",
-                          I915_READ(PCH_PP_STATUS));
+        ironlake_wait_panel_on(intel_dp);
 
         if (IS_GEN5(dev)) {
                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
@@ -1040,46 +1096,25 @@ static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
         }
 }
 
-static void ironlake_edp_panel_off(struct drm_encoder *encoder)
+static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
 {
-        struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-        struct drm_device *dev = encoder->dev;
+        struct drm_device *dev = intel_dp->base.base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
-        u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
-                PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
+        u32 pp;
 
         if (!is_edp(intel_dp))
                 return;
-        pp = I915_READ(PCH_PP_CONTROL);
-        pp &= ~PANEL_UNLOCK_MASK;
-        pp |= PANEL_UNLOCK_REGS;
 
-        if (IS_GEN5(dev)) {
-                /* ILK workaround: disable reset around power sequence */
-                pp &= ~PANEL_POWER_RESET;
-                I915_WRITE(PCH_PP_CONTROL, pp);
-                POSTING_READ(PCH_PP_CONTROL);
-        }
+        DRM_DEBUG_KMS("Turn eDP power off\n");
 
-        intel_dp->panel_off_jiffies = jiffies;
+        WARN(intel_dp->want_panel_vdd, "Cannot turn power off while VDD is on\n");
 
-        if (IS_GEN5(dev)) {
-                pp &= ~POWER_TARGET_ON;
-                I915_WRITE(PCH_PP_CONTROL, pp);
-                POSTING_READ(PCH_PP_CONTROL);
-                pp &= ~POWER_TARGET_ON;
-                I915_WRITE(PCH_PP_CONTROL, pp);
-                POSTING_READ(PCH_PP_CONTROL);
-                msleep(intel_dp->panel_power_cycle_delay);
-
-                if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
-                        DRM_ERROR("panel off wait timed out: 0x%08x\n",
-                                  I915_READ(PCH_PP_STATUS));
+        pp = ironlake_get_pp_control(dev_priv);
+        pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
+        I915_WRITE(PCH_PP_CONTROL, pp);
+        POSTING_READ(PCH_PP_CONTROL);
 
-                pp |= PANEL_POWER_RESET; /* restore panel reset bit */
-                I915_WRITE(PCH_PP_CONTROL, pp);
-                POSTING_READ(PCH_PP_CONTROL);
-        }
+        ironlake_wait_panel_off(intel_dp);
 }
 
 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
@@ -1099,9 +1134,7 @@ static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
          * allowing it to appear.
          */
         msleep(intel_dp->backlight_on_delay);
-        pp = I915_READ(PCH_PP_CONTROL);
-        pp &= ~PANEL_UNLOCK_MASK;
-        pp |= PANEL_UNLOCK_REGS;
+        pp = ironlake_get_pp_control(dev_priv);
         pp |= EDP_BLC_ENABLE;
         I915_WRITE(PCH_PP_CONTROL, pp);
         POSTING_READ(PCH_PP_CONTROL);
@@ -1117,9 +1150,7 @@ static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
                 return;
 
         DRM_DEBUG_KMS("\n");
-        pp = I915_READ(PCH_PP_CONTROL);
-        pp &= ~PANEL_UNLOCK_MASK;
-        pp |= PANEL_UNLOCK_REGS;
+        pp = ironlake_get_pp_control(dev_priv);
         pp &= ~EDP_BLC_ENABLE;
         I915_WRITE(PCH_PP_CONTROL, pp);
         POSTING_READ(PCH_PP_CONTROL);
@@ -1187,17 +1218,18 @@ static void intel_dp_prepare(struct drm_encoder *encoder)
 {
         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
+        ironlake_edp_backlight_off(intel_dp);
+        ironlake_edp_panel_off(intel_dp);
+
         /* Wake up the sink first */
         ironlake_edp_panel_vdd_on(intel_dp);
         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+        intel_dp_link_down(intel_dp);
         ironlake_edp_panel_vdd_off(intel_dp, false);
 
         /* Make sure the panel is off before trying to
          * change the mode
          */
-        ironlake_edp_backlight_off(intel_dp);
-        intel_dp_link_down(intel_dp);
-        ironlake_edp_panel_off(encoder);
 }
 
 static void intel_dp_commit(struct drm_encoder *encoder)
@@ -1211,7 +1243,6 @@ static void intel_dp_commit(struct drm_encoder *encoder)
         intel_dp_start_link_train(intel_dp);
         ironlake_edp_panel_on(intel_dp);
         ironlake_edp_panel_vdd_off(intel_dp, true);
-
         intel_dp_complete_link_train(intel_dp);
         ironlake_edp_backlight_on(intel_dp);
 
@@ -1230,16 +1261,20 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
 
         if (mode != DRM_MODE_DPMS_ON) {
+                ironlake_edp_backlight_off(intel_dp);
+                ironlake_edp_panel_off(intel_dp);
+
                 ironlake_edp_panel_vdd_on(intel_dp);
-                if (is_edp(intel_dp))
-                        ironlake_edp_backlight_off(intel_dp);
                 intel_dp_sink_dpms(intel_dp, mode);
                 intel_dp_link_down(intel_dp);
-                ironlake_edp_panel_off(encoder);
-                if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
-                        ironlake_edp_pll_off(encoder);
                 ironlake_edp_panel_vdd_off(intel_dp, false);
+
+                if (is_cpu_edp(intel_dp))
+                        ironlake_edp_pll_off(encoder);
         } else {
+                if (is_cpu_edp(intel_dp))
+                        ironlake_edp_pll_on(encoder);
+
                 ironlake_edp_panel_vdd_on(intel_dp);
                 intel_dp_sink_dpms(intel_dp, mode);
                 if (!(dp_reg & DP_PORT_EN)) {
@@ -1247,7 +1282,6 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
                         ironlake_edp_panel_on(intel_dp);
                         ironlake_edp_panel_vdd_off(intel_dp, true);
                         intel_dp_complete_link_train(intel_dp);
-                        ironlake_edp_backlight_on(intel_dp);
                 } else
                         ironlake_edp_panel_vdd_off(intel_dp, false);
                 ironlake_edp_backlight_on(intel_dp);
@@ -1285,11 +1319,11 @@ intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
  * link status information
  */
 static bool
-intel_dp_get_link_status(struct intel_dp *intel_dp)
+intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
 {
         return intel_dp_aux_native_read_retry(intel_dp,
                                               DP_LANE0_1_STATUS,
-                                              intel_dp->link_status,
+                                              link_status,
                                               DP_LINK_STATUS_SIZE);
 }
 
@@ -1301,27 +1335,25 @@ intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 }
 
 static uint8_t
-intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
+intel_get_adjust_request_voltage(uint8_t adjust_request[2],
                                  int lane)
 {
-        int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
         int         s = ((lane & 1) ?
                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
-        uint8_t l = intel_dp_link_status(link_status, i);
+        uint8_t l = adjust_request[lane>>1];
 
         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
 }
 
 static uint8_t
-intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
+intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
                                       int lane)
 {
-        int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
         int         s = ((lane & 1) ?
                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
-        uint8_t l = intel_dp_link_status(link_status, i);
+        uint8_t l = adjust_request[lane>>1];
 
         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
 }
@@ -1344,6 +1376,7 @@ static char	*link_train_names[] = {
  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
  */
 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
+#define I830_DP_VOLTAGE_MAX_CPT     DP_TRAIN_VOLTAGE_SWING_1200
 
 static uint8_t
 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
@@ -1362,15 +1395,18 @@ intel_dp_pre_emphasis_max(uint8_t voltage_swing)
 }
 
 static void
-intel_get_adjust_train(struct intel_dp *intel_dp)
+intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
 {
+        struct drm_device *dev = intel_dp->base.base.dev;
         uint8_t v = 0;
         uint8_t p = 0;
         int lane;
+        uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
+        int voltage_max;
 
         for (lane = 0; lane < intel_dp->lane_count; lane++) {
-                uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
-                uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
+                uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
+                uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
 
                 if (this_v > v)
                         v = this_v;
@@ -1378,8 +1414,12 @@ intel_get_adjust_train(struct intel_dp *intel_dp)
                         p = this_p;
         }
 
-        if (v >= I830_DP_VOLTAGE_MAX)
-                v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
+        if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
+                voltage_max = I830_DP_VOLTAGE_MAX_CPT;
+        else
+                voltage_max = I830_DP_VOLTAGE_MAX;
+        if (v >= voltage_max)
+                v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
 
         if (p >= intel_dp_pre_emphasis_max(v))
                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
@@ -1389,7 +1429,7 @@ intel_get_adjust_train(struct intel_dp *intel_dp)
 }
 
 static uint32_t
-intel_dp_signal_levels(uint8_t train_set, int lane_count)
+intel_dp_signal_levels(uint8_t train_set)
 {
         uint32_t        signal_levels = 0;
 
@@ -1458,9 +1498,8 @@ static uint8_t
 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
                       int lane)
 {
-        int i = DP_LANE0_1_STATUS + (lane >> 1);
         int s = (lane & 1) * 4;
-        uint8_t l = intel_dp_link_status(link_status, i);
+        uint8_t l = link_status[lane>>1];
 
         return (l >> s) & 0xf;
 }
@@ -1485,18 +1524,18 @@ intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count
                          DP_LANE_CHANNEL_EQ_DONE|\
                          DP_LANE_SYMBOL_LOCKED)
 static bool
-intel_channel_eq_ok(struct intel_dp *intel_dp)
+intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
 {
         uint8_t lane_align;
         uint8_t lane_status;
         int lane;
 
-        lane_align = intel_dp_link_status(intel_dp->link_status,
+        lane_align = intel_dp_link_status(link_status,
                                           DP_LANE_ALIGN_STATUS_UPDATED);
         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
                 return false;
         for (lane = 0; lane < intel_dp->lane_count; lane++) {
-                lane_status = intel_get_lane_status(intel_dp->link_status, lane);
+                lane_status = intel_get_lane_status(link_status, lane);
                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
                         return false;
         }
@@ -1521,8 +1560,9 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
 
         ret = intel_dp_aux_native_write(intel_dp,
                                         DP_TRAINING_LANE0_SET,
-                                        intel_dp->train_set, 4);
-        if (ret != 4)
+                                        intel_dp->train_set,
+                                        intel_dp->lane_count);
+        if (ret != intel_dp->lane_count)
                 return false;
 
         return true;
@@ -1538,7 +1578,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
         int i;
         uint8_t voltage;
         bool clock_recovery = false;
-        int tries;
+        int voltage_tries, loop_tries;
         u32 reg;
         uint32_t DP = intel_dp->DP;
 
@@ -1565,16 +1605,20 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
                 DP &= ~DP_LINK_TRAIN_MASK;
         memset(intel_dp->train_set, 0, 4);
         voltage = 0xff;
-        tries = 0;
+        voltage_tries = 0;
+        loop_tries = 0;
         clock_recovery = false;
         for (;;) {
                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
+                uint8_t     link_status[DP_LINK_STATUS_SIZE];
                 uint32_t    signal_levels;
-                if (IS_GEN6(dev) && is_edp(intel_dp)) {
+
+                if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
                 } else {
-                        signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
+                        signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
+                        DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
                 }
 
@@ -1590,10 +1634,13 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
                 /* Set training pattern 1 */
 
                 udelay(100);
-                if (!intel_dp_get_link_status(intel_dp))
+                if (!intel_dp_get_link_status(intel_dp, link_status)) {
+                        DRM_ERROR("failed to get link status\n");
                         break;
+                }
 
-                if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
+                if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
+                        DRM_DEBUG_KMS("clock recovery OK\n");
                         clock_recovery = true;
                         break;
                 }
@@ -1602,20 +1649,30 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
                 for (i = 0; i < intel_dp->lane_count; i++)
                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
                                 break;
-                if (i == intel_dp->lane_count)
-                        break;
+                if (i == intel_dp->lane_count) {
+                        ++loop_tries;
+                        if (loop_tries == 5) {
+                                DRM_DEBUG_KMS("too many full retries, give up\n");
+                                break;
+                        }
+                        memset(intel_dp->train_set, 0, 4);
+                        voltage_tries = 0;
+                        continue;
+                }
 
                 /* Check to see if we've tried the same voltage 5 times */
                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
-                        ++tries;
-                        if (tries == 5)
+                        ++voltage_tries;
+                        if (voltage_tries == 5) {
+                                DRM_DEBUG_KMS("too many voltage retries, give up\n");
                                 break;
+                        }
                 } else
-                        tries = 0;
+                        voltage_tries = 0;
                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 
                 /* Compute new intel_dp->train_set as requested by target */
-                intel_get_adjust_train(intel_dp);
+                intel_get_adjust_train(intel_dp, link_status);
         }
 
         intel_dp->DP = DP;
@@ -1638,6 +1695,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
         for (;;) {
                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
                 uint32_t    signal_levels;
+                uint8_t     link_status[DP_LINK_STATUS_SIZE];
 
                 if (cr_tries > 5) {
                         DRM_ERROR("failed to train DP, aborting\n");
@@ -1645,11 +1703,11 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
                         break;
                 }
 
-                if (IS_GEN6(dev) && is_edp(intel_dp)) {
+                if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
                 } else {
-                        signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
+                        signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
                 }
 
@@ -1665,17 +1723,17 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
                         break;
 
                 udelay(400);
-                if (!intel_dp_get_link_status(intel_dp))
+                if (!intel_dp_get_link_status(intel_dp, link_status))
                         break;
 
                 /* Make sure clock is still ok */
-                if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
+                if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
                         intel_dp_start_link_train(intel_dp);
                         cr_tries++;
                         continue;
                 }
 
-                if (intel_channel_eq_ok(intel_dp)) {
+                if (intel_channel_eq_ok(intel_dp, link_status)) {
                         channel_eq = true;
                         break;
                 }
@@ -1690,7 +1748,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
                 }
 
                 /* Compute new intel_dp->train_set as requested by target */
-                intel_get_adjust_train(intel_dp);
+                intel_get_adjust_train(intel_dp, link_status);
                 ++tries;
         }
 
@@ -1735,8 +1793,12 @@ intel_dp_link_down(struct intel_dp *intel_dp)
 
         msleep(17);
 
-        if (is_edp(intel_dp))
-                DP |= DP_LINK_TRAIN_OFF;
+        if (is_edp(intel_dp)) {
+                if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
+                        DP |= DP_LINK_TRAIN_OFF_CPT;
+                else
+                        DP |= DP_LINK_TRAIN_OFF;
+        }
 
         if (!HAS_PCH_CPT(dev) &&
             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
@@ -1822,6 +1884,7 @@ static void
 intel_dp_check_link_status(struct intel_dp *intel_dp)
 {
         u8 sink_irq_vector;
+        u8 link_status[DP_LINK_STATUS_SIZE];
 
         if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
                 return;
@@ -1830,7 +1893,7 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
                 return;
 
         /* Try to read receiver status if the link appears to be up */
-        if (!intel_dp_get_link_status(intel_dp)) {
+        if (!intel_dp_get_link_status(intel_dp, link_status)) {
                 intel_dp_link_down(intel_dp);
                 return;
         }
@@ -1855,7 +1918,7 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
         }
 
-        if (!intel_channel_eq_ok(intel_dp)) {
+        if (!intel_channel_eq_ok(intel_dp, link_status)) {
                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
                               drm_get_encoder_name(&intel_dp->base.base));
                 intel_dp_start_link_train(intel_dp);
@@ -2179,7 +2242,8 @@ intel_trans_dp_port_sel(struct drm_crtc *crtc)
                         continue;
 
                 intel_dp = enc_to_intel_dp(encoder);
-                if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
+                if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
+                    intel_dp->base.type == INTEL_OUTPUT_EDP)
                         return intel_dp->output_reg;
         }
 
@@ -2321,7 +2385,7 @@ intel_dp_init(struct drm_device *dev, int output_reg)
 
                 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
                         PANEL_LIGHT_ON_DELAY_SHIFT;
-                
+
                 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
                         PANEL_LIGHT_OFF_DELAY_SHIFT;
 
@@ -2354,11 +2418,10 @@ intel_dp_init(struct drm_device *dev, int output_reg)
                 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
 
-                intel_dp->panel_off_jiffies = jiffies - intel_dp->panel_power_down_delay;
-
                 ironlake_edp_panel_vdd_on(intel_dp);
                 ret = intel_dp_get_dpcd(intel_dp);
                 ironlake_edp_panel_vdd_off(intel_dp, false);
+
                 if (ret) {
                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
                                 dev_priv->no_aux_handshake =
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 499d4c0dbeeb..21f60b7d69a3 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -326,7 +326,8 @@ static int intel_panel_update_status(struct backlight_device *bd)
 static int intel_panel_get_brightness(struct backlight_device *bd)
 {
         struct drm_device *dev = bl_get_data(bd);
-        return intel_panel_get_backlight(dev);
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        return dev_priv->backlight_level;
 }
 
 static const struct backlight_ops intel_panel_bl_ops = {
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 032a82098136..5fc201b49d30 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -640,10 +640,9 @@ static int
 nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
 {
         struct drm_nouveau_private *dev_priv = dev->dev_private;
-        uint32_t reg0 = nv_rd32(dev, reg + 0);
-        uint32_t reg1 = nv_rd32(dev, reg + 4);
         struct nouveau_pll_vals pll;
         struct pll_lims pll_limits;
+        u32 ctrl, mask, coef;
         int ret;
 
         ret = get_pll_limits(dev, reg, &pll_limits);
@@ -654,15 +653,20 @@ nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
         if (!clk)
                 return -ERANGE;
 
-        reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16);
-        reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1;
-
-        if (dev_priv->vbios.execute) {
-                still_alive();
-                nv_wr32(dev, reg + 4, reg1);
-                nv_wr32(dev, reg + 0, reg0);
+        coef = pll.N1 << 8 | pll.M1;
+        ctrl = pll.log2P << 16;
+        mask = 0x00070000;
+        if (reg == 0x004008) {
+                mask |= 0x01f80000;
+                ctrl |= (pll_limits.log2p_bias << 19);
+                ctrl |= (pll.log2P << 22);
         }
 
+        if (!dev_priv->vbios.execute)
+                return 0;
+
+        nv_mask(dev, reg + 0, mask, ctrl);
+        nv_wr32(dev, reg + 4, coef);
         return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 7226f419e178..7cc37e690860 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -148,7 +148,7 @@ set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
 
         if (dev_priv->card_type == NV_10 &&
             nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
-            nvbo->bo.mem.num_pages < vram_pages / 2) {
+            nvbo->bo.mem.num_pages < vram_pages / 4) {
                 /*
                  * Make sure that the color and depth buffers are handled
                  * by independent memory controller units. Up to a 9x
diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c
index a319d5646ea9..bb6ec9ef8676 100644
--- a/drivers/gpu/drm/nouveau/nouveau_channel.c
+++ b/drivers/gpu/drm/nouveau/nouveau_channel.c
@@ -158,6 +158,7 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
         INIT_LIST_HEAD(&chan->nvsw.vbl_wait);
         INIT_LIST_HEAD(&chan->nvsw.flip);
         INIT_LIST_HEAD(&chan->fence.pending);
+        spin_lock_init(&chan->fence.lock);
 
         /* setup channel's memory and vm */
         ret = nouveau_gpuobj_channel_init(chan, vram_handle, gart_handle);
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index e0d275e1c96c..cea6696b1906 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -710,7 +710,7 @@ nouveau_connector_mode_valid(struct drm_connector *connector,
         case OUTPUT_DP:
                 max_clock  = nv_encoder->dp.link_nr;
                 max_clock *= nv_encoder->dp.link_bw;
-                clock = clock * nouveau_connector_bpp(connector) / 8;
+                clock = clock * nouveau_connector_bpp(connector) / 10;
                 break;
         default:
                 BUG_ON(1);
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 14a8627efe4d..3a4cc32b9e44 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -487,6 +487,7 @@ int nouveau_fbcon_init(struct drm_device *dev)
 {
         struct drm_nouveau_private *dev_priv = dev->dev_private;
         struct nouveau_fbdev *nfbdev;
+        int preferred_bpp;
         int ret;
 
         nfbdev = kzalloc(sizeof(struct nouveau_fbdev), GFP_KERNEL);
@@ -505,7 +506,15 @@ int nouveau_fbcon_init(struct drm_device *dev)
         }
 
         drm_fb_helper_single_add_all_connectors(&nfbdev->helper);
-        drm_fb_helper_initial_config(&nfbdev->helper, 32);
+
+        if (dev_priv->vram_size <= 32 * 1024 * 1024)
+                preferred_bpp = 8;
+        else if (dev_priv->vram_size <= 64 * 1024 * 1024)
+                preferred_bpp = 16;
+        else
+                preferred_bpp = 32;
+
+        drm_fb_helper_initial_config(&nfbdev->helper, preferred_bpp);
         return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c
index 81116cfea275..2f6daae68b9d 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.c
@@ -539,8 +539,6 @@ nouveau_fence_channel_init(struct nouveau_channel *chan)
                         return ret;
         }
 
-        INIT_LIST_HEAD(&chan->fence.pending);
-        spin_lock_init(&chan->fence.lock);
         atomic_set(&chan->fence.last_sequence_irq, 0);
         return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_i2c.c b/drivers/gpu/drm/nouveau/nouveau_i2c.c
index c6143df48b9f..d39b2202b197 100644
--- a/drivers/gpu/drm/nouveau/nouveau_i2c.c
+++ b/drivers/gpu/drm/nouveau/nouveau_i2c.c
@@ -333,7 +333,7 @@ nouveau_i2c_identify(struct drm_device *dev, const char *what,
 
         NV_DEBUG(dev, "Probing %ss on I2C bus: %d\n", what, index);
 
-        for (i = 0; info[i].addr; i++) {
+        for (i = 0; i2c && info[i].addr; i++) {
                 if (nouveau_probe_i2c_addr(i2c, info[i].addr) &&
                     (!match || match(i2c, &info[i]))) {
                         NV_INFO(dev, "Detected %s: %s\n", what, info[i].type);
diff --git a/drivers/gpu/drm/nouveau/nouveau_perf.c b/drivers/gpu/drm/nouveau/nouveau_perf.c
index 9f178aa94162..33d03fbf00df 100644
--- a/drivers/gpu/drm/nouveau/nouveau_perf.c
+++ b/drivers/gpu/drm/nouveau/nouveau_perf.c
@@ -239,7 +239,7 @@ nouveau_perf_init(struct drm_device *dev)
         if(version == 0x15) {
                 memtimings->timing =
                                 kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL);
-                if(!memtimings) {
+                if (!memtimings->timing) {
                         NV_WARN(dev,"Could not allocate memtiming table\n");
                         return;
                 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 82478e0998e5..d8831ab42bb9 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -579,6 +579,14 @@ nouveau_card_init(struct drm_device *dev)
         if (ret)
                 goto out_display_early;
 
+        /* workaround an odd issue on nvc1 by disabling the device's
+         * nosnoop capability.  hopefully won't cause issues until a
+         * better fix is found - assuming there is one...
+         */
+        if (dev_priv->chipset == 0xc1) {
+                nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
+        }
+
         nouveau_pm_init(dev);
 
         ret = engine->vram.init(dev);
@@ -1102,12 +1110,13 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
         dev_priv->noaccel = !!nouveau_noaccel;
         if (nouveau_noaccel == -1) {
                 switch (dev_priv->chipset) {
-                case 0xc1: /* known broken */
-                case 0xc8: /* never tested */
+#if 0
+                case 0xXX: /* known broken */
                         NV_INFO(dev, "acceleration disabled by default, pass "
                                      "noaccel=0 to force enable\n");
                         dev_priv->noaccel = true;
                         break;
+#endif
                 default:
                         dev_priv->noaccel = false;
                         break;
diff --git a/drivers/gpu/drm/nouveau/nv40_pm.c b/drivers/gpu/drm/nouveau/nv40_pm.c
index bbc0b9c7e1f7..e676b0d53478 100644
--- a/drivers/gpu/drm/nouveau/nv40_pm.c
+++ b/drivers/gpu/drm/nouveau/nv40_pm.c
@@ -57,12 +57,14 @@ read_pll_2(struct drm_device *dev, u32 reg)
         int P = (ctrl & 0x00070000) >> 16;
         u32 ref = 27000, clk = 0;
 
-        if (ctrl & 0x80000000)
+        if ((ctrl & 0x80000000) && M1) {
                 clk = ref * N1 / M1;
-
-        if (!(ctrl & 0x00000100)) {
-                if (ctrl & 0x40000000)
-                        clk = clk * N2 / M2;
+                if ((ctrl & 0x40000100) == 0x40000000) {
+                        if (M2)
+                                clk = clk * N2 / M2;
+                        else
+                                clk = 0;
+                }
         }
 
         return clk >> P;
@@ -177,6 +179,11 @@ nv40_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
         }
 
         /* memory clock */
+        if (!perflvl->memory) {
+                info->mpll_ctrl = 0x00000000;
+                goto out;
+        }
+
         ret = nv40_calc_pll(dev, 0x004020, &pll, perflvl->memory,
                             &N1, &M1, &N2, &M2, &log2P);
         if (ret < 0)
@@ -264,6 +271,9 @@ nv40_pm_clocks_set(struct drm_device *dev, void *pre_state)
         mdelay(5);
         nv_mask(dev, 0x00c040, 0x00000333, info->ctrl);
 
+        if (!info->mpll_ctrl)
+                goto resume;
+
         /* wait for vblank start on active crtcs, disable memory access */
         for (i = 0; i < 2; i++) {
                 if (!(crtc_mask & (1 << i)))
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c
index 8c979b31ff61..ac601f7c4e1a 100644
--- a/drivers/gpu/drm/nouveau/nv50_graph.c
+++ b/drivers/gpu/drm/nouveau/nv50_graph.c
@@ -131,8 +131,8 @@ nv50_graph_init(struct drm_device *dev, int engine)
         NV_DEBUG(dev, "\n");
 
         /* master reset */
-        nv_mask(dev, 0x000200, 0x00200100, 0x00000000);
-        nv_mask(dev, 0x000200, 0x00200100, 0x00200100);
+        nv_mask(dev, 0x000200, 0x00201000, 0x00000000);
+        nv_mask(dev, 0x000200, 0x00201000, 0x00201000);
         nv_wr32(dev, 0x40008c, 0x00000004); /* HW_CTX_SWITCH_ENABLED */
 
         /* reset/enable traps and interrupts */
diff --git a/drivers/gpu/drm/nouveau/nv50_grctx.c b/drivers/gpu/drm/nouveau/nv50_grctx.c
index d05c2c3b2444..4b46d6968566 100644
--- a/drivers/gpu/drm/nouveau/nv50_grctx.c
+++ b/drivers/gpu/drm/nouveau/nv50_grctx.c
@@ -601,7 +601,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
                                         gr_def(ctx, offset + 0x1c, 0x00880000);
                                         break;
                                 case 0x86:
-                                        gr_def(ctx, offset + 0x1c, 0x008c0000);
+                                        gr_def(ctx, offset + 0x1c, 0x018c0000);
                                         break;
                                 case 0x92:
                                 case 0x96:
diff --git a/drivers/gpu/drm/nouveau/nv50_vram.c b/drivers/gpu/drm/nouveau/nv50_vram.c
index 9da23838e63e..2e45e57fd869 100644
--- a/drivers/gpu/drm/nouveau/nv50_vram.c
+++ b/drivers/gpu/drm/nouveau/nv50_vram.c
@@ -160,7 +160,7 @@ nv50_vram_rblock(struct drm_device *dev)
         colbits  =  (r4 & 0x0000f000) >> 12;
         rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
         rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
-        banks    = ((r4 & 0x01000000) ? 8 : 4);
+        banks    = 1 << (((r4 & 0x03000000) >> 24) + 2);
 
         rowsize = parts * banks * (1 << colbits) * 8;
         predicted = rowsize << rowbitsa;
diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.c b/drivers/gpu/drm/nouveau/nvc0_graph.c
index bbdbc51830c8..a74e501afd25 100644
--- a/drivers/gpu/drm/nouveau/nvc0_graph.c
+++ b/drivers/gpu/drm/nouveau/nvc0_graph.c
@@ -157,8 +157,8 @@ nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
         struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
         struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
         struct drm_device *dev = chan->dev;
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
         int i = 0, gpc, tp, ret;
-        u32 magic;
 
         ret = nouveau_gpuobj_new(dev, chan, 0x2000, 256, NVOBJ_FLAG_VM,
                                  &grch->unk408004);
@@ -207,14 +207,37 @@ nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
         nv_wo32(grch->mmio, i++ * 4, 0x0041880c);
         nv_wo32(grch->mmio, i++ * 4, 0x80000018);
 
-        magic = 0x02180000;
-        nv_wo32(grch->mmio, i++ * 4, 0x00405830);
-        nv_wo32(grch->mmio, i++ * 4, magic);
-        for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-                for (tp = 0; tp < priv->tp_nr[gpc]; tp++, magic += 0x0324) {
-                        u32 reg = 0x504520 + (gpc * 0x8000) + (tp * 0x0800);
-                        nv_wo32(grch->mmio, i++ * 4, reg);
-                        nv_wo32(grch->mmio, i++ * 4, magic);
+        if (dev_priv->chipset != 0xc1) {
+                u32 magic = 0x02180000;
+                nv_wo32(grch->mmio, i++ * 4, 0x00405830);
+                nv_wo32(grch->mmio, i++ * 4, magic);
+                for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
+                        for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
+                                u32 reg = TP_UNIT(gpc, tp, 0x520);
+                                nv_wo32(grch->mmio, i++ * 4, reg);
+                                nv_wo32(grch->mmio, i++ * 4, magic);
+                                magic += 0x0324;
+                        }
+                }
+        } else {
+                u32 magic = 0x02180000;
+                nv_wo32(grch->mmio, i++ * 4, 0x00405830);
+                nv_wo32(grch->mmio, i++ * 4, magic | 0x0000218);
+                nv_wo32(grch->mmio, i++ * 4, 0x004064c4);
+                nv_wo32(grch->mmio, i++ * 4, 0x0086ffff);
+                for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
+                        for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
+                                u32 reg = TP_UNIT(gpc, tp, 0x520);
+                                nv_wo32(grch->mmio, i++ * 4, reg);
+                                nv_wo32(grch->mmio, i++ * 4, (1 << 28) | magic);
+                                magic += 0x0324;
+                        }
+                        for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
+                                u32 reg = TP_UNIT(gpc, tp, 0x544);
+                                nv_wo32(grch->mmio, i++ * 4, reg);
+                                nv_wo32(grch->mmio, i++ * 4, magic);
+                                magic += 0x0324;
+                        }
                 }
         }
 
diff --git a/drivers/gpu/drm/nouveau/nvc0_grctx.c b/drivers/gpu/drm/nouveau/nvc0_grctx.c
index dd0e6a736b3b..96b0b93d94ca 100644
--- a/drivers/gpu/drm/nouveau/nvc0_grctx.c
+++ b/drivers/gpu/drm/nouveau/nvc0_grctx.c
@@ -1812,6 +1812,7 @@ nvc0_grctx_generate(struct nouveau_channel *chan)
                 /* calculate first set of magics */
                 memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr));
 
+                gpc = -1;
                 for (tp = 0; tp < priv->tp_total; tp++) {
                         do {
                                 gpc = (gpc + 1) % priv->gpc_nr;
@@ -1861,30 +1862,26 @@ nvc0_grctx_generate(struct nouveau_channel *chan)
 
         if (1) {
                 u32 tp_mask = 0, tp_set = 0;
-                u8  tpnr[GPC_MAX];
+                u8  tpnr[GPC_MAX], a, b;
 
                 memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr));
                 for (gpc = 0; gpc < priv->gpc_nr; gpc++)
                         tp_mask |= ((1 << priv->tp_nr[gpc]) - 1) << (gpc * 8);
 
-                gpc = -1;
-                for (i = 0, gpc = -1; i < 32; i++) {
-                        int ltp = i * (priv->tp_total - 1) / 32;
-
-                        do {
-                                gpc = (gpc + 1) % priv->gpc_nr;
-                        } while (!tpnr[gpc]);
-                        tp = priv->tp_nr[gpc] - tpnr[gpc]--;
+                for (i = 0, gpc = -1, b = -1; i < 32; i++) {
+                        a = (i * (priv->tp_total - 1)) / 32;
+                        if (a != b) {
+                                b = a;
+                                do {
+                                        gpc = (gpc + 1) % priv->gpc_nr;
+                                } while (!tpnr[gpc]);
+                                tp = priv->tp_nr[gpc] - tpnr[gpc]--;
 
-                        tp_set |= 1 << ((gpc * 8) + tp);
+                                tp_set |= 1 << ((gpc * 8) + tp);
+                        }
 
-                        do {
-                                nv_wr32(dev, 0x406800 + (i * 0x20), tp_set);
-                                tp_set ^= tp_mask;
-                                nv_wr32(dev, 0x406c00 + (i * 0x20), tp_set);
-                                tp_set ^= tp_mask;
-                        } while (ltp == (++i * (priv->tp_total - 1) / 32));
-                        i--;
+                        nv_wr32(dev, 0x406800 + (i * 0x20), tp_set);
+                        nv_wr32(dev, 0x406c00 + (i * 0x20), tp_set ^ tp_mask);
                 }
         }
 
diff --git a/drivers/gpu/drm/nouveau/nvc0_vram.c b/drivers/gpu/drm/nouveau/nvc0_vram.c
index edbfe9360ae2..ce984d573a51 100644
--- a/drivers/gpu/drm/nouveau/nvc0_vram.c
+++ b/drivers/gpu/drm/nouveau/nvc0_vram.c
@@ -43,7 +43,7 @@ static const u8 types[256] = {
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 3, 3, 3, 3, 1, 1, 1, 1, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3,
-        3, 3, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3,
+        3, 3, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3,
         3, 3, 0, 0, 0, 0, 0, 0, 3, 0, 0, 3, 0, 3, 0, 3,
         3, 0, 3, 3, 3, 3, 3, 0, 0, 3, 0, 3, 0, 3, 3, 0,
         3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 1, 1, 0
@@ -110,22 +110,26 @@ nvc0_vram_init(struct drm_device *dev)
         u32 bsize = nv_rd32(dev, 0x10f20c);
         u32 offset, length;
         bool uniform = true;
-        int ret, i;
+        int ret, part;
 
         NV_DEBUG(dev, "0x100800: 0x%08x\n", nv_rd32(dev, 0x100800));
         NV_DEBUG(dev, "parts 0x%08x bcast_mem_amount 0x%08x\n", parts, bsize);
 
         /* read amount of vram attached to each memory controller */
-        for (i = 0; i < parts; i++) {
-                u32 psize = nv_rd32(dev, 0x11020c + (i * 0x1000));
+        part = 0;
+        while (parts) {
+                u32 psize = nv_rd32(dev, 0x11020c + (part++ * 0x1000));
+                if (psize == 0)
+                        continue;
+                parts--;
+
                 if (psize != bsize) {
                         if (psize < bsize)
                                 bsize = psize;
                         uniform = false;
                 }
 
-                NV_DEBUG(dev, "%d: mem_amount 0x%08x\n", i, psize);
-
+                NV_DEBUG(dev, "%d: mem_amount 0x%08x\n", part, psize);
                 dev_priv->vram_size += (u64)psize << 20;
         }
 
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 87921c88a95c..87631fede1f8 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1522,12 +1522,6 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
                                      struct drm_display_mode *mode,
                                      struct drm_display_mode *adjusted_mode)
 {
-        struct drm_device *dev = crtc->dev;
-        struct radeon_device *rdev = dev->dev_private;
-
-        /* adjust pm to upcoming mode change */
-        radeon_pm_compute_clocks(rdev);
-
         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
                 return false;
         return true;
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index a0de48542f71..6fb335a4fdda 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -283,7 +283,7 @@ int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
                 }
         }
 
-        DRM_ERROR("aux i2c too many retries, giving up\n");
+        DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
         return -EREMOTEIO;
 }
 
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index e4c384b9511c..1d603a3335db 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -157,6 +157,57 @@ int sumo_get_temp(struct radeon_device *rdev)
         return actual_temp * 1000;
 }
 
+void sumo_pm_init_profile(struct radeon_device *rdev)
+{
+        int idx;
+
+        /* default */
+        rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
+        rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
+        rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
+        rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
+
+        /* low,mid sh/mh */
+        if (rdev->flags & RADEON_IS_MOBILITY)
+                idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
+        else
+                idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
+
+        rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
+        rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
+        rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
+        rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
+
+        rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
+        rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
+        rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
+        rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
+
+        rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
+        rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
+        rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
+        rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
+
+        rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
+        rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
+        rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
+        rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
+
+        /* high sh/mh */
+        idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
+        rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
+        rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
+        rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
+        rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
+                rdev->pm.power_state[idx].num_clock_modes - 1;
+
+        rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
+        rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
+        rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
+        rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
+                rdev->pm.power_state[idx].num_clock_modes - 1;
+}
+
 void evergreen_pm_misc(struct radeon_device *rdev)
 {
         int req_ps_idx = rdev->pm.requested_power_state_index;
@@ -1219,7 +1270,7 @@ void evergreen_mc_program(struct radeon_device *rdev)
                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
                         rdev->mc.vram_end >> 12);
         }
-        WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
+        WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
         if (rdev->flags & RADEON_IS_IGP) {
                 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
                 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 7fdfa8ea7570..38e1bda73d33 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -480,21 +480,23 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                 }
                 break;
         case DB_Z_INFO:
-                r = evergreen_cs_packet_next_reloc(p, &reloc);
-                if (r) {
-                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
-                                        "0x%04X\n", reg);
-                        return -EINVAL;
-                }
                 track->db_z_info = radeon_get_ib_value(p, idx);
-                ib[idx] &= ~Z_ARRAY_MODE(0xf);
-                track->db_z_info &= ~Z_ARRAY_MODE(0xf);
-                if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
-                        ib[idx] |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
-                        track->db_z_info |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
-                } else {
-                        ib[idx] |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
-                        track->db_z_info |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
+                if (!p->keep_tiling_flags) {
+                        r = evergreen_cs_packet_next_reloc(p, &reloc);
+                        if (r) {
+                                dev_warn(p->dev, "bad SET_CONTEXT_REG "
+                                                "0x%04X\n", reg);
+                                return -EINVAL;
+                        }
+                        ib[idx] &= ~Z_ARRAY_MODE(0xf);
+                        track->db_z_info &= ~Z_ARRAY_MODE(0xf);
+                        if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
+                                ib[idx] |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
+                                track->db_z_info |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
+                        } else {
+                                ib[idx] |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
+                                track->db_z_info |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
+                        }
                 }
                 break;
         case DB_STENCIL_INFO:
@@ -607,40 +609,44 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
         case CB_COLOR5_INFO:
         case CB_COLOR6_INFO:
         case CB_COLOR7_INFO:
-                r = evergreen_cs_packet_next_reloc(p, &reloc);
-                if (r) {
-                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
-                                        "0x%04X\n", reg);
-                        return -EINVAL;
-                }
                 tmp = (reg - CB_COLOR0_INFO) / 0x3c;
                 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
-                if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
-                        ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
-                        track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
-                } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
-                        ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
-                        track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
+                if (!p->keep_tiling_flags) {
+                        r = evergreen_cs_packet_next_reloc(p, &reloc);
+                        if (r) {
+                                dev_warn(p->dev, "bad SET_CONTEXT_REG "
+                                                "0x%04X\n", reg);
+                                return -EINVAL;
+                        }
+                        if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
+                                ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
+                                track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
+                        } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
+                                ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
+                                track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
+                        }
                 }
                 break;
         case CB_COLOR8_INFO:
         case CB_COLOR9_INFO:
         case CB_COLOR10_INFO:
         case CB_COLOR11_INFO:
-                r = evergreen_cs_packet_next_reloc(p, &reloc);
-                if (r) {
-                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
-                                        "0x%04X\n", reg);
-                        return -EINVAL;
-                }
                 tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
                 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
-                if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
-                        ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
-                        track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
-                } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
-                        ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
-                        track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
+                if (!p->keep_tiling_flags) {
+                        r = evergreen_cs_packet_next_reloc(p, &reloc);
+                        if (r) {
+                                dev_warn(p->dev, "bad SET_CONTEXT_REG "
+                                                "0x%04X\n", reg);
+                                return -EINVAL;
+                        }
+                        if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
+                                ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
+                                track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
+                        } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
+                                ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
+                                track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
+                        }
                 }
                 break;
         case CB_COLOR0_PITCH:
@@ -1311,10 +1317,12 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                         return -EINVAL;
                                 }
                                 ib[idx+1+(i*8)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
-                                if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
-                                        ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
-                                else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
-                                        ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
+                                if (!p->keep_tiling_flags) {
+                                        if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+                                                ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
+                                        else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+                                                ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
+                                }
                                 texture = reloc->robj;
                                 /* tex mip base */
                                 r = evergreen_cs_packet_next_reloc(p, &reloc);
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 400b26df652a..c93bc64707e1 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -701,16 +701,21 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                         return r;
                 }
 
-                if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
-                        tile_flags |= R300_TXO_MACRO_TILE;
-                if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
-                        tile_flags |= R300_TXO_MICRO_TILE;
-                else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
-                        tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
-
-                tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
-                tmp |= tile_flags;
-                ib[idx] = tmp;
+                if (p->keep_tiling_flags) {
+                        ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
+                                  ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset);
+                } else {
+                        if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+                                tile_flags |= R300_TXO_MACRO_TILE;
+                        if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+                                tile_flags |= R300_TXO_MICRO_TILE;
+                        else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
+                                tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
+
+                        tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
+                        tmp |= tile_flags;
+                        ib[idx] = tmp;
+                }
                 track->textures[i].robj = reloc->robj;
                 track->tex_dirty = true;
                 break;
@@ -760,24 +765,26 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                 /* RB3D_COLORPITCH1 */
                 /* RB3D_COLORPITCH2 */
                 /* RB3D_COLORPITCH3 */
-                r = r100_cs_packet_next_reloc(p, &reloc);
-                if (r) {
-                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
-                                  idx, reg);
-                        r100_cs_dump_packet(p, pkt);
-                        return r;
-                }
+                if (!p->keep_tiling_flags) {
+                        r = r100_cs_packet_next_reloc(p, &reloc);
+                        if (r) {
+                                DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+                                          idx, reg);
+                                r100_cs_dump_packet(p, pkt);
+                                return r;
+                        }
 
-                if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
-                        tile_flags |= R300_COLOR_TILE_ENABLE;
-                if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
-                        tile_flags |= R300_COLOR_MICROTILE_ENABLE;
-                else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
-                        tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
+                        if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+                                tile_flags |= R300_COLOR_TILE_ENABLE;
+                        if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+                                tile_flags |= R300_COLOR_MICROTILE_ENABLE;
+                        else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
+                                tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
 
-                tmp = idx_value & ~(0x7 << 16);
-                tmp |= tile_flags;
-                ib[idx] = tmp;
+                        tmp = idx_value & ~(0x7 << 16);
+                        tmp |= tile_flags;
+                        ib[idx] = tmp;
+                }
                 i = (reg - 0x4E38) >> 2;
                 track->cb[i].pitch = idx_value & 0x3FFE;
                 switch (((idx_value >> 21) & 0xF)) {
@@ -843,25 +850,26 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                 break;
         case 0x4F24:
                 /* ZB_DEPTHPITCH */
-                r = r100_cs_packet_next_reloc(p, &reloc);
-                if (r) {
-                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
-                                  idx, reg);
-                        r100_cs_dump_packet(p, pkt);
-                        return r;
-                }
-
-                if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
-                        tile_flags |= R300_DEPTHMACROTILE_ENABLE;
-                if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
-                        tile_flags |= R300_DEPTHMICROTILE_TILED;
-                else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
-                        tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
+                if (!p->keep_tiling_flags) {
+                        r = r100_cs_packet_next_reloc(p, &reloc);
+                        if (r) {
+                                DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+                                          idx, reg);
+                                r100_cs_dump_packet(p, pkt);
+                                return r;
+                        }
 
-                tmp = idx_value & ~(0x7 << 16);
-                tmp |= tile_flags;
-                ib[idx] = tmp;
+                        if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+                                tile_flags |= R300_DEPTHMACROTILE_ENABLE;
+                        if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+                                tile_flags |= R300_DEPTHMICROTILE_TILED;
+                        else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
+                                tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
 
+                        tmp = idx_value & ~(0x7 << 16);
+                        tmp |= tile_flags;
+                        ib[idx] = tmp;
+                }
                 track->zb.pitch = idx_value & 0x3FFC;
                 track->zb_dirty = true;
                 break;
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 19afc43ad173..9cdda0b3b081 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -288,24 +288,6 @@ void r600_pm_get_dynpm_state(struct radeon_device *rdev)
                   pcie_lanes);
 }
 
-static int r600_pm_get_type_index(struct radeon_device *rdev,
-                                  enum radeon_pm_state_type ps_type,
-                                  int instance)
-{
-        int i;
-        int found_instance = -1;
-
-        for (i = 0; i < rdev->pm.num_power_states; i++) {
-                if (rdev->pm.power_state[i].type == ps_type) {
-                        found_instance++;
-                        if (found_instance == instance)
-                                return i;
-                }
-        }
-        /* return default if no match */
-        return rdev->pm.default_power_state_index;
-}
-
 void rs780_pm_init_profile(struct radeon_device *rdev)
 {
         if (rdev->pm.num_power_states == 2) {
@@ -421,6 +403,8 @@ void rs780_pm_init_profile(struct radeon_device *rdev)
 
 void r600_pm_init_profile(struct radeon_device *rdev)
 {
+        int idx;
+
         if (rdev->family == CHIP_R600) {
                 /* XXX */
                 /* default */
@@ -502,81 +486,43 @@ void r600_pm_init_profile(struct radeon_device *rdev)
                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
                         /* low sh */
-                        if (rdev->flags & RADEON_IS_MOBILITY) {
-                                rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
-                                        r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
-                                rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
-                                        r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
-                                rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
-                                rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
-                        } else {
-                                rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
-                                        r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
-                                rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
-                                        r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
-                                rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
-                                rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
-                        }
+                        if (rdev->flags & RADEON_IS_MOBILITY)
+                                idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
+                        else
+                                idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
+                        rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
+                        rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
+                        rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
+                        rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
                         /* mid sh */
-                        if (rdev->flags & RADEON_IS_MOBILITY) {
-                                rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
-                                        r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
-                                rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
-                                        r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
-                                rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
-                                rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
-                        } else {
-                                rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
-                                        r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
-                                rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
-                                        r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
-                                rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
-                                rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
-                        }
+                        rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
+                        rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
+                        rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
+                        rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
                         /* high sh */
-                        rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
-                                r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
-                        rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
-                                r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
+                        idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
+                        rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
+                        rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
                         /* low mh */
-                        if (rdev->flags & RADEON_IS_MOBILITY) {
-                                rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
-                                        r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
-                                rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
-                                        r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
-                                rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
-                                rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
-                        } else {
-                                rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
-                                        r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
-                                rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
-                                        r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
-                                rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
-                                rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
-                        }
+                        if (rdev->flags & RADEON_IS_MOBILITY)
+                                idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
+                        else
+                                idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
+                        rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
+                        rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
+                        rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
+                        rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
                         /* mid mh */
-                        if (rdev->flags & RADEON_IS_MOBILITY) {
-                                rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
-                                        r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
-                                rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
-                                        r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
-                                rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
-                                rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
-                        } else {
-                                rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
-                                        r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
-                                rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
-                                        r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
-                                rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
-                                rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
-                        }
+                        rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
+                        rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
+                        rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
+                        rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
                         /* high mh */
-                        rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
-                                r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
-                        rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
-                                r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
+                        idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
+                        rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
+                        rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
                 }
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 0a2e023c1557..cb1acffd2430 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -941,7 +941,8 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                 track->db_depth_control = radeon_get_ib_value(p, idx);
                 break;
         case R_028010_DB_DEPTH_INFO:
-                if (r600_cs_packet_next_is_pkt3_nop(p)) {
+                if (!p->keep_tiling_flags &&
+                    r600_cs_packet_next_is_pkt3_nop(p)) {
                         r = r600_cs_packet_next_reloc(p, &reloc);
                         if (r) {
                                 dev_warn(p->dev, "bad SET_CONTEXT_REG "
@@ -992,7 +993,8 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
         case R_0280B4_CB_COLOR5_INFO:
         case R_0280B8_CB_COLOR6_INFO:
         case R_0280BC_CB_COLOR7_INFO:
-                if (r600_cs_packet_next_is_pkt3_nop(p)) {
+                if (!p->keep_tiling_flags &&
+                     r600_cs_packet_next_is_pkt3_nop(p)) {
                         r = r600_cs_packet_next_reloc(p, &reloc);
                         if (r) {
                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
@@ -1291,10 +1293,12 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 idx,
         mip_offset <<= 8;
 
         word0 = radeon_get_ib_value(p, idx + 0);
-        if (tiling_flags & RADEON_TILING_MACRO)
-                word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
-        else if (tiling_flags & RADEON_TILING_MICRO)
-                word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
+        if (!p->keep_tiling_flags) {
+                if (tiling_flags & RADEON_TILING_MACRO)
+                        word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
+                else if (tiling_flags & RADEON_TILING_MICRO)
+                        word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
+        }
         word1 = radeon_get_ib_value(p, idx + 1);
         w0 = G_038000_TEX_WIDTH(word0) + 1;
         h0 = G_038004_TEX_HEIGHT(word1) + 1;
@@ -1621,10 +1625,12 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                         return -EINVAL;
                                 }
                                 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
-                                if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
-                                        ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
-                                else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
-                                        ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
+                                if (!p->keep_tiling_flags) {
+                                        if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+                                                ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
+                                        else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+                                                ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
+                                }
                                 texture = reloc->robj;
                                 /* tex mip base */
                                 r = r600_cs_packet_next_reloc(p, &reloc);
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index b316b301152f..8227e76b5c70 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -611,7 +611,8 @@ struct radeon_cs_parser {
         struct radeon_ib        *ib;
         void                    *track;
         unsigned                family;
-        int parser_error;
+        int                     parser_error;
+        bool                    keep_tiling_flags;
 };
 
 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
@@ -784,8 +785,7 @@ struct radeon_pm_clock_info {
 
 struct radeon_power_state {
         enum radeon_pm_state_type type;
-        /* XXX: use a define for num clock modes */
-        struct radeon_pm_clock_info clock_info[8];
+        struct radeon_pm_clock_info *clock_info;
         /* number of valid clock modes in this power state */
         int num_clock_modes;
         struct radeon_pm_clock_info *default_clock_mode;
@@ -855,6 +855,9 @@ struct radeon_pm {
         struct device           *int_hwmon_dev;
 };
 
+int radeon_pm_get_type_index(struct radeon_device *rdev,
+                             enum radeon_pm_state_type ps_type,
+                             int instance);
 
 /*
  * Benchmarking
@@ -1142,6 +1145,48 @@ struct r600_vram_scratch {
         u64                             gpu_addr;
 };
 
+
+/*
+ * Mutex which allows recursive locking from the same process.
+ */
+struct radeon_mutex {
+        struct mutex            mutex;
+        struct task_struct      *owner;
+        int                     level;
+};
+
+static inline void radeon_mutex_init(struct radeon_mutex *mutex)
+{
+        mutex_init(&mutex->mutex);
+        mutex->owner = NULL;
+        mutex->level = 0;
+}
+
+static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
+{
+        if (mutex_trylock(&mutex->mutex)) {
+                /* The mutex was unlocked before, so it's ours now */
+                mutex->owner = current;
+        } else if (mutex->owner != current) {
+                /* Another process locked the mutex, take it */
+                mutex_lock(&mutex->mutex);
+                mutex->owner = current;
+        }
+        /* Otherwise the mutex was already locked by this process */
+
+        mutex->level++;
+}
+
+static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
+{
+        if (--mutex->level > 0)
+                return;
+
+        mutex->owner = NULL;
+        mutex_unlock(&mutex->mutex);
+}
+
+
 /*
  * Core structure, functions and helpers.
  */
@@ -1197,7 +1242,7 @@ struct radeon_device {
         struct radeon_gem               gem;
         struct radeon_pm                pm;
         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
-        struct mutex                    cs_mutex;
+        struct radeon_mutex             cs_mutex;
         struct radeon_wb                wb;
         struct radeon_dummy_page        dummy_page;
         bool                            gpu_lockup;
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index e2944566ffea..a2e1eae114ef 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -834,7 +834,7 @@ static struct radeon_asic sumo_asic = {
         .pm_misc = &evergreen_pm_misc,
         .pm_prepare = &evergreen_pm_prepare,
         .pm_finish = &evergreen_pm_finish,
-        .pm_init_profile = &rs780_pm_init_profile,
+        .pm_init_profile = &sumo_pm_init_profile,
         .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
         .pre_page_flip = &evergreen_pre_page_flip,
         .page_flip = &evergreen_page_flip,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 85f14f0337e4..59914842a729 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -413,6 +413,7 @@ extern int evergreen_cs_parse(struct radeon_cs_parser *p);
 extern void evergreen_pm_misc(struct radeon_device *rdev);
 extern void evergreen_pm_prepare(struct radeon_device *rdev);
 extern void evergreen_pm_finish(struct radeon_device *rdev);
+extern void sumo_pm_init_profile(struct radeon_device *rdev);
 extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
 extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
 extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 08d0b94332e6..d24baf30efcb 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -62,6 +62,87 @@ union atom_supported_devices {
         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
 };
 
+static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
+                                          ATOM_GPIO_I2C_ASSIGMENT *gpio,
+                                          u8 index)
+{
+        /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
+        if ((rdev->family == CHIP_R420) ||
+            (rdev->family == CHIP_R423) ||
+            (rdev->family == CHIP_RV410)) {
+                if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
+                    (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
+                    (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
+                        gpio->ucClkMaskShift = 0x19;
+                        gpio->ucDataMaskShift = 0x18;
+                }
+        }
+
+        /* some evergreen boards have bad data for this entry */
+        if (ASIC_IS_DCE4(rdev)) {
+                if ((index == 7) &&
+                    (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
+                    (gpio->sucI2cId.ucAccess == 0)) {
+                        gpio->sucI2cId.ucAccess = 0x97;
+                        gpio->ucDataMaskShift = 8;
+                        gpio->ucDataEnShift = 8;
+                        gpio->ucDataY_Shift = 8;
+                        gpio->ucDataA_Shift = 8;
+                }
+        }
+
+        /* some DCE3 boards have bad data for this entry */
+        if (ASIC_IS_DCE3(rdev)) {
+                if ((index == 4) &&
+                    (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
+                    (gpio->sucI2cId.ucAccess == 0x94))
+                        gpio->sucI2cId.ucAccess = 0x14;
+        }
+}
+
+static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
+{
+        struct radeon_i2c_bus_rec i2c;
+
+        memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
+
+        i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
+        i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
+        i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
+        i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
+        i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
+        i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
+        i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
+        i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
+        i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
+        i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
+        i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
+        i2c.en_data_mask = (1 << gpio->ucDataEnShift);
+        i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
+        i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
+        i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
+        i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
+
+        if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
+                i2c.hw_capable = true;
+        else
+                i2c.hw_capable = false;
+
+        if (gpio->sucI2cId.ucAccess == 0xa0)
+                i2c.mm_i2c = true;
+        else
+                i2c.mm_i2c = false;
+
+        i2c.i2c_id = gpio->sucI2cId.ucAccess;
+
+        if (i2c.mask_clk_reg)
+                i2c.valid = true;
+        else
+                i2c.valid = false;
+
+        return i2c;
+}
+
 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
                                                                uint8_t id)
 {
@@ -85,59 +166,10 @@ static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rd
                 for (i = 0; i < num_indices; i++) {
                         gpio = &i2c_info->asGPIO_Info[i];
 
-                        /* some evergreen boards have bad data for this entry */
-                        if (ASIC_IS_DCE4(rdev)) {
-                                if ((i == 7) &&
-                                    (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
-                                    (gpio->sucI2cId.ucAccess == 0)) {
-                                        gpio->sucI2cId.ucAccess = 0x97;
-                                        gpio->ucDataMaskShift = 8;
-                                        gpio->ucDataEnShift = 8;
-                                        gpio->ucDataY_Shift = 8;
-                                        gpio->ucDataA_Shift = 8;
-                                }
-                        }
-
-                        /* some DCE3 boards have bad data for this entry */
-                        if (ASIC_IS_DCE3(rdev)) {
-                                if ((i == 4) &&
-                                    (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
-                                    (gpio->sucI2cId.ucAccess == 0x94))
-                                        gpio->sucI2cId.ucAccess = 0x14;
-                        }
+                        radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 
                         if (gpio->sucI2cId.ucAccess == id) {
-                                i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
-                                i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
-                                i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
-                                i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
-                                i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
-                                i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
-                                i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
-                                i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
-                                i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
-                                i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
-                                i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
-                                i2c.en_data_mask = (1 << gpio->ucDataEnShift);
-                                i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
-                                i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
-                                i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
-                                i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
-
-                                if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
-                                        i2c.hw_capable = true;
-                                else
-                                        i2c.hw_capable = false;
-
-                                if (gpio->sucI2cId.ucAccess == 0xa0)
-                                        i2c.mm_i2c = true;
-                                else
-                                        i2c.mm_i2c = false;
-
-                                i2c.i2c_id = gpio->sucI2cId.ucAccess;
-
-                                if (i2c.mask_clk_reg)
-                                        i2c.valid = true;
+                                i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
                                 break;
                         }
                 }
@@ -157,8 +189,6 @@ void radeon_atombios_i2c_init(struct radeon_device *rdev)
         int i, num_indices;
         char stmp[32];
 
-        memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
-
         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 
@@ -167,60 +197,12 @@ void radeon_atombios_i2c_init(struct radeon_device *rdev)
 
                 for (i = 0; i < num_indices; i++) {
                         gpio = &i2c_info->asGPIO_Info[i];
-                        i2c.valid = false;
-
-                        /* some evergreen boards have bad data for this entry */
-                        if (ASIC_IS_DCE4(rdev)) {
-                                if ((i == 7) &&
-                                    (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
-                                    (gpio->sucI2cId.ucAccess == 0)) {
-                                        gpio->sucI2cId.ucAccess = 0x97;
-                                        gpio->ucDataMaskShift = 8;
-                                        gpio->ucDataEnShift = 8;
-                                        gpio->ucDataY_Shift = 8;
-                                        gpio->ucDataA_Shift = 8;
-                                }
-                        }
 
-                        /* some DCE3 boards have bad data for this entry */
-                        if (ASIC_IS_DCE3(rdev)) {
-                                if ((i == 4) &&
-                                    (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
-                                    (gpio->sucI2cId.ucAccess == 0x94))
-                                        gpio->sucI2cId.ucAccess = 0x14;
-                        }
+                        radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 
-                        i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
-                        i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
-                        i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
-                        i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
-                        i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
-                        i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
-                        i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
-                        i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
-                        i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
-                        i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
-                        i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
-                        i2c.en_data_mask = (1 << gpio->ucDataEnShift);
-                        i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
-                        i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
-                        i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
-                        i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
-
-                        if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
-                                i2c.hw_capable = true;
-                        else
-                                i2c.hw_capable = false;
-
-                        if (gpio->sucI2cId.ucAccess == 0xa0)
-                                i2c.mm_i2c = true;
-                        else
-                                i2c.mm_i2c = false;
+                        i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 
-                        i2c.i2c_id = gpio->sucI2cId.ucAccess;
-
-                        if (i2c.mask_clk_reg) {
-                                i2c.valid = true;
+                        if (i2c.valid) {
                                 sprintf(stmp, "0x%x", i2c.i2c_id);
                                 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
                         }
@@ -1996,10 +1978,14 @@ static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
                 return state_index;
         /* last mode is usually default, array is low to high */
         for (i = 0; i < num_modes; i++) {
+                rdev->pm.power_state[state_index].clock_info =
+                        kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
+                if (!rdev->pm.power_state[state_index].clock_info)
+                        return state_index;
+                rdev->pm.power_state[state_index].num_clock_modes = 1;
                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
                 switch (frev) {
                 case 1:
-                        rdev->pm.power_state[state_index].num_clock_modes = 1;
                         rdev->pm.power_state[state_index].clock_info[0].mclk =
                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
                         rdev->pm.power_state[state_index].clock_info[0].sclk =
@@ -2035,7 +2021,6 @@ static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
                         state_index++;
                         break;
                 case 2:
-                        rdev->pm.power_state[state_index].num_clock_modes = 1;
                         rdev->pm.power_state[state_index].clock_info[0].mclk =
                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
                         rdev->pm.power_state[state_index].clock_info[0].sclk =
@@ -2072,7 +2057,6 @@ static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
                         state_index++;
                         break;
                 case 3:
-                        rdev->pm.power_state[state_index].num_clock_modes = 1;
                         rdev->pm.power_state[state_index].clock_info[0].mclk =
                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
                         rdev->pm.power_state[state_index].clock_info[0].sclk =
@@ -2257,7 +2241,7 @@ static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rde
                 rdev->pm.default_power_state_index = state_index;
                 rdev->pm.power_state[state_index].default_clock_mode =
                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
-                if (ASIC_IS_DCE5(rdev)) {
+                if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
                         /* NI chips post without MC ucode, so default clocks are strobe mode only */
                         rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
                         rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
@@ -2377,17 +2361,31 @@ static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
                          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
                          (power_state->v1.ucNonClockStateIndex *
                           power_info->pplib.ucNonClockSize));
-                for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
-                        clock_info = (union pplib_clock_info *)
-                                (mode_info->atom_context->bios + data_offset +
-                                 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
-                                 (power_state->v1.ucClockStateIndices[j] *
-                                  power_info->pplib.ucClockInfoSize));
-                        valid = radeon_atombios_parse_pplib_clock_info(rdev,
-                                                                       state_index, mode_index,
-                                                                       clock_info);
-                        if (valid)
-                                mode_index++;
+                rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
+                                                             ((power_info->pplib.ucStateEntrySize - 1) ?
+                                                              (power_info->pplib.ucStateEntrySize - 1) : 1),
+                                                             GFP_KERNEL);
+                if (!rdev->pm.power_state[i].clock_info)
+                        return state_index;
+                if (power_info->pplib.ucStateEntrySize - 1) {
+                        for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
+                                clock_info = (union pplib_clock_info *)
+                                        (mode_info->atom_context->bios + data_offset +
+                                         le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
+                                         (power_state->v1.ucClockStateIndices[j] *
+                                          power_info->pplib.ucClockInfoSize));
+                                valid = radeon_atombios_parse_pplib_clock_info(rdev,
+                                                                               state_index, mode_index,
+                                                                               clock_info);
+                                if (valid)
+                                        mode_index++;
+                        }
+                } else {
+                        rdev->pm.power_state[state_index].clock_info[0].mclk =
+                                rdev->clock.default_mclk;
+                        rdev->pm.power_state[state_index].clock_info[0].sclk =
+                                rdev->clock.default_sclk;
+                        mode_index++;
                 }
                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
                 if (mode_index) {
@@ -2456,18 +2454,32 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
                 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
-                for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
-                        clock_array_index = power_state->v2.clockInfoIndex[j];
-                        /* XXX this might be an inagua bug... */
-                        if (clock_array_index >= clock_info_array->ucNumEntries)
-                                continue;
-                        clock_info = (union pplib_clock_info *)
-                                &clock_info_array->clockInfo[clock_array_index];
-                        valid = radeon_atombios_parse_pplib_clock_info(rdev,
-                                                                       state_index, mode_index,
-                                                                       clock_info);
-                        if (valid)
-                                mode_index++;
+                rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
+                                                             (power_state->v2.ucNumDPMLevels ?
+                                                              power_state->v2.ucNumDPMLevels : 1),
+                                                             GFP_KERNEL);
+                if (!rdev->pm.power_state[i].clock_info)
+                        return state_index;
+                if (power_state->v2.ucNumDPMLevels) {
+                        for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
+                                clock_array_index = power_state->v2.clockInfoIndex[j];
+                                /* XXX this might be an inagua bug... */
+                                if (clock_array_index >= clock_info_array->ucNumEntries)
+                                        continue;
+                                clock_info = (union pplib_clock_info *)
+                                        &clock_info_array->clockInfo[clock_array_index];
+                                valid = radeon_atombios_parse_pplib_clock_info(rdev,
+                                                                               state_index, mode_index,
+                                                                               clock_info);
+                                if (valid)
+                                        mode_index++;
+                        }
+                } else {
+                        rdev->pm.power_state[state_index].clock_info[0].mclk =
+                                rdev->clock.default_mclk;
+                        rdev->pm.power_state[state_index].clock_info[0].sclk =
+                                rdev->clock.default_sclk;
+                        mode_index++;
                 }
                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
                 if (mode_index) {
@@ -2524,19 +2536,23 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
         } else {
                 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
                 if (rdev->pm.power_state) {
-                        /* add the default mode */
-                        rdev->pm.power_state[state_index].type =
-                                POWER_STATE_TYPE_DEFAULT;
-                        rdev->pm.power_state[state_index].num_clock_modes = 1;
-                        rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
-                        rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
-                        rdev->pm.power_state[state_index].default_clock_mode =
-                                &rdev->pm.power_state[state_index].clock_info[0];
-                        rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
-                        rdev->pm.power_state[state_index].pcie_lanes = 16;
-                        rdev->pm.default_power_state_index = state_index;
-                        rdev->pm.power_state[state_index].flags = 0;
-                        state_index++;
+                        rdev->pm.power_state[0].clock_info =
+                                kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
+                        if (rdev->pm.power_state[0].clock_info) {
+                                /* add the default mode */
+                                rdev->pm.power_state[state_index].type =
+                                        POWER_STATE_TYPE_DEFAULT;
+                                rdev->pm.power_state[state_index].num_clock_modes = 1;
+                                rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
+                                rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
+                                rdev->pm.power_state[state_index].default_clock_mode =
+                                        &rdev->pm.power_state[state_index].clock_info[0];
+                                rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
+                                rdev->pm.power_state[state_index].pcie_lanes = 16;
+                                rdev->pm.default_power_state_index = state_index;
+                                rdev->pm.power_state[state_index].flags = 0;
+                                state_index++;
+                        }
                 }
         }
 
diff --git a/drivers/gpu/drm/radeon/radeon_benchmark.c b/drivers/gpu/drm/radeon/radeon_benchmark.c
index 5cafc90de7f8..17e1a9b2d8fb 100644
--- a/drivers/gpu/drm/radeon/radeon_benchmark.c
+++ b/drivers/gpu/drm/radeon/radeon_benchmark.c
@@ -98,7 +98,7 @@ static void radeon_benchmark_move(struct radeon_device *rdev, unsigned size,
         struct radeon_bo *sobj = NULL;
         uint64_t saddr, daddr;
         int r, n;
-        unsigned int time;
+        int time;
 
         n = RADEON_BENCHMARK_ITERATIONS;
         r = radeon_bo_create(rdev, size, PAGE_SIZE, true, sdomain, &sobj);
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 8bf83c4b4147..81fc100be7e1 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -2563,14 +2563,17 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev)
 
         /* allocate 2 power states */
         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
-        if (!rdev->pm.power_state) {
-                rdev->pm.default_power_state_index = state_index;
-                rdev->pm.num_power_states = 0;
-
-                rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
-                rdev->pm.current_clock_mode_index = 0;
-                return;
-        }
+        if (rdev->pm.power_state) {
+                /* allocate 1 clock mode per state */
+                rdev->pm.power_state[0].clock_info =
+                        kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
+                rdev->pm.power_state[1].clock_info =
+                        kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
+                if (!rdev->pm.power_state[0].clock_info ||
+                    !rdev->pm.power_state[1].clock_info)
+                        goto pm_failed;
+        } else
+                goto pm_failed;
 
         /* check for a thermal chip */
         offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
@@ -2735,6 +2738,14 @@ default_mode:
 
         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
         rdev->pm.current_clock_mode_index = 0;
+        return;
+
+pm_failed:
+        rdev->pm.default_power_state_index = state_index;
+        rdev->pm.num_power_states = 0;
+
+        rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
+        rdev->pm.current_clock_mode_index = 0;
 }
 
 void radeon_external_tmds_setup(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index fae00c0d75aa..29afd71e0840 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -93,7 +93,7 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
 {
         struct drm_radeon_cs *cs = data;
         uint64_t *chunk_array_ptr;
-        unsigned size, i;
+        unsigned size, i, flags = 0;
 
         if (!cs->num_chunks) {
                 return 0;
@@ -140,6 +140,10 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
                         if (p->chunks[i].length_dw == 0)
                                 return -EINVAL;
                 }
+                if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS &&
+                    !p->chunks[i].length_dw) {
+                        return -EINVAL;
+                }
 
                 p->chunks[i].length_dw = user_chunk.length_dw;
                 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
@@ -155,6 +159,9 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
                                                p->chunks[i].user_ptr, size)) {
                                 return -EFAULT;
                         }
+                        if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
+                                flags = p->chunks[i].kdata[0];
+                        }
                 } else {
                         p->chunks[i].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
                         p->chunks[i].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
@@ -174,6 +181,8 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
                           p->chunks[p->chunk_ib_idx].length_dw);
                 return -EINVAL;
         }
+
+        p->keep_tiling_flags = (flags & RADEON_CS_KEEP_TILING_FLAGS) != 0;
         return 0;
 }
 
@@ -222,7 +231,7 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
         struct radeon_cs_chunk *ib_chunk;
         int r;
 
-        mutex_lock(&rdev->cs_mutex);
+        radeon_mutex_lock(&rdev->cs_mutex);
         /* initialize parser */
         memset(&parser, 0, sizeof(struct radeon_cs_parser));
         parser.filp = filp;
@@ -233,14 +242,14 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
         if (r) {
                 DRM_ERROR("Failed to initialize parser !\n");
                 radeon_cs_parser_fini(&parser, r);
-                mutex_unlock(&rdev->cs_mutex);
+                radeon_mutex_unlock(&rdev->cs_mutex);
                 return r;
         }
         r =  radeon_ib_get(rdev, &parser.ib);
         if (r) {
                 DRM_ERROR("Failed to get ib !\n");
                 radeon_cs_parser_fini(&parser, r);
-                mutex_unlock(&rdev->cs_mutex);
+                radeon_mutex_unlock(&rdev->cs_mutex);
                 return r;
         }
         r = radeon_cs_parser_relocs(&parser);
@@ -248,7 +257,7 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
                 if (r != -ERESTARTSYS)
                         DRM_ERROR("Failed to parse relocation %d!\n", r);
                 radeon_cs_parser_fini(&parser, r);
-                mutex_unlock(&rdev->cs_mutex);
+                radeon_mutex_unlock(&rdev->cs_mutex);
                 return r;
         }
         /* Copy the packet into the IB, the parser will read from the
@@ -260,14 +269,14 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
         if (r || parser.parser_error) {
                 DRM_ERROR("Invalid command stream !\n");
                 radeon_cs_parser_fini(&parser, r);
-                mutex_unlock(&rdev->cs_mutex);
+                radeon_mutex_unlock(&rdev->cs_mutex);
                 return r;
         }
         r = radeon_cs_finish_pages(&parser);
         if (r) {
                 DRM_ERROR("Invalid command stream !\n");
                 radeon_cs_parser_fini(&parser, r);
-                mutex_unlock(&rdev->cs_mutex);
+                radeon_mutex_unlock(&rdev->cs_mutex);
                 return r;
         }
         r = radeon_ib_schedule(rdev, parser.ib);
@@ -275,7 +284,7 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
                 DRM_ERROR("Failed to schedule IB !\n");
         }
         radeon_cs_parser_fini(&parser, r);
-        mutex_unlock(&rdev->cs_mutex);
+        radeon_mutex_unlock(&rdev->cs_mutex);
         return r;
 }
 
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index c33bc914d93d..c4d00a171411 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -716,7 +716,7 @@ int radeon_device_init(struct radeon_device *rdev,
 
         /* mutex initialization are all done here so we
          * can recall function without having locking issues */
-        mutex_init(&rdev->cs_mutex);
+        radeon_mutex_init(&rdev->cs_mutex);
         mutex_init(&rdev->ib_pool.mutex);
         mutex_init(&rdev->cp.mutex);
         mutex_init(&rdev->dc_hw_i2c_mutex);
@@ -955,6 +955,9 @@ int radeon_gpu_reset(struct radeon_device *rdev)
         int r;
         int resched;
 
+        /* Prevent CS ioctl from interfering */
+        radeon_mutex_lock(&rdev->cs_mutex);
+
         radeon_save_bios_scratch_regs(rdev);
         /* block TTM */
         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
@@ -967,10 +970,15 @@ int radeon_gpu_reset(struct radeon_device *rdev)
                 radeon_restore_bios_scratch_regs(rdev);
                 drm_helper_resume_force_mode(rdev->ddev);
                 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
-                return 0;
         }
-        /* bad news, how to tell it to userspace ? */
-        dev_info(rdev->dev, "GPU reset failed\n");
+
+        radeon_mutex_unlock(&rdev->cs_mutex);
+
+        if (r) {
+                /* bad news, how to tell it to userspace ? */
+                dev_info(rdev->dev, "GPU reset failed\n");
+        }
+
         return r;
 }
 
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index a0b35e909489..71499fc3daf5 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -53,9 +53,10 @@
  *   2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
  *   2.10.0 - fusion 2D tiling
  *   2.11.0 - backend map, initial compute support for the CS checker
+ *   2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
  */
 #define KMS_DRIVER_MAJOR        2
-#define KMS_DRIVER_MINOR        11
+#define KMS_DRIVER_MINOR        12
 #define KMS_DRIVER_PATCHLEVEL   0
 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
 int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 41a5d48e657b..daadf2111040 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -991,12 +991,6 @@ static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
                                    struct drm_display_mode *mode,
                                    struct drm_display_mode *adjusted_mode)
 {
-        struct drm_device *dev = crtc->dev;
-        struct radeon_device *rdev = dev->dev_private;
-
-        /* adjust pm to upcoming mode change */
-        radeon_pm_compute_clocks(rdev);
-
         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
                 return false;
         return true;
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 6fabe89fa6a1..78a665bd9519 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -53,6 +53,24 @@ static void radeon_pm_set_clocks(struct radeon_device *rdev);
 
 #define ACPI_AC_CLASS           "ac_adapter"
 
+int radeon_pm_get_type_index(struct radeon_device *rdev,
+                             enum radeon_pm_state_type ps_type,
+                             int instance)
+{
+        int i;
+        int found_instance = -1;
+
+        for (i = 0; i < rdev->pm.num_power_states; i++) {
+                if (rdev->pm.power_state[i].type == ps_type) {
+                        found_instance++;
+                        if (found_instance == instance)
+                                return i;
+                }
+        }
+        /* return default if no match */
+        return rdev->pm.default_power_state_index;
+}
+
 #ifdef CONFIG_ACPI
 static int radeon_acpi_event(struct notifier_block *nb,
                              unsigned long val,
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 617b64678fc6..0bb0f5f713e6 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -574,10 +574,16 @@ retry:
                 return ret;
 
         spin_lock(&glob->lru_lock);
+
+        if (unlikely(list_empty(&bo->ddestroy))) {
+                spin_unlock(&glob->lru_lock);
+                return 0;
+        }
+
         ret = ttm_bo_reserve_locked(bo, interruptible,
                                     no_wait_reserve, false, 0);
 
-        if (unlikely(ret != 0) || list_empty(&bo->ddestroy)) {
+        if (unlikely(ret != 0)) {
                 spin_unlock(&glob->lru_lock);
                 return ret;
         }
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index 03daefa73397..880e285d7578 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -105,6 +105,10 @@ int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
         struct vmw_dma_buffer *dmabuf = NULL;
         int ret;
 
+        /* A lot of the code assumes this */
+        if (handle && (width != 64 || height != 64))
+                return -EINVAL;
+
         if (handle) {
                 ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
                                                      handle, &surface);
@@ -410,8 +414,9 @@ static int do_surface_dirty_sou(struct vmw_private *dev_priv,
         top = clips->y1;
         bottom = clips->y2;
 
-        clips_ptr = clips;
-        for (i = 1; i < num_clips; i++, clips_ptr += inc) {
+        /* skip the first clip rect */
+        for (i = 1, clips_ptr = clips + inc;
+             i < num_clips; i++, clips_ptr += inc) {
                 left = min_t(int, left, (int)clips_ptr->x1);
                 right = max_t(int, right, (int)clips_ptr->x2);
                 top = min_t(int, top, (int)clips_ptr->y1);
@@ -1323,7 +1328,10 @@ int vmw_kms_close(struct vmw_private *dev_priv)
          * drm_encoder_cleanup which takes the lock we deadlock.
          */
         drm_mode_config_cleanup(dev_priv->dev);
-        vmw_kms_close_legacy_display_system(dev_priv);
+        if (dev_priv->sou_priv)
+                vmw_kms_close_screen_object_display(dev_priv);
+        else
+                vmw_kms_close_legacy_display_system(dev_priv);
         return 0;
 }