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authorAlex Deucher <alexander.deucher@amd.com>2013-06-25 17:56:16 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-06-27 19:40:05 -0400
commita9e61410921bcc1aa8f594ffa6301d5baba90f3b (patch)
tree82c267bd9854a8d0cb7b3a8ccc8693194ecfd236 /drivers/gpu/drm
parenta0ceada6b4da18e8539bc3229adae3dc9b05d9a2 (diff)
drm/radeon/kms: add dpm support for SI (v7)
This adds dpm support for SI asics. This includes: - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2/gen3 switching - power containment - shader power scaling Set radeon.dpm=1 to enable. v2: enable hainan support, rebase v3: guard acpi stuff v4: fix 64 bit math v5: fix 64 bit div harder v6: fix thermal interrupt check noticed by Jerome v7: attempt fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/radeon/Makefile2
-rw-r--r--drivers/gpu/drm/radeon/atombios.h3
-rw-r--r--drivers/gpu/drm/radeon/ni_dpm.c22
-rw-r--r--drivers/gpu/drm/radeon/ni_dpm.h7
-rw-r--r--drivers/gpu/drm/radeon/ppsmc.h13
-rw-r--r--drivers/gpu/drm/radeon/r600_dpm.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c14
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h9
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon_ucode.h15
-rw-r--r--drivers/gpu/drm/radeon/rv770_dpm.h1
-rw-r--r--drivers/gpu/drm/radeon/si.c48
-rw-r--r--drivers/gpu/drm/radeon/si_dpm.c6329
-rw-r--r--drivers/gpu/drm/radeon/si_dpm.h227
-rw-r--r--drivers/gpu/drm/radeon/si_smc.c284
-rw-r--r--drivers/gpu/drm/radeon/sid.h312
-rw-r--r--drivers/gpu/drm/radeon/sislands_smc.h397
18 files changed, 7665 insertions, 25 deletions
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 32d1c7fcad24..c3df52c1a60c 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -79,7 +79,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
79 si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \ 79 si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \
80 r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \ 80 r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \
81 rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \ 81 rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \
82 trinity_smc.o ni_dpm.o 82 trinity_smc.o ni_dpm.o si_smc.o si_dpm.o
83 83
84radeon-$(CONFIG_COMPAT) += radeon_ioc32.o 84radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
85radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o 85radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index 7ba95881fbf3..16b120c3f144 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -7763,6 +7763,9 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER
7763#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature. 7763#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature.
7764#define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state. 7764#define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state.
7765#define ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE 0x00040000 // Does the driver supports new CAC voltage table. 7765#define ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE 0x00040000 // Does the driver supports new CAC voltage table.
7766#define ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY 0x00080000 // Does the driver supports revert GPIO5 polarity.
7767#define ATOM_PP_PLATFORM_CAP_OUTPUT_THERMAL2GPIO17 0x00100000 // Does the driver supports thermal2GPIO17.
7768#define ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE 0x00200000 // Does the driver supports VR HOT GPIO Configurable.
7766 7769
7767typedef struct _ATOM_PPLIB_POWERPLAYTABLE 7770typedef struct _ATOM_PPLIB_POWERPLAYTABLE
7768{ 7771{
diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c
index 8e6b23aecc7f..649d94979bb2 100644
--- a/drivers/gpu/drm/radeon/ni_dpm.c
+++ b/drivers/gpu/drm/radeon/ni_dpm.c
@@ -719,7 +719,7 @@ static const u32 cayman_sysls_enable[] =
719struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 719struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
720struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 720struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
721 721
722static struct ni_power_info *ni_get_pi(struct radeon_device *rdev) 722struct ni_power_info *ni_get_pi(struct radeon_device *rdev)
723{ 723{
724 struct ni_power_info *pi = rdev->pm.dpm.priv; 724 struct ni_power_info *pi = rdev->pm.dpm.priv;
725 725
@@ -1471,8 +1471,8 @@ static int ni_populate_smc_tdp_limits(struct radeon_device *rdev,
1471 return 0; 1471 return 0;
1472} 1472}
1473 1473
1474static int ni_copy_and_switch_arb_sets(struct radeon_device *rdev, 1474int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
1475 u32 arb_freq_src, u32 arb_freq_dest) 1475 u32 arb_freq_src, u32 arb_freq_dest)
1476{ 1476{
1477 u32 mc_arb_dram_timing; 1477 u32 mc_arb_dram_timing;
1478 u32 mc_arb_dram_timing2; 1478 u32 mc_arb_dram_timing2;
@@ -3488,8 +3488,8 @@ void ni_dpm_setup_asic(struct radeon_device *rdev)
3488 rv770_enable_acpi_pm(rdev); 3488 rv770_enable_acpi_pm(rdev);
3489} 3489}
3490 3490
3491static void ni_update_current_ps(struct radeon_device *rdev, 3491void ni_update_current_ps(struct radeon_device *rdev,
3492 struct radeon_ps *rps) 3492 struct radeon_ps *rps)
3493{ 3493{
3494 struct ni_ps *new_ps = ni_get_ps(rps); 3494 struct ni_ps *new_ps = ni_get_ps(rps);
3495 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3495 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
@@ -3500,8 +3500,8 @@ static void ni_update_current_ps(struct radeon_device *rdev,
3500 eg_pi->current_rps.ps_priv = &ni_pi->current_ps; 3500 eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3501} 3501}
3502 3502
3503static void ni_update_requested_ps(struct radeon_device *rdev, 3503void ni_update_requested_ps(struct radeon_device *rdev,
3504 struct radeon_ps *rps) 3504 struct radeon_ps *rps)
3505{ 3505{
3506 struct ni_ps *new_ps = ni_get_ps(rps); 3506 struct ni_ps *new_ps = ni_get_ps(rps);
3507 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3507 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
@@ -4192,8 +4192,12 @@ void ni_dpm_print_power_state(struct radeon_device *rdev,
4192 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 4192 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
4193 for (i = 0; i < ps->performance_level_count; i++) { 4193 for (i = 0; i < ps->performance_level_count; i++) {
4194 pl = &ps->performance_levels[i]; 4194 pl = &ps->performance_levels[i];
4195 printk("\t\tpower level 0 sclk: %u mclk: %u vddc: %u vddci: %u\n", 4195 if (rdev->family >= CHIP_TAHITI)
4196 pl->sclk, pl->mclk, pl->vddc, pl->vddci); 4196 printk("\t\tpower level 0 sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
4197 pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
4198 else
4199 printk("\t\tpower level 0 sclk: %u mclk: %u vddc: %u vddci: %u\n",
4200 pl->sclk, pl->mclk, pl->vddc, pl->vddci);
4197 } 4201 }
4198 r600_dpm_print_ps_status(rdev, rps); 4202 r600_dpm_print_ps_status(rdev, rps);
4199} 4203}
diff --git a/drivers/gpu/drm/radeon/ni_dpm.h b/drivers/gpu/drm/radeon/ni_dpm.h
index 59c1692f7838..887442497bff 100644
--- a/drivers/gpu/drm/radeon/ni_dpm.h
+++ b/drivers/gpu/drm/radeon/ni_dpm.h
@@ -231,4 +231,11 @@ struct ni_power_info {
231#define NISLANDS_DPM2_SQ_RAMP_STI_SIZE 0x1E 231#define NISLANDS_DPM2_SQ_RAMP_STI_SIZE 0x1E
232#define NISLANDS_DPM2_SQ_RAMP_LTI_RATIO 0xF 232#define NISLANDS_DPM2_SQ_RAMP_LTI_RATIO 0xF
233 233
234int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
235 u32 arb_freq_src, u32 arb_freq_dest);
236void ni_update_current_ps(struct radeon_device *rdev,
237 struct radeon_ps *rps);
238void ni_update_requested_ps(struct radeon_device *rdev,
239 struct radeon_ps *rps);
240
234#endif 241#endif
diff --git a/drivers/gpu/drm/radeon/ppsmc.h b/drivers/gpu/drm/radeon/ppsmc.h
index 0f6ccce27a35..8fb1113a8fd7 100644
--- a/drivers/gpu/drm/radeon/ppsmc.h
+++ b/drivers/gpu/drm/radeon/ppsmc.h
@@ -26,6 +26,9 @@
26#pragma pack(push, 1) 26#pragma pack(push, 1)
27 27
28#define PPSMC_SWSTATE_FLAG_DC 0x01 28#define PPSMC_SWSTATE_FLAG_DC 0x01
29#define PPSMC_SWSTATE_FLAG_UVD 0x02
30#define PPSMC_SWSTATE_FLAG_VCE 0x04
31#define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
29 32
30#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 33#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
31#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 34#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
@@ -36,17 +39,22 @@
36#define PPSMC_SYSTEMFLAG_GDDR5 0x04 39#define PPSMC_SYSTEMFLAG_GDDR5 0x04
37#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 40#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08
38#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10 41#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10
42#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20
43#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO 0x40
39 44
40#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07 45#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07
41#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08 46#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08
42#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00 47#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00
43#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01 48#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01
49#define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH 0x02
44 50
45#define PPSMC_DISPLAY_WATERMARK_LOW 0 51#define PPSMC_DISPLAY_WATERMARK_LOW 0
46#define PPSMC_DISPLAY_WATERMARK_HIGH 1 52#define PPSMC_DISPLAY_WATERMARK_HIGH 1
47 53
48#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 54#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01
49#define PPSMC_STATEFLAG_POWERBOOST 0x02 55#define PPSMC_STATEFLAG_POWERBOOST 0x02
56#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
57#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40
50 58
51#define PPSMC_Result_OK ((uint8_t)0x01) 59#define PPSMC_Result_OK ((uint8_t)0x01)
52#define PPSMC_Result_Failed ((uint8_t)0xFF) 60#define PPSMC_Result_Failed ((uint8_t)0xFF)
@@ -80,9 +88,14 @@ typedef uint8_t PPSMC_Result;
80#define PPSMC_CACLongTermAvgEnable ((uint8_t)0x6E) 88#define PPSMC_CACLongTermAvgEnable ((uint8_t)0x6E)
81#define PPSMC_CACLongTermAvgDisable ((uint8_t)0x6F) 89#define PPSMC_CACLongTermAvgDisable ((uint8_t)0x6F)
82#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint8_t)0x7A) 90#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint8_t)0x7A)
91#define PPSMC_FlushDataCache ((uint8_t)0x80)
83#define PPSMC_MSG_SetEnabledLevels ((uint8_t)0x82) 92#define PPSMC_MSG_SetEnabledLevels ((uint8_t)0x82)
84#define PPSMC_MSG_SetForcedLevels ((uint8_t)0x83) 93#define PPSMC_MSG_SetForcedLevels ((uint8_t)0x83)
85#define PPSMC_MSG_ResetToDefaults ((uint8_t)0x84) 94#define PPSMC_MSG_ResetToDefaults ((uint8_t)0x84)
95#define PPSMC_MSG_EnableDTE ((uint8_t)0x87)
96#define PPSMC_MSG_DisableDTE ((uint8_t)0x88)
97#define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint8_t)0x96)
98#define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint8_t)0x97)
86 99
87/* TN */ 100/* TN */
88#define PPSMC_MSG_DPM_Config ((uint32_t) 0x102) 101#define PPSMC_MSG_DPM_Config ((uint32_t) 0x102)
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c
index e7684c6d07e3..76368c04f809 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -906,6 +906,7 @@ int r600_parse_extended_power_table(struct radeon_device *rdev)
906 sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE5)) { 906 sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE5)) {
907 rdev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit); 907 rdev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit);
908 rdev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit); 908 rdev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit);
909 rdev->pm.dpm.near_tdp_limit_adjusted = rdev->pm.dpm.near_tdp_limit;
909 rdev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit); 910 rdev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit);
910 if (rdev->pm.dpm.tdp_od_limit) 911 if (rdev->pm.dpm.tdp_od_limit)
911 rdev->pm.dpm.power_control = true; 912 rdev->pm.dpm.power_control = true;
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 9de8ae20bc99..a424949005c9 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1359,6 +1359,7 @@ struct radeon_dpm {
1359 struct radeon_dpm_fan fan; 1359 struct radeon_dpm_fan fan;
1360 u32 tdp_limit; 1360 u32 tdp_limit;
1361 u32 near_tdp_limit; 1361 u32 near_tdp_limit;
1362 u32 near_tdp_limit_adjusted;
1362 u32 sq_ramping_threshold; 1363 u32 sq_ramping_threshold;
1363 u32 cac_leakage; 1364 u32 cac_leakage;
1364 u16 tdp_od_limit; 1365 u16 tdp_od_limit;
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index c20ec37ef2b1..c3df589715a0 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -2262,6 +2262,20 @@ static struct radeon_asic si_asic = {
2262 .set_uvd_clocks = &si_set_uvd_clocks, 2262 .set_uvd_clocks = &si_set_uvd_clocks,
2263 .get_temperature = &si_get_temp, 2263 .get_temperature = &si_get_temp,
2264 }, 2264 },
2265 .dpm = {
2266 .init = &si_dpm_init,
2267 .setup_asic = &si_dpm_setup_asic,
2268 .enable = &si_dpm_enable,
2269 .disable = &si_dpm_disable,
2270 .pre_set_power_state = &si_dpm_pre_set_power_state,
2271 .set_power_state = &si_dpm_set_power_state,
2272 .post_set_power_state = &si_dpm_post_set_power_state,
2273 .display_configuration_changed = &si_dpm_display_configuration_changed,
2274 .fini = &si_dpm_fini,
2275 .get_sclk = &ni_dpm_get_sclk,
2276 .get_mclk = &ni_dpm_get_mclk,
2277 .print_power_state = &ni_dpm_print_power_state,
2278 },
2265 .pflip = { 2279 .pflip = {
2266 .pre_page_flip = &evergreen_pre_page_flip, 2280 .pre_page_flip = &evergreen_pre_page_flip,
2267 .page_flip = &evergreen_page_flip, 2281 .page_flip = &evergreen_page_flip,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 2b4a922716b1..2497d0a02de5 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -658,6 +658,15 @@ u32 si_get_xclk(struct radeon_device *rdev);
658uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); 658uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
659int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 659int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
660int si_get_temp(struct radeon_device *rdev); 660int si_get_temp(struct radeon_device *rdev);
661int si_dpm_init(struct radeon_device *rdev);
662void si_dpm_setup_asic(struct radeon_device *rdev);
663int si_dpm_enable(struct radeon_device *rdev);
664void si_dpm_disable(struct radeon_device *rdev);
665int si_dpm_pre_set_power_state(struct radeon_device *rdev);
666int si_dpm_set_power_state(struct radeon_device *rdev);
667void si_dpm_post_set_power_state(struct radeon_device *rdev);
668void si_dpm_fini(struct radeon_device *rdev);
669void si_dpm_display_configuration_changed(struct radeon_device *rdev);
661 670
662/* DCE8 - CIK */ 671/* DCE8 - CIK */
663void dce8_bandwidth_update(struct radeon_device *rdev); 672void dce8_bandwidth_update(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 2f70c1b195d9..9737baeb711d 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -1096,6 +1096,11 @@ int radeon_pm_init(struct radeon_device *rdev)
1096 case CHIP_CAICOS: 1096 case CHIP_CAICOS:
1097 case CHIP_CAYMAN: 1097 case CHIP_CAYMAN:
1098 case CHIP_ARUBA: 1098 case CHIP_ARUBA:
1099 case CHIP_TAHITI:
1100 case CHIP_PITCAIRN:
1101 case CHIP_VERDE:
1102 case CHIP_OLAND:
1103 case CHIP_HAINAN:
1099 if (radeon_dpm == 1) 1104 if (radeon_dpm == 1)
1100 rdev->pm.pm_method = PM_METHOD_DPM; 1105 rdev->pm.pm_method = PM_METHOD_DPM;
1101 else 1106 else
diff --git a/drivers/gpu/drm/radeon/radeon_ucode.h b/drivers/gpu/drm/radeon/radeon_ucode.h
index 4fe9237af83d..d8b05f7bcf1a 100644
--- a/drivers/gpu/drm/radeon/radeon_ucode.h
+++ b/drivers/gpu/drm/radeon/radeon_ucode.h
@@ -111,4 +111,19 @@
111#define CAYMAN_SMC_INT_VECTOR_START 0xffc0 111#define CAYMAN_SMC_INT_VECTOR_START 0xffc0
112#define CAYMAN_SMC_INT_VECTOR_SIZE 0x0040 112#define CAYMAN_SMC_INT_VECTOR_SIZE 0x0040
113 113
114#define TAHITI_SMC_UCODE_START 0x10000
115#define TAHITI_SMC_UCODE_SIZE 0xf458
116
117#define PITCAIRN_SMC_UCODE_START 0x10000
118#define PITCAIRN_SMC_UCODE_SIZE 0xe9f4
119
120#define VERDE_SMC_UCODE_START 0x10000
121#define VERDE_SMC_UCODE_SIZE 0xebe4
122
123#define OLAND_SMC_UCODE_START 0x10000
124#define OLAND_SMC_UCODE_SIZE 0xe7b4
125
126#define HAINAN_SMC_UCODE_START 0x10000
127#define HAINAN_SMC_UCODE_SIZE 0xe67C
128
114#endif 129#endif
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.h b/drivers/gpu/drm/radeon/rv770_dpm.h
index 7fa14b9557f3..f1e1fcf7f622 100644
--- a/drivers/gpu/drm/radeon/rv770_dpm.h
+++ b/drivers/gpu/drm/radeon/rv770_dpm.h
@@ -144,6 +144,7 @@ struct rv7xx_pl {
144 u16 vddc; 144 u16 vddc;
145 u16 vddci; /* eg+ only */ 145 u16 vddci; /* eg+ only */
146 u32 flags; 146 u32 flags;
147 enum radeon_pcie_gen pcie_gen; /* si+ only */
147}; 148};
148 149
149struct rv7xx_ps { 150struct rv7xx_ps {
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 7d797f4db360..6c8caaf7a715 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -41,26 +41,31 @@ MODULE_FIRMWARE("radeon/TAHITI_me.bin");
41MODULE_FIRMWARE("radeon/TAHITI_ce.bin"); 41MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
42MODULE_FIRMWARE("radeon/TAHITI_mc.bin"); 42MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
43MODULE_FIRMWARE("radeon/TAHITI_rlc.bin"); 43MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
44MODULE_FIRMWARE("radeon/TAHITI_smc.bin");
44MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin"); 45MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
45MODULE_FIRMWARE("radeon/PITCAIRN_me.bin"); 46MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
46MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin"); 47MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
47MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin"); 48MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
48MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin"); 49MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
50MODULE_FIRMWARE("radeon/PITCAIRN_smc.bin");
49MODULE_FIRMWARE("radeon/VERDE_pfp.bin"); 51MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
50MODULE_FIRMWARE("radeon/VERDE_me.bin"); 52MODULE_FIRMWARE("radeon/VERDE_me.bin");
51MODULE_FIRMWARE("radeon/VERDE_ce.bin"); 53MODULE_FIRMWARE("radeon/VERDE_ce.bin");
52MODULE_FIRMWARE("radeon/VERDE_mc.bin"); 54MODULE_FIRMWARE("radeon/VERDE_mc.bin");
53MODULE_FIRMWARE("radeon/VERDE_rlc.bin"); 55MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
56MODULE_FIRMWARE("radeon/VERDE_smc.bin");
54MODULE_FIRMWARE("radeon/OLAND_pfp.bin"); 57MODULE_FIRMWARE("radeon/OLAND_pfp.bin");
55MODULE_FIRMWARE("radeon/OLAND_me.bin"); 58MODULE_FIRMWARE("radeon/OLAND_me.bin");
56MODULE_FIRMWARE("radeon/OLAND_ce.bin"); 59MODULE_FIRMWARE("radeon/OLAND_ce.bin");
57MODULE_FIRMWARE("radeon/OLAND_mc.bin"); 60MODULE_FIRMWARE("radeon/OLAND_mc.bin");
58MODULE_FIRMWARE("radeon/OLAND_rlc.bin"); 61MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
62MODULE_FIRMWARE("radeon/OLAND_smc.bin");
59MODULE_FIRMWARE("radeon/HAINAN_pfp.bin"); 63MODULE_FIRMWARE("radeon/HAINAN_pfp.bin");
60MODULE_FIRMWARE("radeon/HAINAN_me.bin"); 64MODULE_FIRMWARE("radeon/HAINAN_me.bin");
61MODULE_FIRMWARE("radeon/HAINAN_ce.bin"); 65MODULE_FIRMWARE("radeon/HAINAN_ce.bin");
62MODULE_FIRMWARE("radeon/HAINAN_mc.bin"); 66MODULE_FIRMWARE("radeon/HAINAN_mc.bin");
63MODULE_FIRMWARE("radeon/HAINAN_rlc.bin"); 67MODULE_FIRMWARE("radeon/HAINAN_rlc.bin");
68MODULE_FIRMWARE("radeon/HAINAN_smc.bin");
64 69
65static void si_pcie_gen3_enable(struct radeon_device *rdev); 70static void si_pcie_gen3_enable(struct radeon_device *rdev);
66static void si_program_aspm(struct radeon_device *rdev); 71static void si_program_aspm(struct radeon_device *rdev);
@@ -1540,6 +1545,7 @@ static int si_init_microcode(struct radeon_device *rdev)
1540 const char *chip_name; 1545 const char *chip_name;
1541 const char *rlc_chip_name; 1546 const char *rlc_chip_name;
1542 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size; 1547 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
1548 size_t smc_req_size;
1543 char fw_name[30]; 1549 char fw_name[30];
1544 int err; 1550 int err;
1545 1551
@@ -1561,6 +1567,7 @@ static int si_init_microcode(struct radeon_device *rdev)
1561 ce_req_size = SI_CE_UCODE_SIZE * 4; 1567 ce_req_size = SI_CE_UCODE_SIZE * 4;
1562 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 1568 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1563 mc_req_size = SI_MC_UCODE_SIZE * 4; 1569 mc_req_size = SI_MC_UCODE_SIZE * 4;
1570 smc_req_size = ALIGN(TAHITI_SMC_UCODE_SIZE, 4);
1564 break; 1571 break;
1565 case CHIP_PITCAIRN: 1572 case CHIP_PITCAIRN:
1566 chip_name = "PITCAIRN"; 1573 chip_name = "PITCAIRN";
@@ -1570,6 +1577,7 @@ static int si_init_microcode(struct radeon_device *rdev)
1570 ce_req_size = SI_CE_UCODE_SIZE * 4; 1577 ce_req_size = SI_CE_UCODE_SIZE * 4;
1571 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 1578 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1572 mc_req_size = SI_MC_UCODE_SIZE * 4; 1579 mc_req_size = SI_MC_UCODE_SIZE * 4;
1580 smc_req_size = ALIGN(PITCAIRN_SMC_UCODE_SIZE, 4);
1573 break; 1581 break;
1574 case CHIP_VERDE: 1582 case CHIP_VERDE:
1575 chip_name = "VERDE"; 1583 chip_name = "VERDE";
@@ -1579,6 +1587,7 @@ static int si_init_microcode(struct radeon_device *rdev)
1579 ce_req_size = SI_CE_UCODE_SIZE * 4; 1587 ce_req_size = SI_CE_UCODE_SIZE * 4;
1580 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 1588 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1581 mc_req_size = SI_MC_UCODE_SIZE * 4; 1589 mc_req_size = SI_MC_UCODE_SIZE * 4;
1590 smc_req_size = ALIGN(VERDE_SMC_UCODE_SIZE, 4);
1582 break; 1591 break;
1583 case CHIP_OLAND: 1592 case CHIP_OLAND:
1584 chip_name = "OLAND"; 1593 chip_name = "OLAND";
@@ -1588,6 +1597,7 @@ static int si_init_microcode(struct radeon_device *rdev)
1588 ce_req_size = SI_CE_UCODE_SIZE * 4; 1597 ce_req_size = SI_CE_UCODE_SIZE * 4;
1589 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 1598 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1590 mc_req_size = OLAND_MC_UCODE_SIZE * 4; 1599 mc_req_size = OLAND_MC_UCODE_SIZE * 4;
1600 smc_req_size = ALIGN(OLAND_SMC_UCODE_SIZE, 4);
1591 break; 1601 break;
1592 case CHIP_HAINAN: 1602 case CHIP_HAINAN:
1593 chip_name = "HAINAN"; 1603 chip_name = "HAINAN";
@@ -1597,6 +1607,7 @@ static int si_init_microcode(struct radeon_device *rdev)
1597 ce_req_size = SI_CE_UCODE_SIZE * 4; 1607 ce_req_size = SI_CE_UCODE_SIZE * 4;
1598 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 1608 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1599 mc_req_size = OLAND_MC_UCODE_SIZE * 4; 1609 mc_req_size = OLAND_MC_UCODE_SIZE * 4;
1610 smc_req_size = ALIGN(HAINAN_SMC_UCODE_SIZE, 4);
1600 break; 1611 break;
1601 default: BUG(); 1612 default: BUG();
1602 } 1613 }
@@ -1659,6 +1670,17 @@ static int si_init_microcode(struct radeon_device *rdev)
1659 err = -EINVAL; 1670 err = -EINVAL;
1660 } 1671 }
1661 1672
1673 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
1674 err = request_firmware(&rdev->smc_fw, fw_name, &pdev->dev);
1675 if (err)
1676 goto out;
1677 if (rdev->smc_fw->size != smc_req_size) {
1678 printk(KERN_ERR
1679 "si_smc: Bogus length %zu in firmware \"%s\"\n",
1680 rdev->smc_fw->size, fw_name);
1681 err = -EINVAL;
1682 }
1683
1662out: 1684out:
1663 platform_device_unregister(pdev); 1685 platform_device_unregister(pdev);
1664 1686
@@ -1677,6 +1699,8 @@ out:
1677 rdev->rlc_fw = NULL; 1699 rdev->rlc_fw = NULL;
1678 release_firmware(rdev->mc_fw); 1700 release_firmware(rdev->mc_fw);
1679 rdev->mc_fw = NULL; 1701 rdev->mc_fw = NULL;
1702 release_firmware(rdev->smc_fw);
1703 rdev->smc_fw = NULL;
1680 } 1704 }
1681 return err; 1705 return err;
1682} 1706}
@@ -5420,6 +5444,7 @@ int si_irq_set(struct radeon_device *rdev)
5420 u32 grbm_int_cntl = 0; 5444 u32 grbm_int_cntl = 0;
5421 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; 5445 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
5422 u32 dma_cntl, dma_cntl1; 5446 u32 dma_cntl, dma_cntl1;
5447 u32 thermal_int = 0;
5423 5448
5424 if (!rdev->irq.installed) { 5449 if (!rdev->irq.installed) {
5425 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 5450 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
@@ -5445,6 +5470,9 @@ int si_irq_set(struct radeon_device *rdev)
5445 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; 5470 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
5446 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; 5471 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
5447 5472
5473 thermal_int = RREG32(CG_THERMAL_INT) &
5474 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
5475
5448 /* enable CP interrupts on all rings */ 5476 /* enable CP interrupts on all rings */
5449 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 5477 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
5450 DRM_DEBUG("si_irq_set: sw int gfx\n"); 5478 DRM_DEBUG("si_irq_set: sw int gfx\n");
@@ -5531,6 +5559,11 @@ int si_irq_set(struct radeon_device *rdev)
5531 5559
5532 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 5560 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
5533 5561
5562 if (rdev->irq.dpm_thermal) {
5563 DRM_DEBUG("dpm thermal\n");
5564 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
5565 }
5566
5534 if (rdev->num_crtc >= 2) { 5567 if (rdev->num_crtc >= 2) {
5535 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 5568 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
5536 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 5569 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
@@ -5566,6 +5599,8 @@ int si_irq_set(struct radeon_device *rdev)
5566 WREG32(DC_HPD6_INT_CONTROL, hpd6); 5599 WREG32(DC_HPD6_INT_CONTROL, hpd6);
5567 } 5600 }
5568 5601
5602 WREG32(CG_THERMAL_INT, thermal_int);
5603
5569 return 0; 5604 return 0;
5570} 5605}
5571 5606
@@ -5730,6 +5765,7 @@ int si_irq_process(struct radeon_device *rdev)
5730 u32 src_id, src_data, ring_id; 5765 u32 src_id, src_data, ring_id;
5731 u32 ring_index; 5766 u32 ring_index;
5732 bool queue_hotplug = false; 5767 bool queue_hotplug = false;
5768 bool queue_thermal = false;
5733 5769
5734 if (!rdev->ih.enabled || rdev->shutdown) 5770 if (!rdev->ih.enabled || rdev->shutdown)
5735 return IRQ_NONE; 5771 return IRQ_NONE;
@@ -6000,6 +6036,16 @@ restart_ih:
6000 DRM_DEBUG("IH: DMA trap\n"); 6036 DRM_DEBUG("IH: DMA trap\n");
6001 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 6037 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
6002 break; 6038 break;
6039 case 230: /* thermal low to high */
6040 DRM_DEBUG("IH: thermal low to high\n");
6041 rdev->pm.dpm.thermal.high_to_low = false;
6042 queue_thermal = true;
6043 break;
6044 case 231: /* thermal high to low */
6045 DRM_DEBUG("IH: thermal high to low\n");
6046 rdev->pm.dpm.thermal.high_to_low = true;
6047 queue_thermal = true;
6048 break;
6003 case 233: /* GUI IDLE */ 6049 case 233: /* GUI IDLE */
6004 DRM_DEBUG("IH: GUI idle\n"); 6050 DRM_DEBUG("IH: GUI idle\n");
6005 break; 6051 break;
@@ -6018,6 +6064,8 @@ restart_ih:
6018 } 6064 }
6019 if (queue_hotplug) 6065 if (queue_hotplug)
6020 schedule_work(&rdev->hotplug_work); 6066 schedule_work(&rdev->hotplug_work);
6067 if (queue_thermal && rdev->pm.dpm_enabled)
6068 schedule_work(&rdev->pm.dpm.thermal.work);
6021 rdev->ih.rptr = rptr; 6069 rdev->ih.rptr = rptr;
6022 WREG32(IH_RB_RPTR, rdev->ih.rptr); 6070 WREG32(IH_RB_RPTR, rdev->ih.rptr);
6023 atomic_set(&rdev->ih.lock, 0); 6071 atomic_set(&rdev->ih.lock, 0);
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
new file mode 100644
index 000000000000..32d03f195f35
--- /dev/null
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -0,0 +1,6329 @@
1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "drmP.h"
25#include "radeon.h"
26#include "sid.h"
27#include "r600_dpm.h"
28#include "si_dpm.h"
29#include "atom.h"
30#include <linux/math64.h>
31
32#define MC_CG_ARB_FREQ_F0 0x0a
33#define MC_CG_ARB_FREQ_F1 0x0b
34#define MC_CG_ARB_FREQ_F2 0x0c
35#define MC_CG_ARB_FREQ_F3 0x0d
36
37#define SMC_RAM_END 0x20000
38
39#define DDR3_DRAM_ROWS 0x2000
40
41#define SCLK_MIN_DEEPSLEEP_FREQ 1350
42
43static const struct si_cac_config_reg cac_weights_tahiti[] =
44{
45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
105 { 0xFFFFFFFF }
106};
107
108static const struct si_cac_config_reg lcac_tahiti[] =
109{
110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
196 { 0xFFFFFFFF }
197
198};
199
200static const struct si_cac_config_reg cac_override_tahiti[] =
201{
202 { 0xFFFFFFFF }
203};
204
205static const struct si_powertune_data powertune_data_tahiti =
206{
207 ((1 << 16) | 27027),
208 6,
209 0,
210 4,
211 95,
212 {
213 0UL,
214 0UL,
215 4521550UL,
216 309631529UL,
217 -1270850L,
218 4513710L,
219 40
220 },
221 595000000UL,
222 12,
223 {
224 0,
225 0,
226 0,
227 0,
228 0,
229 0,
230 0,
231 0
232 },
233 true
234};
235
236static const struct si_dte_data dte_data_tahiti =
237{
238 { 1159409, 0, 0, 0, 0 },
239 { 777, 0, 0, 0, 0 },
240 2,
241 54000,
242 127000,
243 25,
244 2,
245 10,
246 13,
247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
250 85,
251 false
252};
253
254static const struct si_dte_data dte_data_tahiti_le =
255{
256 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
257 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
258 0x5,
259 0xAFC8,
260 0x64,
261 0x32,
262 1,
263 0,
264 0x10,
265 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
266 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
267 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
268 85,
269 true
270};
271
272static const struct si_dte_data dte_data_tahiti_pro =
273{
274 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
275 { 0x0, 0x0, 0x0, 0x0, 0x0 },
276 5,
277 45000,
278 100,
279 0xA,
280 1,
281 0,
282 0x10,
283 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
284 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
285 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
286 90,
287 true
288};
289
290static const struct si_dte_data dte_data_new_zealand =
291{
292 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
293 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
294 0x5,
295 0xAFC8,
296 0x69,
297 0x32,
298 1,
299 0,
300 0x10,
301 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
302 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
303 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
304 85,
305 true
306};
307
308static const struct si_dte_data dte_data_aruba_pro =
309{
310 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
311 { 0x0, 0x0, 0x0, 0x0, 0x0 },
312 5,
313 45000,
314 100,
315 0xA,
316 1,
317 0,
318 0x10,
319 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
320 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
321 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
322 90,
323 true
324};
325
326static const struct si_dte_data dte_data_malta =
327{
328 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
329 { 0x0, 0x0, 0x0, 0x0, 0x0 },
330 5,
331 45000,
332 100,
333 0xA,
334 1,
335 0,
336 0x10,
337 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
338 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
339 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
340 90,
341 true
342};
343
344struct si_cac_config_reg cac_weights_pitcairn[] =
345{
346 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
347 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
348 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
349 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
350 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
351 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
352 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
353 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
354 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
355 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
356 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
357 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
358 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
359 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
360 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
361 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
362 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
363 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
364 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
365 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
366 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
367 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
368 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
369 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
370 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
371 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
372 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
373 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
374 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
375 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
376 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
377 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
378 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
379 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
380 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
381 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
382 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
383 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
384 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
385 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
386 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
387 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
388 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
389 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
390 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
391 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
392 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
393 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
394 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
395 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
396 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
397 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
398 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
399 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
400 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
401 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
402 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
403 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
404 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
405 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
406 { 0xFFFFFFFF }
407};
408
409static const struct si_cac_config_reg lcac_pitcairn[] =
410{
411 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
412 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
413 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
414 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
415 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
416 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
417 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
418 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
419 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
420 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
421 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
422 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
423 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
424 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
425 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
426 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
427 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
428 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
429 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
430 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
431 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
432 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
433 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
434 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
435 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
436 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
437 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
438 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
439 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
440 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
441 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
442 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
443 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
444 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
445 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
446 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
447 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
448 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
449 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
450 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
451 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
452 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
453 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
454 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
455 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
456 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
457 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
458 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
459 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
460 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
461 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
462 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
463 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
464 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
465 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
466 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
467 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
468 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
469 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
470 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
471 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
472 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
473 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
474 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
475 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
476 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
477 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
478 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
479 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
480 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
481 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
482 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
483 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
484 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
485 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
486 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
487 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
488 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
489 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
490 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
491 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
492 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
493 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
494 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
495 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
496 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
497 { 0xFFFFFFFF }
498};
499
500static const struct si_cac_config_reg cac_override_pitcairn[] =
501{
502 { 0xFFFFFFFF }
503};
504
505static const struct si_powertune_data powertune_data_pitcairn =
506{
507 ((1 << 16) | 27027),
508 5,
509 0,
510 6,
511 100,
512 {
513 51600000UL,
514 1800000UL,
515 7194395UL,
516 309631529UL,
517 -1270850L,
518 4513710L,
519 100
520 },
521 117830498UL,
522 12,
523 {
524 0,
525 0,
526 0,
527 0,
528 0,
529 0,
530 0,
531 0
532 },
533 true
534};
535
536static const struct si_dte_data dte_data_pitcairn =
537{
538 { 0, 0, 0, 0, 0 },
539 { 0, 0, 0, 0, 0 },
540 0,
541 0,
542 0,
543 0,
544 0,
545 0,
546 0,
547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
550 0,
551 false
552};
553
554static const struct si_dte_data dte_data_curacao_xt =
555{
556 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
557 { 0x0, 0x0, 0x0, 0x0, 0x0 },
558 5,
559 45000,
560 100,
561 0xA,
562 1,
563 0,
564 0x10,
565 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
566 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
567 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
568 90,
569 true
570};
571
572static const struct si_dte_data dte_data_curacao_pro =
573{
574 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
575 { 0x0, 0x0, 0x0, 0x0, 0x0 },
576 5,
577 45000,
578 100,
579 0xA,
580 1,
581 0,
582 0x10,
583 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
584 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
585 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
586 90,
587 true
588};
589
590static const struct si_dte_data dte_data_neptune_xt =
591{
592 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
593 { 0x0, 0x0, 0x0, 0x0, 0x0 },
594 5,
595 45000,
596 100,
597 0xA,
598 1,
599 0,
600 0x10,
601 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
602 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
603 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
604 90,
605 true
606};
607
608static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
609{
610 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
611 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
612 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
613 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
614 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
615 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
616 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
617 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
618 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
619 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
620 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
621 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
622 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
623 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
624 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
625 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
626 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
627 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
628 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
629 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
630 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
631 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
632 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
633 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
634 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
635 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
636 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
637 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
638 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
639 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
640 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
641 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
642 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
643 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
644 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
645 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
646 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
647 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
648 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
649 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
650 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
651 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
652 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
653 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
654 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
655 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
656 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
657 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
658 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
659 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
660 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
661 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
662 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
663 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
664 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
665 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
666 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
667 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
668 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
669 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
670 { 0xFFFFFFFF }
671};
672
673static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
674{
675 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
676 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
677 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
678 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
679 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
680 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
681 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
682 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
683 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
684 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
685 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
686 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
687 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
688 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
689 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
690 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
691 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
692 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
693 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
694 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
695 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
696 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
697 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
698 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
699 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
700 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
701 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
702 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
703 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
704 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
705 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
706 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
707 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
708 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
709 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
710 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
711 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
712 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
713 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
714 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
715 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
716 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
717 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
718 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
719 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
720 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
721 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
722 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
723 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
724 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
725 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
726 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
727 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
728 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
729 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
730 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
731 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
732 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
733 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
734 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
735 { 0xFFFFFFFF }
736};
737
738static const struct si_cac_config_reg cac_weights_heathrow[] =
739{
740 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
741 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
742 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
743 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
744 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
745 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
746 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
747 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
748 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
749 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
750 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
751 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
752 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
753 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
754 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
755 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
756 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
757 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
758 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
759 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
760 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
761 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
762 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
763 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
764 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
765 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
766 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
767 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
768 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
769 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
770 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
771 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
772 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
773 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
774 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
775 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
776 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
777 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
778 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
779 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
780 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
781 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
782 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
783 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
784 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
785 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
786 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
787 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
788 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
789 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
790 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
791 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
792 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
793 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
794 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
795 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
796 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
797 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
798 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
799 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
800 { 0xFFFFFFFF }
801};
802
803static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
804{
805 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
806 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
807 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
808 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
809 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
810 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
811 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
812 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
813 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
814 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
815 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
816 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
817 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
818 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
819 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
820 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
821 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
822 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
823 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
824 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
825 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
826 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
827 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
828 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
829 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
830 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
831 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
832 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
833 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
834 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
835 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
836 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
837 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
838 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
839 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
840 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
841 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
842 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
843 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
844 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
845 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
846 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
847 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
848 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
849 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
850 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
851 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
852 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
853 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
854 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
855 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
856 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
857 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
858 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
859 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
860 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
861 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
862 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
863 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
864 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
865 { 0xFFFFFFFF }
866};
867
868static const struct si_cac_config_reg cac_weights_cape_verde[] =
869{
870 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
871 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
872 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
873 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
874 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
875 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
876 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
877 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
878 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
879 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
880 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
881 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
882 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
883 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
884 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
885 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
886 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
887 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
888 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
889 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
890 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
891 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
892 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
893 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
894 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
895 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
896 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
897 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
898 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
899 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
900 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
901 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
902 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
903 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
904 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
905 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
906 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
907 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
908 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
909 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
910 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
911 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
912 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
913 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
914 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
915 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
916 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
917 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
918 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
919 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
920 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
921 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
922 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
923 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
924 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
925 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
926 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
927 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
928 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
929 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
930 { 0xFFFFFFFF }
931};
932
933static const struct si_cac_config_reg lcac_cape_verde[] =
934{
935 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
936 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
937 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
938 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
939 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
940 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
941 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
942 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
943 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
944 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
945 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
946 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
947 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
948 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
949 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
950 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
951 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
952 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
953 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
954 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
955 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
956 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
957 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
958 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
959 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
960 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
961 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
962 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
963 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
964 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
965 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
966 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
967 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
968 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
969 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
970 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
971 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
972 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
973 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
974 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
975 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
976 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
977 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
978 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
979 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
980 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
981 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
982 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
983 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
984 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
985 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
986 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
987 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
988 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
989 { 0xFFFFFFFF }
990};
991
992static const struct si_cac_config_reg cac_override_cape_verde[] =
993{
994 { 0xFFFFFFFF }
995};
996
997static const struct si_powertune_data powertune_data_cape_verde =
998{
999 ((1 << 16) | 0x6993),
1000 5,
1001 0,
1002 7,
1003 105,
1004 {
1005 0UL,
1006 0UL,
1007 7194395UL,
1008 309631529UL,
1009 -1270850L,
1010 4513710L,
1011 100
1012 },
1013 117830498UL,
1014 12,
1015 {
1016 0,
1017 0,
1018 0,
1019 0,
1020 0,
1021 0,
1022 0,
1023 0
1024 },
1025 true
1026};
1027
1028static const struct si_dte_data dte_data_cape_verde =
1029{
1030 { 0, 0, 0, 0, 0 },
1031 { 0, 0, 0, 0, 0 },
1032 0,
1033 0,
1034 0,
1035 0,
1036 0,
1037 0,
1038 0,
1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1042 0,
1043 false
1044};
1045
1046static const struct si_dte_data dte_data_venus_xtx =
1047{
1048 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1049 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1050 5,
1051 55000,
1052 0x69,
1053 0xA,
1054 1,
1055 0,
1056 0x3,
1057 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1060 90,
1061 true
1062};
1063
1064static const struct si_dte_data dte_data_venus_xt =
1065{
1066 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1067 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1068 5,
1069 55000,
1070 0x69,
1071 0xA,
1072 1,
1073 0,
1074 0x3,
1075 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1078 90,
1079 true
1080};
1081
1082static const struct si_dte_data dte_data_venus_pro =
1083{
1084 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1085 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1086 5,
1087 55000,
1088 0x69,
1089 0xA,
1090 1,
1091 0,
1092 0x3,
1093 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1096 90,
1097 true
1098};
1099
1100struct si_cac_config_reg cac_weights_oland[] =
1101{
1102 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1103 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1104 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1105 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1106 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1107 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1108 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1109 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1110 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1111 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1112 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1113 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1114 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1115 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1116 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1117 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1118 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1119 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1120 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1121 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1122 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1123 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1124 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1125 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1126 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1127 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1128 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1129 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1130 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1131 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1132 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1133 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1134 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1135 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1136 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1137 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1138 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1139 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1140 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1141 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1142 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1143 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1145 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1146 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1147 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1148 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1149 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1150 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1151 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1152 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1153 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1154 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1155 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1156 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1157 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1158 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1159 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1160 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1161 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1162 { 0xFFFFFFFF }
1163};
1164
1165static const struct si_cac_config_reg cac_weights_mars_pro[] =
1166{
1167 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1168 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1169 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1170 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1171 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1172 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1173 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1174 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1175 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1176 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1177 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1178 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1179 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1180 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1181 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1182 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1183 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1184 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1185 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1186 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1187 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1188 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1189 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1190 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1191 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1192 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1193 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1194 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1195 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1196 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1197 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1198 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1199 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1200 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1201 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1202 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1203 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1204 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1205 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1206 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1207 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1208 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1210 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1211 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1212 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1213 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1214 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1215 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1216 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1217 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1218 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1219 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1220 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1222 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1223 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1224 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1225 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1226 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1227 { 0xFFFFFFFF }
1228};
1229
1230static const struct si_cac_config_reg cac_weights_mars_xt[] =
1231{
1232 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1233 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1234 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1235 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1236 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1238 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1239 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1240 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1241 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1242 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1243 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1244 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1245 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1246 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1247 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1248 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1249 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1250 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1251 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1252 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1253 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1254 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1255 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1256 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1257 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1258 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1259 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1260 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1261 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1262 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1263 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1264 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1265 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1266 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1267 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1268 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1269 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1270 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1271 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1272 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1273 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1275 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1276 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1277 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1278 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1279 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1280 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1281 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1282 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1283 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1284 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1285 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1286 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1287 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1288 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1289 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1290 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1291 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1292 { 0xFFFFFFFF }
1293};
1294
1295static const struct si_cac_config_reg cac_weights_oland_pro[] =
1296{
1297 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1298 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1299 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1300 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1301 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1303 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1304 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1305 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1306 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1307 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1308 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1309 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1310 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1311 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1312 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1313 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1314 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1315 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1316 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1317 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1318 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1319 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1320 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1321 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1322 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1323 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1324 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1325 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1326 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1327 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1328 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1329 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1330 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1331 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1332 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1333 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1334 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1335 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1336 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1337 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1338 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1340 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1341 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1342 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1343 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1344 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1345 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1346 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1347 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1348 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1349 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1350 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1351 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1352 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1353 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1354 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1355 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1356 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1357 { 0xFFFFFFFF }
1358};
1359
1360static const struct si_cac_config_reg cac_weights_oland_xt[] =
1361{
1362 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1363 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1364 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1365 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1366 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1368 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1369 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1370 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1371 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1372 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1373 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1374 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1375 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1376 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1377 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1378 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1379 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1380 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1381 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1382 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1383 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1384 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1385 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1386 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1387 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1388 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1389 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1390 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1391 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1392 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1393 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1394 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1395 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1396 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1397 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1398 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1399 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1400 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1401 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1402 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1403 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1405 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1406 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1407 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1408 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1409 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1410 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1411 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1412 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1413 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1414 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1415 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1416 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1417 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1418 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1419 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1420 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1421 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1422 { 0xFFFFFFFF }
1423};
1424
1425static const struct si_cac_config_reg lcac_oland[] =
1426{
1427 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1428 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1429 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1430 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1431 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1432 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1434 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1435 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1436 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1437 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1438 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1439 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1440 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1441 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1442 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1443 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1444 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1445 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1446 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1447 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1448 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1449 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1450 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1451 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1452 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1453 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1454 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1455 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1456 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1457 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1458 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1459 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1460 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1461 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1462 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1463 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1464 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1465 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1466 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1468 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1469 { 0xFFFFFFFF }
1470};
1471
1472static const struct si_cac_config_reg lcac_mars_pro[] =
1473{
1474 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1475 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1476 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1477 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1478 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1479 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1480 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1481 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1483 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1484 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1485 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1486 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1487 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1488 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1489 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1490 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1491 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1492 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1493 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1494 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1495 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1496 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1497 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1499 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1500 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1501 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1502 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1503 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1504 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1505 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1506 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1507 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1508 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1509 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1510 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1511 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1513 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1515 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1516 { 0xFFFFFFFF }
1517};
1518
1519static const struct si_cac_config_reg cac_override_oland[] =
1520{
1521 { 0xFFFFFFFF }
1522};
1523
1524static const struct si_powertune_data powertune_data_oland =
1525{
1526 ((1 << 16) | 0x6993),
1527 5,
1528 0,
1529 7,
1530 105,
1531 {
1532 0UL,
1533 0UL,
1534 7194395UL,
1535 309631529UL,
1536 -1270850L,
1537 4513710L,
1538 100
1539 },
1540 117830498UL,
1541 12,
1542 {
1543 0,
1544 0,
1545 0,
1546 0,
1547 0,
1548 0,
1549 0,
1550 0
1551 },
1552 true
1553};
1554
1555static const struct si_powertune_data powertune_data_mars_pro =
1556{
1557 ((1 << 16) | 0x6993),
1558 5,
1559 0,
1560 7,
1561 105,
1562 {
1563 0UL,
1564 0UL,
1565 7194395UL,
1566 309631529UL,
1567 -1270850L,
1568 4513710L,
1569 100
1570 },
1571 117830498UL,
1572 12,
1573 {
1574 0,
1575 0,
1576 0,
1577 0,
1578 0,
1579 0,
1580 0,
1581 0
1582 },
1583 true
1584};
1585
1586static const struct si_dte_data dte_data_oland =
1587{
1588 { 0, 0, 0, 0, 0 },
1589 { 0, 0, 0, 0, 0 },
1590 0,
1591 0,
1592 0,
1593 0,
1594 0,
1595 0,
1596 0,
1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1600 0,
1601 false
1602};
1603
1604static const struct si_dte_data dte_data_mars_pro =
1605{
1606 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1607 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1608 5,
1609 55000,
1610 105,
1611 0xA,
1612 1,
1613 0,
1614 0x10,
1615 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1616 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1617 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1618 90,
1619 true
1620};
1621
1622static const struct si_dte_data dte_data_sun_xt =
1623{
1624 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1625 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1626 5,
1627 55000,
1628 105,
1629 0xA,
1630 1,
1631 0,
1632 0x10,
1633 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1634 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1635 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1636 90,
1637 true
1638};
1639
1640
1641static const struct si_cac_config_reg cac_weights_hainan[] =
1642{
1643 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1644 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1645 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1646 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1647 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1648 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1649 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1650 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1651 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1652 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1653 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1654 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1655 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1656 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1657 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1658 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1659 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1660 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1661 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1662 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1663 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1664 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1665 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1666 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1667 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1668 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1669 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1670 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1671 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1672 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1673 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1674 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1675 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1677 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1678 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1679 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1680 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1681 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1682 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1683 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1684 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1685 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1686 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1687 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1688 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1689 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1690 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1691 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1692 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1693 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1694 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1695 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1696 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1697 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1698 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1699 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1700 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1701 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1702 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1703 { 0xFFFFFFFF }
1704};
1705
1706static const struct si_powertune_data powertune_data_hainan =
1707{
1708 ((1 << 16) | 0x6993),
1709 5,
1710 0,
1711 9,
1712 105,
1713 {
1714 0UL,
1715 0UL,
1716 7194395UL,
1717 309631529UL,
1718 -1270850L,
1719 4513710L,
1720 100
1721 },
1722 117830498UL,
1723 12,
1724 {
1725 0,
1726 0,
1727 0,
1728 0,
1729 0,
1730 0,
1731 0,
1732 0
1733 },
1734 true
1735};
1736
1737struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1738struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1739struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1740struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1741
1742static int si_populate_voltage_value(struct radeon_device *rdev,
1743 const struct atom_voltage_table *table,
1744 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1745static int si_get_std_voltage_value(struct radeon_device *rdev,
1746 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1747 u16 *std_voltage);
1748static int si_write_smc_soft_register(struct radeon_device *rdev,
1749 u16 reg_offset, u32 value);
1750static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1751 struct rv7xx_pl *pl,
1752 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1753static int si_calculate_sclk_params(struct radeon_device *rdev,
1754 u32 engine_clock,
1755 SISLANDS_SMC_SCLK_VALUE *sclk);
1756
1757static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1758{
1759 struct si_power_info *pi = rdev->pm.dpm.priv;
1760
1761 return pi;
1762}
1763
1764static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1765 u16 v, s32 t, u32 ileakage, u32 *leakage)
1766{
1767 s64 kt, kv, leakage_w, i_leakage, vddc;
1768 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1769
1770 i_leakage = drm_int2fixp(ileakage / 100);
1771 vddc = div64_s64(drm_int2fixp(v), 1000);
1772 temperature = div64_s64(drm_int2fixp(t), 1000);
1773
1774 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1775 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1776 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1777 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1778 t_ref = drm_int2fixp(coeff->t_ref);
1779
1780 kt = drm_fixp_div(drm_fixp_exp(drm_fixp_mul(drm_fixp_mul(t_slope, vddc) + t_intercept, temperature)),
1781 drm_fixp_exp(drm_fixp_mul(drm_fixp_mul(t_slope, vddc) + t_intercept, t_ref)));
1782 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1783
1784 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1785
1786 *leakage = drm_fixp2int(leakage_w * 1000);
1787}
1788
1789static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1790 const struct ni_leakage_coeffients *coeff,
1791 u16 v,
1792 s32 t,
1793 u32 i_leakage,
1794 u32 *leakage)
1795{
1796 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1797}
1798
1799static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1800 const u32 fixed_kt, u16 v,
1801 u32 ileakage, u32 *leakage)
1802{
1803 s64 kt, kv, leakage_w, i_leakage, vddc;
1804
1805 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1806 vddc = div64_s64(drm_int2fixp(v), 1000);
1807
1808 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1809 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1810 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1811
1812 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1813
1814 *leakage = drm_fixp2int(leakage_w * 1000);
1815}
1816
1817static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1818 const struct ni_leakage_coeffients *coeff,
1819 const u32 fixed_kt,
1820 u16 v,
1821 u32 i_leakage,
1822 u32 *leakage)
1823{
1824 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1825}
1826
1827
1828static void si_update_dte_from_pl2(struct radeon_device *rdev,
1829 struct si_dte_data *dte_data)
1830{
1831 u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1832 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1833 u32 k = dte_data->k;
1834 u32 t_max = dte_data->max_t;
1835 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1836 u32 t_0 = dte_data->t0;
1837 u32 i;
1838
1839 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1840 dte_data->tdep_count = 3;
1841
1842 for (i = 0; i < k; i++) {
1843 dte_data->r[i] =
1844 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1845 (p_limit2 * (u32)100);
1846 }
1847
1848 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1849
1850 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1851 dte_data->tdep_r[i] = dte_data->r[4];
1852 }
1853 } else {
1854 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1855 }
1856}
1857
1858static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1859{
1860 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1861 struct si_power_info *si_pi = si_get_pi(rdev);
1862 bool update_dte_from_pl2 = false;
1863
1864 if (rdev->family == CHIP_TAHITI) {
1865 si_pi->cac_weights = cac_weights_tahiti;
1866 si_pi->lcac_config = lcac_tahiti;
1867 si_pi->cac_override = cac_override_tahiti;
1868 si_pi->powertune_data = &powertune_data_tahiti;
1869 si_pi->dte_data = dte_data_tahiti;
1870
1871 switch (rdev->pdev->device) {
1872 case 0x6798:
1873 si_pi->dte_data.enable_dte_by_default = true;
1874 break;
1875 case 0x6799:
1876 si_pi->dte_data = dte_data_new_zealand;
1877 break;
1878 case 0x6790:
1879 case 0x6791:
1880 case 0x6792:
1881 case 0x679E:
1882 si_pi->dte_data = dte_data_aruba_pro;
1883 update_dte_from_pl2 = true;
1884 break;
1885 case 0x679B:
1886 si_pi->dte_data = dte_data_malta;
1887 update_dte_from_pl2 = true;
1888 break;
1889 case 0x679A:
1890 si_pi->dte_data = dte_data_tahiti_pro;
1891 update_dte_from_pl2 = true;
1892 break;
1893 default:
1894 if (si_pi->dte_data.enable_dte_by_default == true)
1895 DRM_ERROR("DTE is not enabled!\n");
1896 break;
1897 }
1898 } else if (rdev->family == CHIP_PITCAIRN) {
1899 switch (rdev->pdev->device) {
1900 case 0x6810:
1901 case 0x6818:
1902 si_pi->cac_weights = cac_weights_pitcairn;
1903 si_pi->lcac_config = lcac_pitcairn;
1904 si_pi->cac_override = cac_override_pitcairn;
1905 si_pi->powertune_data = &powertune_data_pitcairn;
1906 si_pi->dte_data = dte_data_curacao_xt;
1907 update_dte_from_pl2 = true;
1908 break;
1909 case 0x6819:
1910 case 0x6811:
1911 si_pi->cac_weights = cac_weights_pitcairn;
1912 si_pi->lcac_config = lcac_pitcairn;
1913 si_pi->cac_override = cac_override_pitcairn;
1914 si_pi->powertune_data = &powertune_data_pitcairn;
1915 si_pi->dte_data = dte_data_curacao_pro;
1916 update_dte_from_pl2 = true;
1917 break;
1918 case 0x6800:
1919 case 0x6806:
1920 si_pi->cac_weights = cac_weights_pitcairn;
1921 si_pi->lcac_config = lcac_pitcairn;
1922 si_pi->cac_override = cac_override_pitcairn;
1923 si_pi->powertune_data = &powertune_data_pitcairn;
1924 si_pi->dte_data = dte_data_neptune_xt;
1925 update_dte_from_pl2 = true;
1926 break;
1927 default:
1928 si_pi->cac_weights = cac_weights_pitcairn;
1929 si_pi->lcac_config = lcac_pitcairn;
1930 si_pi->cac_override = cac_override_pitcairn;
1931 si_pi->powertune_data = &powertune_data_pitcairn;
1932 si_pi->dte_data = dte_data_pitcairn;
1933 }
1934 } else if (rdev->family == CHIP_VERDE) {
1935 si_pi->lcac_config = lcac_cape_verde;
1936 si_pi->cac_override = cac_override_cape_verde;
1937 si_pi->powertune_data = &powertune_data_cape_verde;
1938
1939 switch (rdev->pdev->device) {
1940 case 0x683B:
1941 case 0x683F:
1942 case 0x6829:
1943 si_pi->cac_weights = cac_weights_cape_verde_pro;
1944 si_pi->dte_data = dte_data_cape_verde;
1945 break;
1946 case 0x6825:
1947 case 0x6827:
1948 si_pi->cac_weights = cac_weights_heathrow;
1949 si_pi->dte_data = dte_data_cape_verde;
1950 break;
1951 case 0x6824:
1952 case 0x682D:
1953 si_pi->cac_weights = cac_weights_chelsea_xt;
1954 si_pi->dte_data = dte_data_cape_verde;
1955 break;
1956 case 0x682F:
1957 si_pi->cac_weights = cac_weights_chelsea_pro;
1958 si_pi->dte_data = dte_data_cape_verde;
1959 break;
1960 case 0x6820:
1961 si_pi->cac_weights = cac_weights_heathrow;
1962 si_pi->dte_data = dte_data_venus_xtx;
1963 break;
1964 case 0x6821:
1965 si_pi->cac_weights = cac_weights_heathrow;
1966 si_pi->dte_data = dte_data_venus_xt;
1967 break;
1968 case 0x6823:
1969 si_pi->cac_weights = cac_weights_chelsea_pro;
1970 si_pi->dte_data = dte_data_venus_pro;
1971 break;
1972 case 0x682B:
1973 si_pi->cac_weights = cac_weights_chelsea_pro;
1974 si_pi->dte_data = dte_data_venus_pro;
1975 break;
1976 default:
1977 si_pi->cac_weights = cac_weights_cape_verde;
1978 si_pi->dte_data = dte_data_cape_verde;
1979 break;
1980 }
1981 } else if (rdev->family == CHIP_OLAND) {
1982 switch (rdev->pdev->device) {
1983 case 0x6601:
1984 case 0x6621:
1985 case 0x6603:
1986 si_pi->cac_weights = cac_weights_mars_pro;
1987 si_pi->lcac_config = lcac_mars_pro;
1988 si_pi->cac_override = cac_override_oland;
1989 si_pi->powertune_data = &powertune_data_mars_pro;
1990 si_pi->dte_data = dte_data_mars_pro;
1991 update_dte_from_pl2 = true;
1992 break;
1993 case 0x6600:
1994 case 0x6606:
1995 case 0x6620:
1996 si_pi->cac_weights = cac_weights_mars_xt;
1997 si_pi->lcac_config = lcac_mars_pro;
1998 si_pi->cac_override = cac_override_oland;
1999 si_pi->powertune_data = &powertune_data_mars_pro;
2000 si_pi->dte_data = dte_data_mars_pro;
2001 update_dte_from_pl2 = true;
2002 break;
2003 case 0x6611:
2004 si_pi->cac_weights = cac_weights_oland_pro;
2005 si_pi->lcac_config = lcac_mars_pro;
2006 si_pi->cac_override = cac_override_oland;
2007 si_pi->powertune_data = &powertune_data_mars_pro;
2008 si_pi->dte_data = dte_data_mars_pro;
2009 update_dte_from_pl2 = true;
2010 break;
2011 case 0x6610:
2012 si_pi->cac_weights = cac_weights_oland_xt;
2013 si_pi->lcac_config = lcac_mars_pro;
2014 si_pi->cac_override = cac_override_oland;
2015 si_pi->powertune_data = &powertune_data_mars_pro;
2016 si_pi->dte_data = dte_data_mars_pro;
2017 update_dte_from_pl2 = true;
2018 break;
2019 default:
2020 si_pi->cac_weights = cac_weights_oland;
2021 si_pi->lcac_config = lcac_oland;
2022 si_pi->cac_override = cac_override_oland;
2023 si_pi->powertune_data = &powertune_data_oland;
2024 si_pi->dte_data = dte_data_oland;
2025 break;
2026 }
2027 } else if (rdev->family == CHIP_HAINAN) {
2028 si_pi->cac_weights = cac_weights_hainan;
2029 si_pi->lcac_config = lcac_oland;
2030 si_pi->cac_override = cac_override_oland;
2031 si_pi->powertune_data = &powertune_data_hainan;
2032 si_pi->dte_data = dte_data_sun_xt;
2033 update_dte_from_pl2 = true;
2034 } else {
2035 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2036 return;
2037 }
2038
2039 ni_pi->enable_power_containment = false;
2040 ni_pi->enable_cac = false;
2041 ni_pi->enable_sq_ramping = false;
2042 si_pi->enable_dte = false;
2043
2044 if (si_pi->powertune_data->enable_powertune_by_default) {
2045 ni_pi->enable_power_containment= true;
2046 ni_pi->enable_cac = true;
2047 if (si_pi->dte_data.enable_dte_by_default) {
2048 si_pi->enable_dte = true;
2049 if (update_dte_from_pl2)
2050 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2051
2052 }
2053 ni_pi->enable_sq_ramping = true;
2054 }
2055
2056 ni_pi->driver_calculate_cac_leakage = true;
2057 ni_pi->cac_configuration_required = true;
2058
2059 if (ni_pi->cac_configuration_required) {
2060 ni_pi->support_cac_long_term_average = true;
2061 si_pi->dyn_powertune_data.l2_lta_window_size =
2062 si_pi->powertune_data->l2_lta_window_size_default;
2063 si_pi->dyn_powertune_data.lts_truncate =
2064 si_pi->powertune_data->lts_truncate_default;
2065 } else {
2066 ni_pi->support_cac_long_term_average = false;
2067 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2068 si_pi->dyn_powertune_data.lts_truncate = 0;
2069 }
2070
2071 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2072}
2073
2074static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2075{
2076 return 1;
2077}
2078
2079static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2080{
2081 u32 xclk;
2082 u32 wintime;
2083 u32 cac_window;
2084 u32 cac_window_size;
2085
2086 xclk = radeon_get_xclk(rdev);
2087
2088 if (xclk == 0)
2089 return 0;
2090
2091 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2092 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2093
2094 wintime = (cac_window_size * 100) / xclk;
2095
2096 return wintime;
2097}
2098
2099static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2100{
2101 return power_in_watts;
2102}
2103
2104static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2105 bool adjust_polarity,
2106 u32 tdp_adjustment,
2107 u32 *tdp_limit,
2108 u32 *near_tdp_limit)
2109{
2110 u32 adjustment_delta, max_tdp_limit;
2111
2112 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2113 return -EINVAL;
2114
2115 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2116
2117 if (adjust_polarity) {
2118 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2119 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2120 } else {
2121 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2122 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit;
2123 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2124 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2125 else
2126 *near_tdp_limit = 0;
2127 }
2128
2129 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2130 return -EINVAL;
2131 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2132 return -EINVAL;
2133
2134 return 0;
2135}
2136
2137static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2138 struct radeon_ps *radeon_state)
2139{
2140 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2141 struct si_power_info *si_pi = si_get_pi(rdev);
2142
2143 if (ni_pi->enable_power_containment) {
2144 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2145 PP_SIslands_PAPMParameters *papm_parm;
2146 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2147 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2148 u32 tdp_limit;
2149 u32 near_tdp_limit;
2150 int ret;
2151
2152 if (scaling_factor == 0)
2153 return -EINVAL;
2154
2155 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2156
2157 ret = si_calculate_adjusted_tdp_limits(rdev,
2158 false, /* ??? */
2159 rdev->pm.dpm.tdp_adjustment,
2160 &tdp_limit,
2161 &near_tdp_limit);
2162 if (ret)
2163 return ret;
2164
2165 smc_table->dpm2Params.TDPLimit =
2166 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2167 smc_table->dpm2Params.NearTDPLimit =
2168 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2169 smc_table->dpm2Params.SafePowerLimit =
2170 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2171
2172 ret = si_copy_bytes_to_smc(rdev,
2173 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2174 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2175 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2176 sizeof(u32) * 3,
2177 si_pi->sram_end);
2178 if (ret)
2179 return ret;
2180
2181 if (si_pi->enable_ppm) {
2182 papm_parm = &si_pi->papm_parm;
2183 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2184 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2185 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2186 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2187 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2188 papm_parm->PlatformPowerLimit = 0xffffffff;
2189 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2190
2191 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2192 (u8 *)papm_parm,
2193 sizeof(PP_SIslands_PAPMParameters),
2194 si_pi->sram_end);
2195 if (ret)
2196 return ret;
2197 }
2198 }
2199 return 0;
2200}
2201
2202static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2203 struct radeon_ps *radeon_state)
2204{
2205 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2206 struct si_power_info *si_pi = si_get_pi(rdev);
2207
2208 if (ni_pi->enable_power_containment) {
2209 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2210 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2211 int ret;
2212
2213 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2214
2215 smc_table->dpm2Params.NearTDPLimit =
2216 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2217 smc_table->dpm2Params.SafePowerLimit =
2218 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2219
2220 ret = si_copy_bytes_to_smc(rdev,
2221 (si_pi->state_table_start +
2222 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2223 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2224 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2225 sizeof(u32) * 2,
2226 si_pi->sram_end);
2227 if (ret)
2228 return ret;
2229 }
2230
2231 return 0;
2232}
2233
2234static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2235 const u16 prev_std_vddc,
2236 const u16 curr_std_vddc)
2237{
2238 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2239 u64 prev_vddc = (u64)prev_std_vddc;
2240 u64 curr_vddc = (u64)curr_std_vddc;
2241 u64 pwr_efficiency_ratio, n, d;
2242
2243 if ((prev_vddc == 0) || (curr_vddc == 0))
2244 return 0;
2245
2246 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2247 d = prev_vddc * prev_vddc;
2248 pwr_efficiency_ratio = div64_u64(n, d);
2249
2250 if (pwr_efficiency_ratio > (u64)0xFFFF)
2251 return 0;
2252
2253 return (u16)pwr_efficiency_ratio;
2254}
2255
2256static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2257 struct radeon_ps *radeon_state)
2258{
2259 struct si_power_info *si_pi = si_get_pi(rdev);
2260
2261 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2262 radeon_state->vclk && radeon_state->dclk)
2263 return true;
2264
2265 return false;
2266}
2267
2268static int si_populate_power_containment_values(struct radeon_device *rdev,
2269 struct radeon_ps *radeon_state,
2270 SISLANDS_SMC_SWSTATE *smc_state)
2271{
2272 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2273 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2274 struct ni_ps *state = ni_get_ps(radeon_state);
2275 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2276 u32 prev_sclk;
2277 u32 max_sclk;
2278 u32 min_sclk;
2279 u16 prev_std_vddc;
2280 u16 curr_std_vddc;
2281 int i;
2282 u16 pwr_efficiency_ratio;
2283 u8 max_ps_percent;
2284 bool disable_uvd_power_tune;
2285 int ret;
2286
2287 if (ni_pi->enable_power_containment == false)
2288 return 0;
2289
2290 if (state->performance_level_count == 0)
2291 return -EINVAL;
2292
2293 if (smc_state->levelCount != state->performance_level_count)
2294 return -EINVAL;
2295
2296 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2297
2298 smc_state->levels[0].dpm2.MaxPS = 0;
2299 smc_state->levels[0].dpm2.NearTDPDec = 0;
2300 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2301 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2302 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2303
2304 for (i = 1; i < state->performance_level_count; i++) {
2305 prev_sclk = state->performance_levels[i-1].sclk;
2306 max_sclk = state->performance_levels[i].sclk;
2307 if (i == 1)
2308 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2309 else
2310 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2311
2312 if (prev_sclk > max_sclk)
2313 return -EINVAL;
2314
2315 if ((max_ps_percent == 0) ||
2316 (prev_sclk == max_sclk) ||
2317 disable_uvd_power_tune) {
2318 min_sclk = max_sclk;
2319 } else if (i == 1) {
2320 min_sclk = prev_sclk;
2321 } else {
2322 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2323 }
2324
2325 if (min_sclk < state->performance_levels[0].sclk)
2326 min_sclk = state->performance_levels[0].sclk;
2327
2328 if (min_sclk == 0)
2329 return -EINVAL;
2330
2331 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2332 state->performance_levels[i-1].vddc, &vddc);
2333 if (ret)
2334 return ret;
2335
2336 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2337 if (ret)
2338 return ret;
2339
2340 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2341 state->performance_levels[i].vddc, &vddc);
2342 if (ret)
2343 return ret;
2344
2345 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2346 if (ret)
2347 return ret;
2348
2349 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2350 prev_std_vddc, curr_std_vddc);
2351
2352 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2353 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2354 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2355 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2356 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2357 }
2358
2359 return 0;
2360}
2361
2362static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2363 struct radeon_ps *radeon_state,
2364 SISLANDS_SMC_SWSTATE *smc_state)
2365{
2366 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2367 struct ni_ps *state = ni_get_ps(radeon_state);
2368 u32 sq_power_throttle, sq_power_throttle2;
2369 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2370 int i;
2371
2372 if (state->performance_level_count == 0)
2373 return -EINVAL;
2374
2375 if (smc_state->levelCount != state->performance_level_count)
2376 return -EINVAL;
2377
2378 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2379 return -EINVAL;
2380
2381 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2382 enable_sq_ramping = false;
2383
2384 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2385 enable_sq_ramping = false;
2386
2387 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2388 enable_sq_ramping = false;
2389
2390 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2391 enable_sq_ramping = false;
2392
2393 if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2394 enable_sq_ramping = false;
2395
2396 for (i = 0; i < state->performance_level_count; i++) {
2397 sq_power_throttle = 0;
2398 sq_power_throttle2 = 0;
2399
2400 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2401 enable_sq_ramping) {
2402 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2403 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2404 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2405 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2406 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2407 } else {
2408 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2409 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2410 }
2411
2412 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2413 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2414 }
2415
2416 return 0;
2417}
2418
2419static int si_enable_power_containment(struct radeon_device *rdev,
2420 struct radeon_ps *radeon_new_state,
2421 bool enable)
2422{
2423 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2424 PPSMC_Result smc_result;
2425 int ret = 0;
2426
2427 if (ni_pi->enable_power_containment) {
2428 if (enable) {
2429 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2430 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2431 if (smc_result != PPSMC_Result_OK) {
2432 ret = -EINVAL;
2433 ni_pi->pc_enabled = false;
2434 } else {
2435 ni_pi->pc_enabled = true;
2436 }
2437 }
2438 } else {
2439 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2440 if (smc_result != PPSMC_Result_OK)
2441 ret = -EINVAL;
2442 ni_pi->pc_enabled = false;
2443 }
2444 }
2445
2446 return ret;
2447}
2448
2449static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2450{
2451 struct si_power_info *si_pi = si_get_pi(rdev);
2452 int ret = 0;
2453 struct si_dte_data *dte_data = &si_pi->dte_data;
2454 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2455 u32 table_size;
2456 u8 tdep_count;
2457 u32 i;
2458
2459 if (dte_data == NULL)
2460 si_pi->enable_dte = false;
2461
2462 if (si_pi->enable_dte == false)
2463 return 0;
2464
2465 if (dte_data->k <= 0)
2466 return -EINVAL;
2467
2468 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2469 if (dte_tables == NULL) {
2470 si_pi->enable_dte = false;
2471 return -ENOMEM;
2472 }
2473
2474 table_size = dte_data->k;
2475
2476 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2477 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2478
2479 tdep_count = dte_data->tdep_count;
2480 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2481 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2482
2483 dte_tables->K = cpu_to_be32(table_size);
2484 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2485 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2486 dte_tables->WindowSize = dte_data->window_size;
2487 dte_tables->temp_select = dte_data->temp_select;
2488 dte_tables->DTE_mode = dte_data->dte_mode;
2489 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2490
2491 if (tdep_count > 0)
2492 table_size--;
2493
2494 for (i = 0; i < table_size; i++) {
2495 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2496 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2497 }
2498
2499 dte_tables->Tdep_count = tdep_count;
2500
2501 for (i = 0; i < (u32)tdep_count; i++) {
2502 dte_tables->T_limits[i] = dte_data->t_limits[i];
2503 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2504 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2505 }
2506
2507 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2508 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2509 kfree(dte_tables);
2510
2511 return ret;
2512}
2513
2514static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2515 u16 *max, u16 *min)
2516{
2517 struct si_power_info *si_pi = si_get_pi(rdev);
2518 struct radeon_cac_leakage_table *table =
2519 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2520 u32 i;
2521 u32 v0_loadline;
2522
2523
2524 if (table == NULL)
2525 return -EINVAL;
2526
2527 *max = 0;
2528 *min = 0xFFFF;
2529
2530 for (i = 0; i < table->count; i++) {
2531 if (table->entries[i].vddc > *max)
2532 *max = table->entries[i].vddc;
2533 if (table->entries[i].vddc < *min)
2534 *min = table->entries[i].vddc;
2535 }
2536
2537 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2538 return -EINVAL;
2539
2540 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2541
2542 if (v0_loadline > 0xFFFFUL)
2543 return -EINVAL;
2544
2545 *min = (u16)v0_loadline;
2546
2547 if ((*min > *max) || (*max == 0) || (*min == 0))
2548 return -EINVAL;
2549
2550 return 0;
2551}
2552
2553static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2554{
2555 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2556 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2557}
2558
2559static int si_init_dte_leakage_table(struct radeon_device *rdev,
2560 PP_SIslands_CacConfig *cac_tables,
2561 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2562 u16 t0, u16 t_step)
2563{
2564 struct si_power_info *si_pi = si_get_pi(rdev);
2565 u32 leakage;
2566 unsigned int i, j;
2567 s32 t;
2568 u32 smc_leakage;
2569 u32 scaling_factor;
2570 u16 voltage;
2571
2572 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2573
2574 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2575 t = (1000 * (i * t_step + t0));
2576
2577 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2578 voltage = vddc_max - (vddc_step * j);
2579
2580 si_calculate_leakage_for_v_and_t(rdev,
2581 &si_pi->powertune_data->leakage_coefficients,
2582 voltage,
2583 t,
2584 si_pi->dyn_powertune_data.cac_leakage,
2585 &leakage);
2586
2587 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2588
2589 if (smc_leakage > 0xFFFF)
2590 smc_leakage = 0xFFFF;
2591
2592 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2593 cpu_to_be16((u16)smc_leakage);
2594 }
2595 }
2596 return 0;
2597}
2598
2599static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2600 PP_SIslands_CacConfig *cac_tables,
2601 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2602{
2603 struct si_power_info *si_pi = si_get_pi(rdev);
2604 u32 leakage;
2605 unsigned int i, j;
2606 u32 smc_leakage;
2607 u32 scaling_factor;
2608 u16 voltage;
2609
2610 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2611
2612 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2613 voltage = vddc_max - (vddc_step * j);
2614
2615 si_calculate_leakage_for_v(rdev,
2616 &si_pi->powertune_data->leakage_coefficients,
2617 si_pi->powertune_data->fixed_kt,
2618 voltage,
2619 si_pi->dyn_powertune_data.cac_leakage,
2620 &leakage);
2621
2622 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2623
2624 if (smc_leakage > 0xFFFF)
2625 smc_leakage = 0xFFFF;
2626
2627 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2628 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2629 cpu_to_be16((u16)smc_leakage);
2630 }
2631 return 0;
2632}
2633
2634static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2635{
2636 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2637 struct si_power_info *si_pi = si_get_pi(rdev);
2638 PP_SIslands_CacConfig *cac_tables = NULL;
2639 u16 vddc_max, vddc_min, vddc_step;
2640 u16 t0, t_step;
2641 u32 load_line_slope, reg;
2642 int ret = 0;
2643 u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2644
2645 if (ni_pi->enable_cac == false)
2646 return 0;
2647
2648 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2649 if (!cac_tables)
2650 return -ENOMEM;
2651
2652 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2653 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2654 WREG32(CG_CAC_CTRL, reg);
2655
2656 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2657 si_pi->dyn_powertune_data.dc_pwr_value =
2658 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2659 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2660 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2661
2662 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2663
2664 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2665 if (ret)
2666 goto done_free;
2667
2668 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2669 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2670 t_step = 4;
2671 t0 = 60;
2672
2673 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2674 ret = si_init_dte_leakage_table(rdev, cac_tables,
2675 vddc_max, vddc_min, vddc_step,
2676 t0, t_step);
2677 else
2678 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2679 vddc_max, vddc_min, vddc_step);
2680 if (ret)
2681 goto done_free;
2682
2683 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2684
2685 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2686 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2687 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2688 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2689 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2690 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2691 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2692 cac_tables->calculation_repeats = cpu_to_be32(2);
2693 cac_tables->dc_cac = cpu_to_be32(0);
2694 cac_tables->log2_PG_LKG_SCALE = 12;
2695 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2696 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2697 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2698
2699 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2700 sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2701
2702 if (ret)
2703 goto done_free;
2704
2705 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2706
2707done_free:
2708 if (ret) {
2709 ni_pi->enable_cac = false;
2710 ni_pi->enable_power_containment = false;
2711 }
2712
2713 kfree(cac_tables);
2714
2715 return 0;
2716}
2717
2718static int si_program_cac_config_registers(struct radeon_device *rdev,
2719 const struct si_cac_config_reg *cac_config_regs)
2720{
2721 const struct si_cac_config_reg *config_regs = cac_config_regs;
2722 u32 data = 0, offset;
2723
2724 if (!config_regs)
2725 return -EINVAL;
2726
2727 while (config_regs->offset != 0xFFFFFFFF) {
2728 switch (config_regs->type) {
2729 case SISLANDS_CACCONFIG_CGIND:
2730 offset = SMC_CG_IND_START + config_regs->offset;
2731 if (offset < SMC_CG_IND_END)
2732 data = RREG32_SMC(offset);
2733 break;
2734 default:
2735 data = RREG32(config_regs->offset << 2);
2736 break;
2737 }
2738
2739 data &= ~config_regs->mask;
2740 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2741
2742 switch (config_regs->type) {
2743 case SISLANDS_CACCONFIG_CGIND:
2744 offset = SMC_CG_IND_START + config_regs->offset;
2745 if (offset < SMC_CG_IND_END)
2746 WREG32_SMC(offset, data);
2747 break;
2748 default:
2749 WREG32(config_regs->offset << 2, data);
2750 break;
2751 }
2752 config_regs++;
2753 }
2754 return 0;
2755}
2756
2757static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2758{
2759 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2760 struct si_power_info *si_pi = si_get_pi(rdev);
2761 int ret;
2762
2763 if ((ni_pi->enable_cac == false) ||
2764 (ni_pi->cac_configuration_required == false))
2765 return 0;
2766
2767 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2768 if (ret)
2769 return ret;
2770 ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2771 if (ret)
2772 return ret;
2773 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2774 if (ret)
2775 return ret;
2776
2777 return 0;
2778}
2779
2780static int si_enable_smc_cac(struct radeon_device *rdev,
2781 struct radeon_ps *radeon_new_state,
2782 bool enable)
2783{
2784 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2785 struct si_power_info *si_pi = si_get_pi(rdev);
2786 PPSMC_Result smc_result;
2787 int ret = 0;
2788
2789 if (ni_pi->enable_cac) {
2790 if (enable) {
2791 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2792 if (ni_pi->support_cac_long_term_average) {
2793 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2794 if (smc_result != PPSMC_Result_OK)
2795 ni_pi->support_cac_long_term_average = false;
2796 }
2797
2798 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2799 if (smc_result != PPSMC_Result_OK) {
2800 ret = -EINVAL;
2801 ni_pi->cac_enabled = false;
2802 } else {
2803 ni_pi->cac_enabled = true;
2804 }
2805
2806 if (si_pi->enable_dte) {
2807 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2808 if (smc_result != PPSMC_Result_OK)
2809 ret = -EINVAL;
2810 }
2811 }
2812 } else if (ni_pi->cac_enabled) {
2813 if (si_pi->enable_dte)
2814 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2815
2816 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2817
2818 ni_pi->cac_enabled = false;
2819
2820 if (ni_pi->support_cac_long_term_average)
2821 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2822 }
2823 }
2824 return ret;
2825}
2826
2827static int si_init_smc_spll_table(struct radeon_device *rdev)
2828{
2829 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2830 struct si_power_info *si_pi = si_get_pi(rdev);
2831 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2832 SISLANDS_SMC_SCLK_VALUE sclk_params;
2833 u32 fb_div, p_div;
2834 u32 clk_s, clk_v;
2835 u32 sclk = 0;
2836 int ret = 0;
2837 u32 tmp;
2838 int i;
2839
2840 if (si_pi->spll_table_start == 0)
2841 return -EINVAL;
2842
2843 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2844 if (spll_table == NULL)
2845 return -ENOMEM;
2846
2847 for (i = 0; i < 256; i++) {
2848 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2849 if (ret)
2850 break;
2851
2852 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2853 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2854 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2855 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2856
2857 fb_div &= ~0x00001FFF;
2858 fb_div >>= 1;
2859 clk_v >>= 6;
2860
2861 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2862 ret = -EINVAL;
2863 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2864 ret = -EINVAL;
2865 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2866 ret = -EINVAL;
2867 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2868 ret = -EINVAL;
2869
2870 if (ret)
2871 break;
2872
2873 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2874 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2875 spll_table->freq[i] = cpu_to_be32(tmp);
2876
2877 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2878 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2879 spll_table->ss[i] = cpu_to_be32(tmp);
2880
2881 sclk += 512;
2882 }
2883
2884
2885 if (!ret)
2886 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2887 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2888 si_pi->sram_end);
2889
2890 if (ret)
2891 ni_pi->enable_power_containment = false;
2892
2893 kfree(spll_table);
2894
2895 return ret;
2896}
2897
2898static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2899 struct radeon_ps *rps)
2900{
2901 struct ni_ps *ps = ni_get_ps(rps);
2902 struct radeon_clock_and_voltage_limits *max_limits;
2903 bool disable_mclk_switching;
2904 u32 mclk, sclk;
2905 u16 vddc, vddci;
2906 int i;
2907
2908 if (rdev->pm.dpm.new_active_crtc_count > 1)
2909 disable_mclk_switching = true;
2910 else
2911 disable_mclk_switching = false;
2912
2913 if (rdev->pm.dpm.ac_power)
2914 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2915 else
2916 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
2917
2918 for (i = ps->performance_level_count - 2; i >= 0; i--) {
2919 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
2920 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
2921 }
2922 if (rdev->pm.dpm.ac_power == false) {
2923 for (i = 0; i < ps->performance_level_count; i++) {
2924 if (ps->performance_levels[i].mclk > max_limits->mclk)
2925 ps->performance_levels[i].mclk = max_limits->mclk;
2926 if (ps->performance_levels[i].sclk > max_limits->sclk)
2927 ps->performance_levels[i].sclk = max_limits->sclk;
2928 if (ps->performance_levels[i].vddc > max_limits->vddc)
2929 ps->performance_levels[i].vddc = max_limits->vddc;
2930 if (ps->performance_levels[i].vddci > max_limits->vddci)
2931 ps->performance_levels[i].vddci = max_limits->vddci;
2932 }
2933 }
2934
2935 /* XXX validate the min clocks required for display */
2936
2937 if (disable_mclk_switching) {
2938 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
2939 sclk = ps->performance_levels[0].sclk;
2940 vddc = ps->performance_levels[0].vddc;
2941 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
2942 } else {
2943 sclk = ps->performance_levels[0].sclk;
2944 mclk = ps->performance_levels[0].mclk;
2945 vddc = ps->performance_levels[0].vddc;
2946 vddci = ps->performance_levels[0].vddci;
2947 }
2948
2949 /* adjusted low state */
2950 ps->performance_levels[0].sclk = sclk;
2951 ps->performance_levels[0].mclk = mclk;
2952 ps->performance_levels[0].vddc = vddc;
2953 ps->performance_levels[0].vddci = vddci;
2954
2955 for (i = 1; i < ps->performance_level_count; i++) {
2956 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
2957 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
2958 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
2959 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
2960 }
2961
2962 if (disable_mclk_switching) {
2963 mclk = ps->performance_levels[0].mclk;
2964 for (i = 1; i < ps->performance_level_count; i++) {
2965 if (mclk < ps->performance_levels[i].mclk)
2966 mclk = ps->performance_levels[i].mclk;
2967 }
2968 for (i = 0; i < ps->performance_level_count; i++) {
2969 ps->performance_levels[i].mclk = mclk;
2970 ps->performance_levels[i].vddci = vddci;
2971 }
2972 } else {
2973 for (i = 1; i < ps->performance_level_count; i++) {
2974 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
2975 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
2976 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
2977 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
2978 }
2979 }
2980
2981 for (i = 0; i < ps->performance_level_count; i++)
2982 btc_adjust_clock_combinations(rdev, max_limits,
2983 &ps->performance_levels[i]);
2984
2985 for (i = 0; i < ps->performance_level_count; i++) {
2986 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2987 ps->performance_levels[i].sclk,
2988 max_limits->vddc, &ps->performance_levels[i].vddc);
2989 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2990 ps->performance_levels[i].mclk,
2991 max_limits->vddci, &ps->performance_levels[i].vddci);
2992 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2993 ps->performance_levels[i].mclk,
2994 max_limits->vddc, &ps->performance_levels[i].vddc);
2995 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
2996 rdev->clock.current_dispclk,
2997 max_limits->vddc, &ps->performance_levels[i].vddc);
2998 }
2999
3000 for (i = 0; i < ps->performance_level_count; i++) {
3001 btc_apply_voltage_delta_rules(rdev,
3002 max_limits->vddc, max_limits->vddci,
3003 &ps->performance_levels[i].vddc,
3004 &ps->performance_levels[i].vddci);
3005 }
3006
3007 ps->dc_compatible = true;
3008 for (i = 0; i < ps->performance_level_count; i++) {
3009 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3010 ps->dc_compatible = false;
3011 }
3012
3013}
3014
3015#if 0
3016static int si_read_smc_soft_register(struct radeon_device *rdev,
3017 u16 reg_offset, u32 *value)
3018{
3019 struct si_power_info *si_pi = si_get_pi(rdev);
3020
3021 return si_read_smc_sram_dword(rdev,
3022 si_pi->soft_regs_start + reg_offset, value,
3023 si_pi->sram_end);
3024}
3025#endif
3026
3027static int si_write_smc_soft_register(struct radeon_device *rdev,
3028 u16 reg_offset, u32 value)
3029{
3030 struct si_power_info *si_pi = si_get_pi(rdev);
3031
3032 return si_write_smc_sram_dword(rdev,
3033 si_pi->soft_regs_start + reg_offset,
3034 value, si_pi->sram_end);
3035}
3036
3037static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3038{
3039 bool ret = false;
3040 u32 tmp, width, row, column, bank, density;
3041 bool is_memory_gddr5, is_special;
3042
3043 tmp = RREG32(MC_SEQ_MISC0);
3044 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3045 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3046 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3047
3048 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3049 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3050
3051 tmp = RREG32(MC_ARB_RAMCFG);
3052 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3053 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3054 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3055
3056 density = (1 << (row + column - 20 + bank)) * width;
3057
3058 if ((rdev->pdev->device == 0x6819) &&
3059 is_memory_gddr5 && is_special && (density == 0x400))
3060 ret = true;
3061
3062 return ret;
3063}
3064
3065static void si_get_leakage_vddc(struct radeon_device *rdev)
3066{
3067 struct si_power_info *si_pi = si_get_pi(rdev);
3068 u16 vddc, count = 0;
3069 int i, ret;
3070
3071 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3072 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3073
3074 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3075 si_pi->leakage_voltage.entries[count].voltage = vddc;
3076 si_pi->leakage_voltage.entries[count].leakage_index =
3077 SISLANDS_LEAKAGE_INDEX0 + i;
3078 count++;
3079 }
3080 }
3081 si_pi->leakage_voltage.count = count;
3082}
3083
3084static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3085 u32 index, u16 *leakage_voltage)
3086{
3087 struct si_power_info *si_pi = si_get_pi(rdev);
3088 int i;
3089
3090 if (leakage_voltage == NULL)
3091 return -EINVAL;
3092
3093 if ((index & 0xff00) != 0xff00)
3094 return -EINVAL;
3095
3096 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3097 return -EINVAL;
3098
3099 if (index < SISLANDS_LEAKAGE_INDEX0)
3100 return -EINVAL;
3101
3102 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3103 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3104 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3105 return 0;
3106 }
3107 }
3108 return -EAGAIN;
3109}
3110
3111static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3112{
3113 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3114 bool want_thermal_protection;
3115 enum radeon_dpm_event_src dpm_event_src;
3116
3117 switch (sources) {
3118 case 0:
3119 default:
3120 want_thermal_protection = false;
3121 break;
3122 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3123 want_thermal_protection = true;
3124 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3125 break;
3126 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3127 want_thermal_protection = true;
3128 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3129 break;
3130 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3131 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3132 want_thermal_protection = true;
3133 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3134 break;
3135 }
3136
3137 if (want_thermal_protection) {
3138 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3139 if (pi->thermal_protection)
3140 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3141 } else {
3142 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3143 }
3144}
3145
3146static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3147 enum radeon_dpm_auto_throttle_src source,
3148 bool enable)
3149{
3150 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3151
3152 if (enable) {
3153 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3154 pi->active_auto_throttle_sources |= 1 << source;
3155 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3156 }
3157 } else {
3158 if (pi->active_auto_throttle_sources & (1 << source)) {
3159 pi->active_auto_throttle_sources &= ~(1 << source);
3160 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3161 }
3162 }
3163}
3164
3165static void si_start_dpm(struct radeon_device *rdev)
3166{
3167 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3168}
3169
3170static void si_stop_dpm(struct radeon_device *rdev)
3171{
3172 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3173}
3174
3175static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3176{
3177 if (enable)
3178 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3179 else
3180 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3181
3182}
3183
3184#if 0
3185static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3186 u32 thermal_level)
3187{
3188 PPSMC_Result ret;
3189
3190 if (thermal_level == 0) {
3191 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3192 if (ret == PPSMC_Result_OK)
3193 return 0;
3194 else
3195 return -EINVAL;
3196 }
3197 return 0;
3198}
3199
3200static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3201{
3202 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3203}
3204#endif
3205
3206#if 0
3207static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3208{
3209 if (ac_power)
3210 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3211 0 : -EINVAL;
3212
3213 return 0;
3214}
3215#endif
3216
3217static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3218 PPSMC_Msg msg, u32 parameter)
3219{
3220 WREG32(SMC_SCRATCH0, parameter);
3221 return si_send_msg_to_smc(rdev, msg);
3222}
3223
3224static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3225{
3226 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3227 return -EINVAL;
3228
3229 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3230 0 : -EINVAL;
3231}
3232
3233#if 0
3234static int si_unrestrict_performance_levels_after_switch(struct radeon_device *rdev)
3235{
3236 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3237 return -EINVAL;
3238
3239 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) == PPSMC_Result_OK) ?
3240 0 : -EINVAL;
3241}
3242#endif
3243
3244static int si_set_boot_state(struct radeon_device *rdev)
3245{
3246 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3247 0 : -EINVAL;
3248}
3249
3250static int si_set_sw_state(struct radeon_device *rdev)
3251{
3252 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3253 0 : -EINVAL;
3254}
3255
3256static int si_halt_smc(struct radeon_device *rdev)
3257{
3258 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3259 return -EINVAL;
3260
3261 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3262 0 : -EINVAL;
3263}
3264
3265static int si_resume_smc(struct radeon_device *rdev)
3266{
3267 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3268 return -EINVAL;
3269
3270 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3271 0 : -EINVAL;
3272}
3273
3274static void si_dpm_start_smc(struct radeon_device *rdev)
3275{
3276 si_program_jump_on_start(rdev);
3277 si_start_smc(rdev);
3278 si_start_smc_clock(rdev);
3279}
3280
3281static void si_dpm_stop_smc(struct radeon_device *rdev)
3282{
3283 si_reset_smc(rdev);
3284 si_stop_smc_clock(rdev);
3285}
3286
3287static int si_process_firmware_header(struct radeon_device *rdev)
3288{
3289 struct si_power_info *si_pi = si_get_pi(rdev);
3290 u32 tmp;
3291 int ret;
3292
3293 ret = si_read_smc_sram_dword(rdev,
3294 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3295 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3296 &tmp, si_pi->sram_end);
3297 if (ret)
3298 return ret;
3299
3300 si_pi->state_table_start = tmp;
3301
3302 ret = si_read_smc_sram_dword(rdev,
3303 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3304 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3305 &tmp, si_pi->sram_end);
3306 if (ret)
3307 return ret;
3308
3309 si_pi->soft_regs_start = tmp;
3310
3311 ret = si_read_smc_sram_dword(rdev,
3312 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3313 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3314 &tmp, si_pi->sram_end);
3315 if (ret)
3316 return ret;
3317
3318 si_pi->mc_reg_table_start = tmp;
3319
3320 ret = si_read_smc_sram_dword(rdev,
3321 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3322 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3323 &tmp, si_pi->sram_end);
3324 if (ret)
3325 return ret;
3326
3327 si_pi->arb_table_start = tmp;
3328
3329 ret = si_read_smc_sram_dword(rdev,
3330 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3331 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3332 &tmp, si_pi->sram_end);
3333 if (ret)
3334 return ret;
3335
3336 si_pi->cac_table_start = tmp;
3337
3338 ret = si_read_smc_sram_dword(rdev,
3339 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3340 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3341 &tmp, si_pi->sram_end);
3342 if (ret)
3343 return ret;
3344
3345 si_pi->dte_table_start = tmp;
3346
3347 ret = si_read_smc_sram_dword(rdev,
3348 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3349 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3350 &tmp, si_pi->sram_end);
3351 if (ret)
3352 return ret;
3353
3354 si_pi->spll_table_start = tmp;
3355
3356 ret = si_read_smc_sram_dword(rdev,
3357 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3358 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3359 &tmp, si_pi->sram_end);
3360 if (ret)
3361 return ret;
3362
3363 si_pi->papm_cfg_table_start = tmp;
3364
3365 return ret;
3366}
3367
3368static void si_read_clock_registers(struct radeon_device *rdev)
3369{
3370 struct si_power_info *si_pi = si_get_pi(rdev);
3371
3372 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3373 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3374 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3375 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3376 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3377 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3378 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3379 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3380 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3381 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3382 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3383 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3384 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3385 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3386 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3387}
3388
3389static void si_enable_thermal_protection(struct radeon_device *rdev,
3390 bool enable)
3391{
3392 if (enable)
3393 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3394 else
3395 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3396}
3397
3398static void si_enable_acpi_power_management(struct radeon_device *rdev)
3399{
3400 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3401}
3402
3403#if 0
3404static int si_enter_ulp_state(struct radeon_device *rdev)
3405{
3406 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3407
3408 udelay(25000);
3409
3410 return 0;
3411}
3412
3413static int si_exit_ulp_state(struct radeon_device *rdev)
3414{
3415 int i;
3416
3417 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3418
3419 udelay(7000);
3420
3421 for (i = 0; i < rdev->usec_timeout; i++) {
3422 if (RREG32(SMC_RESP_0) == 1)
3423 break;
3424 udelay(1000);
3425 }
3426
3427 return 0;
3428}
3429#endif
3430
3431static int si_notify_smc_display_change(struct radeon_device *rdev,
3432 bool has_display)
3433{
3434 PPSMC_Msg msg = has_display ?
3435 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3436
3437 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3438 0 : -EINVAL;
3439}
3440
3441static void si_program_response_times(struct radeon_device *rdev)
3442{
3443 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3444 u32 vddc_dly, acpi_dly, vbi_dly;
3445 u32 reference_clock;
3446
3447 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3448
3449 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3450 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3451
3452 if (voltage_response_time == 0)
3453 voltage_response_time = 1000;
3454
3455 acpi_delay_time = 15000;
3456 vbi_time_out = 100000;
3457
3458 reference_clock = radeon_get_xclk(rdev);
3459
3460 vddc_dly = (voltage_response_time * reference_clock) / 100;
3461 acpi_dly = (acpi_delay_time * reference_clock) / 100;
3462 vbi_dly = (vbi_time_out * reference_clock) / 100;
3463
3464 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
3465 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
3466 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3467 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3468}
3469
3470static void si_program_ds_registers(struct radeon_device *rdev)
3471{
3472 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3473 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3474
3475 if (eg_pi->sclk_deep_sleep) {
3476 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3477 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3478 ~AUTOSCALE_ON_SS_CLEAR);
3479 }
3480}
3481
3482static void si_program_display_gap(struct radeon_device *rdev)
3483{
3484 u32 tmp, pipe;
3485 int i;
3486
3487 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3488 if (rdev->pm.dpm.new_active_crtc_count > 0)
3489 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3490 else
3491 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3492
3493 if (rdev->pm.dpm.new_active_crtc_count > 1)
3494 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3495 else
3496 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3497
3498 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3499
3500 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3501 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3502
3503 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3504 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3505 /* find the first active crtc */
3506 for (i = 0; i < rdev->num_crtc; i++) {
3507 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3508 break;
3509 }
3510 if (i == rdev->num_crtc)
3511 pipe = 0;
3512 else
3513 pipe = i;
3514
3515 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3516 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3517 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3518 }
3519
3520 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3521}
3522
3523static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3524{
3525 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3526
3527 if (enable) {
3528 if (pi->sclk_ss)
3529 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3530 } else {
3531 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3532 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3533 }
3534}
3535
3536static void si_setup_bsp(struct radeon_device *rdev)
3537{
3538 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3539 u32 xclk = radeon_get_xclk(rdev);
3540
3541 r600_calculate_u_and_p(pi->asi,
3542 xclk,
3543 16,
3544 &pi->bsp,
3545 &pi->bsu);
3546
3547 r600_calculate_u_and_p(pi->pasi,
3548 xclk,
3549 16,
3550 &pi->pbsp,
3551 &pi->pbsu);
3552
3553
3554 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3555 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3556
3557 WREG32(CG_BSP, pi->dsp);
3558}
3559
3560static void si_program_git(struct radeon_device *rdev)
3561{
3562 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3563}
3564
3565static void si_program_tp(struct radeon_device *rdev)
3566{
3567 int i;
3568 enum r600_td td = R600_TD_DFLT;
3569
3570 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3571 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3572
3573 if (td == R600_TD_AUTO)
3574 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3575 else
3576 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3577
3578 if (td == R600_TD_UP)
3579 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3580
3581 if (td == R600_TD_DOWN)
3582 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3583}
3584
3585static void si_program_tpp(struct radeon_device *rdev)
3586{
3587 WREG32(CG_TPC, R600_TPC_DFLT);
3588}
3589
3590static void si_program_sstp(struct radeon_device *rdev)
3591{
3592 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3593}
3594
3595static void si_enable_display_gap(struct radeon_device *rdev)
3596{
3597 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3598
3599 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3600 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) |
3601 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3602 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3603}
3604
3605static void si_program_vc(struct radeon_device *rdev)
3606{
3607 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3608
3609 WREG32(CG_FTV, pi->vrc);
3610}
3611
3612static void si_clear_vc(struct radeon_device *rdev)
3613{
3614 WREG32(CG_FTV, 0);
3615}
3616
3617static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3618{
3619 u8 mc_para_index;
3620
3621 if (memory_clock < 10000)
3622 mc_para_index = 0;
3623 else if (memory_clock >= 80000)
3624 mc_para_index = 0x0f;
3625 else
3626 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3627 return mc_para_index;
3628}
3629
3630static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3631{
3632 u8 mc_para_index;
3633
3634 if (strobe_mode) {
3635 if (memory_clock < 12500)
3636 mc_para_index = 0x00;
3637 else if (memory_clock > 47500)
3638 mc_para_index = 0x0f;
3639 else
3640 mc_para_index = (u8)((memory_clock - 10000) / 2500);
3641 } else {
3642 if (memory_clock < 65000)
3643 mc_para_index = 0x00;
3644 else if (memory_clock > 135000)
3645 mc_para_index = 0x0f;
3646 else
3647 mc_para_index = (u8)((memory_clock - 60000) / 5000);
3648 }
3649 return mc_para_index;
3650}
3651
3652static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3653{
3654 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3655 bool strobe_mode = false;
3656 u8 result = 0;
3657
3658 if (mclk <= pi->mclk_strobe_mode_threshold)
3659 strobe_mode = true;
3660
3661 if (pi->mem_gddr5)
3662 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3663 else
3664 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3665
3666 if (strobe_mode)
3667 result |= SISLANDS_SMC_STROBE_ENABLE;
3668
3669 return result;
3670}
3671
3672static int si_upload_firmware(struct radeon_device *rdev)
3673{
3674 struct si_power_info *si_pi = si_get_pi(rdev);
3675 int ret;
3676
3677 si_reset_smc(rdev);
3678 si_stop_smc_clock(rdev);
3679
3680 ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3681
3682 return ret;
3683}
3684
3685static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3686 const struct atom_voltage_table *table,
3687 const struct radeon_phase_shedding_limits_table *limits)
3688{
3689 u32 data, num_bits, num_levels;
3690
3691 if ((table == NULL) || (limits == NULL))
3692 return false;
3693
3694 data = table->mask_low;
3695
3696 num_bits = hweight32(data);
3697
3698 if (num_bits == 0)
3699 return false;
3700
3701 num_levels = (1 << num_bits);
3702
3703 if (table->count != num_levels)
3704 return false;
3705
3706 if (limits->count != (num_levels - 1))
3707 return false;
3708
3709 return true;
3710}
3711
3712static void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3713 struct atom_voltage_table *voltage_table)
3714{
3715 unsigned int i, diff;
3716
3717 if (voltage_table->count <= SISLANDS_MAX_NO_VREG_STEPS)
3718 return;
3719
3720 diff = voltage_table->count - SISLANDS_MAX_NO_VREG_STEPS;
3721
3722 for (i= 0; i < SISLANDS_MAX_NO_VREG_STEPS; i++)
3723 voltage_table->entries[i] = voltage_table->entries[i + diff];
3724
3725 voltage_table->count = SISLANDS_MAX_NO_VREG_STEPS;
3726}
3727
3728static int si_construct_voltage_tables(struct radeon_device *rdev)
3729{
3730 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3731 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3732 struct si_power_info *si_pi = si_get_pi(rdev);
3733 int ret;
3734
3735 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3736 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3737 if (ret)
3738 return ret;
3739
3740 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3741 si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddc_voltage_table);
3742
3743 if (eg_pi->vddci_control) {
3744 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3745 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3746 if (ret)
3747 return ret;
3748
3749 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3750 si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddci_voltage_table);
3751 }
3752
3753 if (pi->mvdd_control) {
3754 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
3755 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
3756
3757 if (ret) {
3758 pi->mvdd_control = false;
3759 return ret;
3760 }
3761
3762 if (si_pi->mvdd_voltage_table.count == 0) {
3763 pi->mvdd_control = false;
3764 return -EINVAL;
3765 }
3766
3767 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3768 si_trim_voltage_table_to_fit_state_table(rdev, &si_pi->mvdd_voltage_table);
3769 }
3770
3771 if (si_pi->vddc_phase_shed_control) {
3772 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3773 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
3774 if (ret)
3775 si_pi->vddc_phase_shed_control = false;
3776
3777 if ((si_pi->vddc_phase_shed_table.count == 0) ||
3778 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
3779 si_pi->vddc_phase_shed_control = false;
3780 }
3781
3782 return 0;
3783}
3784
3785static void si_populate_smc_voltage_table(struct radeon_device *rdev,
3786 const struct atom_voltage_table *voltage_table,
3787 SISLANDS_SMC_STATETABLE *table)
3788{
3789 unsigned int i;
3790
3791 for (i = 0; i < voltage_table->count; i++)
3792 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
3793}
3794
3795static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
3796 SISLANDS_SMC_STATETABLE *table)
3797{
3798 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3799 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3800 struct si_power_info *si_pi = si_get_pi(rdev);
3801 u8 i;
3802
3803 if (eg_pi->vddc_voltage_table.count) {
3804 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
3805 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3806 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
3807
3808 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
3809 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
3810 table->maxVDDCIndexInPPTable = i;
3811 break;
3812 }
3813 }
3814 }
3815
3816 if (eg_pi->vddci_voltage_table.count) {
3817 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
3818
3819 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
3820 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
3821 }
3822
3823
3824 if (si_pi->mvdd_voltage_table.count) {
3825 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
3826
3827 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
3828 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
3829 }
3830
3831 if (si_pi->vddc_phase_shed_control) {
3832 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
3833 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
3834 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
3835
3836 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3837 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
3838
3839 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
3840 (u32)si_pi->vddc_phase_shed_table.phase_delay);
3841 } else {
3842 si_pi->vddc_phase_shed_control = false;
3843 }
3844 }
3845
3846 return 0;
3847}
3848
3849static int si_populate_voltage_value(struct radeon_device *rdev,
3850 const struct atom_voltage_table *table,
3851 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3852{
3853 unsigned int i;
3854
3855 for (i = 0; i < table->count; i++) {
3856 if (value <= table->entries[i].value) {
3857 voltage->index = (u8)i;
3858 voltage->value = cpu_to_be16(table->entries[i].value);
3859 break;
3860 }
3861 }
3862
3863 if (i >= table->count)
3864 return -EINVAL;
3865
3866 return 0;
3867}
3868
3869static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
3870 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3871{
3872 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3873 struct si_power_info *si_pi = si_get_pi(rdev);
3874
3875 if (pi->mvdd_control) {
3876 if (mclk <= pi->mvdd_split_frequency)
3877 voltage->index = 0;
3878 else
3879 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
3880
3881 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
3882 }
3883 return 0;
3884}
3885
3886static int si_get_std_voltage_value(struct radeon_device *rdev,
3887 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
3888 u16 *std_voltage)
3889{
3890 u16 v_index;
3891 bool voltage_found = false;
3892 *std_voltage = be16_to_cpu(voltage->value);
3893
3894 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
3895 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
3896 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
3897 return -EINVAL;
3898
3899 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
3900 if (be16_to_cpu(voltage->value) ==
3901 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
3902 voltage_found = true;
3903 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
3904 *std_voltage =
3905 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
3906 else
3907 *std_voltage =
3908 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
3909 break;
3910 }
3911 }
3912
3913 if (!voltage_found) {
3914 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
3915 if (be16_to_cpu(voltage->value) <=
3916 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
3917 voltage_found = true;
3918 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
3919 *std_voltage =
3920 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
3921 else
3922 *std_voltage =
3923 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
3924 break;
3925 }
3926 }
3927 }
3928 } else {
3929 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
3930 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
3931 }
3932 }
3933
3934 return 0;
3935}
3936
3937static int si_populate_std_voltage_value(struct radeon_device *rdev,
3938 u16 value, u8 index,
3939 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3940{
3941 voltage->index = index;
3942 voltage->value = cpu_to_be16(value);
3943
3944 return 0;
3945}
3946
3947static int si_populate_phase_shedding_value(struct radeon_device *rdev,
3948 const struct radeon_phase_shedding_limits_table *limits,
3949 u16 voltage, u32 sclk, u32 mclk,
3950 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
3951{
3952 unsigned int i;
3953
3954 for (i = 0; i < limits->count; i++) {
3955 if ((voltage <= limits->entries[i].voltage) &&
3956 (sclk <= limits->entries[i].sclk) &&
3957 (mclk <= limits->entries[i].mclk))
3958 break;
3959 }
3960
3961 smc_voltage->phase_settings = (u8)i;
3962
3963 return 0;
3964}
3965
3966static int si_init_arb_table_index(struct radeon_device *rdev)
3967{
3968 struct si_power_info *si_pi = si_get_pi(rdev);
3969 u32 tmp;
3970 int ret;
3971
3972 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
3973 if (ret)
3974 return ret;
3975
3976 tmp &= 0x00FFFFFF;
3977 tmp |= MC_CG_ARB_FREQ_F1 << 24;
3978
3979 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
3980}
3981
3982static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
3983{
3984 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
3985}
3986
3987static int si_reset_to_default(struct radeon_device *rdev)
3988{
3989 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
3990 0 : -EINVAL;
3991}
3992
3993static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
3994{
3995 struct si_power_info *si_pi = si_get_pi(rdev);
3996 u32 tmp;
3997 int ret;
3998
3999 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4000 &tmp, si_pi->sram_end);
4001 if (ret)
4002 return ret;
4003
4004 tmp = (tmp >> 24) & 0xff;
4005
4006 if (tmp == MC_CG_ARB_FREQ_F0)
4007 return 0;
4008
4009 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4010}
4011
4012static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4013 u32 engine_clock)
4014{
4015 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4016 u32 dram_rows;
4017 u32 dram_refresh_rate;
4018 u32 mc_arb_rfsh_rate;
4019 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4020
4021 if (pi->mem_gddr5)
4022 dram_rows = 1 << (tmp + 10);
4023 else
4024 dram_rows = DDR3_DRAM_ROWS;
4025
4026 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4027 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4028
4029 return mc_arb_rfsh_rate;
4030}
4031
4032static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4033 struct rv7xx_pl *pl,
4034 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4035{
4036 u32 dram_timing;
4037 u32 dram_timing2;
4038 u32 burst_time;
4039
4040 arb_regs->mc_arb_rfsh_rate =
4041 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4042
4043 radeon_atom_set_engine_dram_timings(rdev,
4044 pl->sclk,
4045 pl->mclk);
4046
4047 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4048 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4049 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4050
4051 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4052 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4053 arb_regs->mc_arb_burst_time = (u8)burst_time;
4054
4055 return 0;
4056}
4057
4058static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4059 struct radeon_ps *radeon_state,
4060 unsigned int first_arb_set)
4061{
4062 struct si_power_info *si_pi = si_get_pi(rdev);
4063 struct ni_ps *state = ni_get_ps(radeon_state);
4064 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4065 int i, ret = 0;
4066
4067 for (i = 0; i < state->performance_level_count; i++) {
4068 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4069 if (ret)
4070 break;
4071 ret = si_copy_bytes_to_smc(rdev,
4072 si_pi->arb_table_start +
4073 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4074 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4075 (u8 *)&arb_regs,
4076 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4077 si_pi->sram_end);
4078 if (ret)
4079 break;
4080 }
4081
4082 return ret;
4083}
4084
4085static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4086 struct radeon_ps *radeon_new_state)
4087{
4088 return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4089 SISLANDS_DRIVER_STATE_ARB_INDEX);
4090}
4091
4092static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4093 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4094{
4095 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4096 struct si_power_info *si_pi = si_get_pi(rdev);
4097
4098 if (pi->mvdd_control)
4099 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4100 si_pi->mvdd_bootup_value, voltage);
4101
4102 return 0;
4103}
4104
4105static int si_populate_smc_initial_state(struct radeon_device *rdev,
4106 struct radeon_ps *radeon_initial_state,
4107 SISLANDS_SMC_STATETABLE *table)
4108{
4109 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4110 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4111 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4112 struct si_power_info *si_pi = si_get_pi(rdev);
4113 u32 reg;
4114 int ret;
4115
4116 table->initialState.levels[0].mclk.vDLL_CNTL =
4117 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4118 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4119 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4120 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4121 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4122 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4123 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4124 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4125 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4126 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4127 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4128 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4129 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4130 table->initialState.levels[0].mclk.vMPLL_SS =
4131 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4132 table->initialState.levels[0].mclk.vMPLL_SS2 =
4133 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4134
4135 table->initialState.levels[0].mclk.mclk_value =
4136 cpu_to_be32(initial_state->performance_levels[0].mclk);
4137
4138 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4139 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4140 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4141 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4142 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4143 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4144 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4145 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4146 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4147 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4148 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4149 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4150
4151 table->initialState.levels[0].sclk.sclk_value =
4152 cpu_to_be32(initial_state->performance_levels[0].sclk);
4153
4154 table->initialState.levels[0].arbRefreshState =
4155 SISLANDS_INITIAL_STATE_ARB_INDEX;
4156
4157 table->initialState.levels[0].ACIndex = 0;
4158
4159 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4160 initial_state->performance_levels[0].vddc,
4161 &table->initialState.levels[0].vddc);
4162
4163 if (!ret) {
4164 u16 std_vddc;
4165
4166 ret = si_get_std_voltage_value(rdev,
4167 &table->initialState.levels[0].vddc,
4168 &std_vddc);
4169 if (!ret)
4170 si_populate_std_voltage_value(rdev, std_vddc,
4171 table->initialState.levels[0].vddc.index,
4172 &table->initialState.levels[0].std_vddc);
4173 }
4174
4175 if (eg_pi->vddci_control)
4176 si_populate_voltage_value(rdev,
4177 &eg_pi->vddci_voltage_table,
4178 initial_state->performance_levels[0].vddci,
4179 &table->initialState.levels[0].vddci);
4180
4181 if (si_pi->vddc_phase_shed_control)
4182 si_populate_phase_shedding_value(rdev,
4183 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4184 initial_state->performance_levels[0].vddc,
4185 initial_state->performance_levels[0].sclk,
4186 initial_state->performance_levels[0].mclk,
4187 &table->initialState.levels[0].vddc);
4188
4189 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4190
4191 reg = CG_R(0xffff) | CG_L(0);
4192 table->initialState.levels[0].aT = cpu_to_be32(reg);
4193
4194 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4195
4196 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4197
4198 if (pi->mem_gddr5) {
4199 table->initialState.levels[0].strobeMode =
4200 si_get_strobe_mode_settings(rdev,
4201 initial_state->performance_levels[0].mclk);
4202
4203 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4204 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4205 else
4206 table->initialState.levels[0].mcFlags = 0;
4207 }
4208
4209 table->initialState.levelCount = 1;
4210
4211 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4212
4213 table->initialState.levels[0].dpm2.MaxPS = 0;
4214 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4215 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4216 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4217 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4218
4219 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4220 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4221
4222 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4223 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4224
4225 return 0;
4226}
4227
4228static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4229 SISLANDS_SMC_STATETABLE *table)
4230{
4231 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4232 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4233 struct si_power_info *si_pi = si_get_pi(rdev);
4234 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4235 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4236 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4237 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4238 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4239 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4240 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4241 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4242 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4243 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4244 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4245 u32 reg;
4246 int ret;
4247
4248 table->ACPIState = table->initialState;
4249
4250 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4251
4252 if (pi->acpi_vddc) {
4253 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4254 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4255 if (!ret) {
4256 u16 std_vddc;
4257
4258 ret = si_get_std_voltage_value(rdev,
4259 &table->ACPIState.levels[0].vddc, &std_vddc);
4260 if (!ret)
4261 si_populate_std_voltage_value(rdev, std_vddc,
4262 table->ACPIState.levels[0].vddc.index,
4263 &table->ACPIState.levels[0].std_vddc);
4264 }
4265 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4266
4267 if (si_pi->vddc_phase_shed_control) {
4268 si_populate_phase_shedding_value(rdev,
4269 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4270 pi->acpi_vddc,
4271 0,
4272 0,
4273 &table->ACPIState.levels[0].vddc);
4274 }
4275 } else {
4276 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4277 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4278 if (!ret) {
4279 u16 std_vddc;
4280
4281 ret = si_get_std_voltage_value(rdev,
4282 &table->ACPIState.levels[0].vddc, &std_vddc);
4283
4284 if (!ret)
4285 si_populate_std_voltage_value(rdev, std_vddc,
4286 table->ACPIState.levels[0].vddc.index,
4287 &table->ACPIState.levels[0].std_vddc);
4288 }
4289 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4290 si_pi->sys_pcie_mask,
4291 si_pi->boot_pcie_gen,
4292 RADEON_PCIE_GEN1);
4293
4294 if (si_pi->vddc_phase_shed_control)
4295 si_populate_phase_shedding_value(rdev,
4296 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4297 pi->min_vddc_in_table,
4298 0,
4299 0,
4300 &table->ACPIState.levels[0].vddc);
4301 }
4302
4303 if (pi->acpi_vddc) {
4304 if (eg_pi->acpi_vddci)
4305 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4306 eg_pi->acpi_vddci,
4307 &table->ACPIState.levels[0].vddci);
4308 }
4309
4310 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4311 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4312
4313 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4314
4315 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4316 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4317
4318 table->ACPIState.levels[0].mclk.vDLL_CNTL =
4319 cpu_to_be32(dll_cntl);
4320 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4321 cpu_to_be32(mclk_pwrmgt_cntl);
4322 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4323 cpu_to_be32(mpll_ad_func_cntl);
4324 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4325 cpu_to_be32(mpll_dq_func_cntl);
4326 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4327 cpu_to_be32(mpll_func_cntl);
4328 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4329 cpu_to_be32(mpll_func_cntl_1);
4330 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4331 cpu_to_be32(mpll_func_cntl_2);
4332 table->ACPIState.levels[0].mclk.vMPLL_SS =
4333 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4334 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4335 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4336
4337 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4338 cpu_to_be32(spll_func_cntl);
4339 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4340 cpu_to_be32(spll_func_cntl_2);
4341 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4342 cpu_to_be32(spll_func_cntl_3);
4343 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4344 cpu_to_be32(spll_func_cntl_4);
4345
4346 table->ACPIState.levels[0].mclk.mclk_value = 0;
4347 table->ACPIState.levels[0].sclk.sclk_value = 0;
4348
4349 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4350
4351 if (eg_pi->dynamic_ac_timing)
4352 table->ACPIState.levels[0].ACIndex = 0;
4353
4354 table->ACPIState.levels[0].dpm2.MaxPS = 0;
4355 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4356 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4357 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4358 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4359
4360 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4361 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4362
4363 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4364 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4365
4366 return 0;
4367}
4368
4369static int si_populate_ulv_state(struct radeon_device *rdev,
4370 SISLANDS_SMC_SWSTATE *state)
4371{
4372 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4373 struct si_power_info *si_pi = si_get_pi(rdev);
4374 struct si_ulv_param *ulv = &si_pi->ulv;
4375 u32 sclk_in_sr = 1350; /* ??? */
4376 int ret;
4377
4378 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4379 &state->levels[0]);
4380 if (!ret) {
4381 if (eg_pi->sclk_deep_sleep) {
4382 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4383 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4384 else
4385 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4386 }
4387 if (ulv->one_pcie_lane_in_ulv)
4388 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4389 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4390 state->levels[0].ACIndex = 1;
4391 state->levels[0].std_vddc = state->levels[0].vddc;
4392 state->levelCount = 1;
4393
4394 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4395 }
4396
4397 return ret;
4398}
4399
4400static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4401{
4402 struct si_power_info *si_pi = si_get_pi(rdev);
4403 struct si_ulv_param *ulv = &si_pi->ulv;
4404 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4405 int ret;
4406
4407 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4408 &arb_regs);
4409 if (ret)
4410 return ret;
4411
4412 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4413 ulv->volt_change_delay);
4414
4415 ret = si_copy_bytes_to_smc(rdev,
4416 si_pi->arb_table_start +
4417 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4418 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4419 (u8 *)&arb_regs,
4420 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4421 si_pi->sram_end);
4422
4423 return ret;
4424}
4425
4426static void si_get_mvdd_configuration(struct radeon_device *rdev)
4427{
4428 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4429
4430 pi->mvdd_split_frequency = 30000;
4431}
4432
4433static int si_init_smc_table(struct radeon_device *rdev)
4434{
4435 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4436 struct si_power_info *si_pi = si_get_pi(rdev);
4437 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4438 const struct si_ulv_param *ulv = &si_pi->ulv;
4439 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
4440 int ret;
4441 u32 lane_width;
4442 u32 vr_hot_gpio;
4443
4444 si_populate_smc_voltage_tables(rdev, table);
4445
4446 switch (rdev->pm.int_thermal_type) {
4447 case THERMAL_TYPE_SI:
4448 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4449 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4450 break;
4451 case THERMAL_TYPE_NONE:
4452 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4453 break;
4454 default:
4455 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4456 break;
4457 }
4458
4459 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4460 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4461
4462 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4463 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4464 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4465 }
4466
4467 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4468 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4469
4470 if (pi->mem_gddr5)
4471 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4472
4473 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4474 table->systemFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4475
4476 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4477 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4478 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4479 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4480 vr_hot_gpio);
4481 }
4482
4483 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4484 if (ret)
4485 return ret;
4486
4487 ret = si_populate_smc_acpi_state(rdev, table);
4488 if (ret)
4489 return ret;
4490
4491 table->driverState = table->initialState;
4492
4493 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4494 SISLANDS_INITIAL_STATE_ARB_INDEX);
4495 if (ret)
4496 return ret;
4497
4498 if (ulv->supported && ulv->pl.vddc) {
4499 ret = si_populate_ulv_state(rdev, &table->ULVState);
4500 if (ret)
4501 return ret;
4502
4503 ret = si_program_ulv_memory_timing_parameters(rdev);
4504 if (ret)
4505 return ret;
4506
4507 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4508 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4509
4510 lane_width = radeon_get_pcie_lanes(rdev);
4511 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4512 } else {
4513 table->ULVState = table->initialState;
4514 }
4515
4516 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4517 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4518 si_pi->sram_end);
4519}
4520
4521static int si_calculate_sclk_params(struct radeon_device *rdev,
4522 u32 engine_clock,
4523 SISLANDS_SMC_SCLK_VALUE *sclk)
4524{
4525 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4526 struct si_power_info *si_pi = si_get_pi(rdev);
4527 struct atom_clock_dividers dividers;
4528 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4529 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4530 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4531 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4532 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4533 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4534 u64 tmp;
4535 u32 reference_clock = rdev->clock.spll.reference_freq;
4536 u32 reference_divider;
4537 u32 fbdiv;
4538 int ret;
4539
4540 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4541 engine_clock, false, &dividers);
4542 if (ret)
4543 return ret;
4544
4545 reference_divider = 1 + dividers.ref_div;
4546
4547 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4548 do_div(tmp, reference_clock);
4549 fbdiv = (u32) tmp;
4550
4551 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4552 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4553 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4554
4555 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4556 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4557
4558 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4559 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4560 spll_func_cntl_3 |= SPLL_DITHEN;
4561
4562 if (pi->sclk_ss) {
4563 struct radeon_atom_ss ss;
4564 u32 vco_freq = engine_clock * dividers.post_div;
4565
4566 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4567 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4568 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4569 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4570
4571 cg_spll_spread_spectrum &= ~CLK_S_MASK;
4572 cg_spll_spread_spectrum |= CLK_S(clk_s);
4573 cg_spll_spread_spectrum |= SSEN;
4574
4575 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4576 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4577 }
4578 }
4579
4580 sclk->sclk_value = engine_clock;
4581 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4582 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4583 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4584 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4585 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4586 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4587
4588 return 0;
4589}
4590
4591static int si_populate_sclk_value(struct radeon_device *rdev,
4592 u32 engine_clock,
4593 SISLANDS_SMC_SCLK_VALUE *sclk)
4594{
4595 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4596 int ret;
4597
4598 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4599 if (!ret) {
4600 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4601 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4602 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4603 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4604 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4605 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4606 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4607 }
4608
4609 return ret;
4610}
4611
4612static int si_populate_mclk_value(struct radeon_device *rdev,
4613 u32 engine_clock,
4614 u32 memory_clock,
4615 SISLANDS_SMC_MCLK_VALUE *mclk,
4616 bool strobe_mode,
4617 bool dll_state_on)
4618{
4619 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4620 struct si_power_info *si_pi = si_get_pi(rdev);
4621 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4622 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4623 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4624 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4625 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4626 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4627 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4628 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4629 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4630 struct atom_mpll_param mpll_param;
4631 int ret;
4632
4633 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4634 if (ret)
4635 return ret;
4636
4637 mpll_func_cntl &= ~BWCTRL_MASK;
4638 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4639
4640 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4641 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4642 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4643
4644 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4645 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4646
4647 if (pi->mem_gddr5) {
4648 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4649 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4650 YCLK_POST_DIV(mpll_param.post_div);
4651 }
4652
4653 if (pi->mclk_ss) {
4654 struct radeon_atom_ss ss;
4655 u32 freq_nom;
4656 u32 tmp;
4657 u32 reference_clock = rdev->clock.mpll.reference_freq;
4658
4659 if (pi->mem_gddr5)
4660 freq_nom = memory_clock * 4;
4661 else
4662 freq_nom = memory_clock * 2;
4663
4664 tmp = freq_nom / reference_clock;
4665 tmp = tmp * tmp;
4666 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4667 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4668 u32 clks = reference_clock * 5 / ss.rate;
4669 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4670
4671 mpll_ss1 &= ~CLKV_MASK;
4672 mpll_ss1 |= CLKV(clkv);
4673
4674 mpll_ss2 &= ~CLKS_MASK;
4675 mpll_ss2 |= CLKS(clks);
4676 }
4677 }
4678
4679 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4680 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4681
4682 if (dll_state_on)
4683 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4684 else
4685 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4686
4687 mclk->mclk_value = cpu_to_be32(memory_clock);
4688 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4689 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4690 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4691 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4692 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4693 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4694 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4695 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4696 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4697
4698 return 0;
4699}
4700
4701static void si_populate_smc_sp(struct radeon_device *rdev,
4702 struct radeon_ps *radeon_state,
4703 SISLANDS_SMC_SWSTATE *smc_state)
4704{
4705 struct ni_ps *ps = ni_get_ps(radeon_state);
4706 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4707 int i;
4708
4709 for (i = 0; i < ps->performance_level_count - 1; i++)
4710 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4711
4712 smc_state->levels[ps->performance_level_count - 1].bSP =
4713 cpu_to_be32(pi->psp);
4714}
4715
4716static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4717 struct rv7xx_pl *pl,
4718 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4719{
4720 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4721 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4722 struct si_power_info *si_pi = si_get_pi(rdev);
4723 int ret;
4724 bool dll_state_on;
4725 u16 std_vddc;
4726 bool gmc_pg = false;
4727
4728 if (eg_pi->pcie_performance_request &&
4729 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4730 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4731 else
4732 level->gen2PCIE = (u8)pl->pcie_gen;
4733
4734 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4735 if (ret)
4736 return ret;
4737
4738 level->mcFlags = 0;
4739
4740 if (pi->mclk_stutter_mode_threshold &&
4741 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
4742 !eg_pi->uvd_enabled &&
4743 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
4744 (rdev->pm.dpm.new_active_crtc_count <= 2)) {
4745 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
4746
4747 if (gmc_pg)
4748 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
4749 }
4750
4751 if (pi->mem_gddr5) {
4752 if (pl->mclk > pi->mclk_edc_enable_threshold)
4753 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
4754
4755 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
4756 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
4757
4758 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
4759
4760 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
4761 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
4762 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
4763 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4764 else
4765 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
4766 } else {
4767 dll_state_on = false;
4768 }
4769 } else {
4770 level->strobeMode = si_get_strobe_mode_settings(rdev,
4771 pl->mclk);
4772
4773 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4774 }
4775
4776 ret = si_populate_mclk_value(rdev,
4777 pl->sclk,
4778 pl->mclk,
4779 &level->mclk,
4780 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
4781 if (ret)
4782 return ret;
4783
4784 ret = si_populate_voltage_value(rdev,
4785 &eg_pi->vddc_voltage_table,
4786 pl->vddc, &level->vddc);
4787 if (ret)
4788 return ret;
4789
4790
4791 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
4792 if (ret)
4793 return ret;
4794
4795 ret = si_populate_std_voltage_value(rdev, std_vddc,
4796 level->vddc.index, &level->std_vddc);
4797 if (ret)
4798 return ret;
4799
4800 if (eg_pi->vddci_control) {
4801 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4802 pl->vddci, &level->vddci);
4803 if (ret)
4804 return ret;
4805 }
4806
4807 if (si_pi->vddc_phase_shed_control) {
4808 ret = si_populate_phase_shedding_value(rdev,
4809 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4810 pl->vddc,
4811 pl->sclk,
4812 pl->mclk,
4813 &level->vddc);
4814 if (ret)
4815 return ret;
4816 }
4817
4818 level->MaxPoweredUpCU = si_pi->max_cu;
4819
4820 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
4821
4822 return ret;
4823}
4824
4825static int si_populate_smc_t(struct radeon_device *rdev,
4826 struct radeon_ps *radeon_state,
4827 SISLANDS_SMC_SWSTATE *smc_state)
4828{
4829 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4830 struct ni_ps *state = ni_get_ps(radeon_state);
4831 u32 a_t;
4832 u32 t_l, t_h;
4833 u32 high_bsp;
4834 int i, ret;
4835
4836 if (state->performance_level_count >= 9)
4837 return -EINVAL;
4838
4839 if (state->performance_level_count < 2) {
4840 a_t = CG_R(0xffff) | CG_L(0);
4841 smc_state->levels[0].aT = cpu_to_be32(a_t);
4842 return 0;
4843 }
4844
4845 smc_state->levels[0].aT = cpu_to_be32(0);
4846
4847 for (i = 0; i <= state->performance_level_count - 2; i++) {
4848 ret = r600_calculate_at(
4849 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
4850 100 * R600_AH_DFLT,
4851 state->performance_levels[i + 1].sclk,
4852 state->performance_levels[i].sclk,
4853 &t_l,
4854 &t_h);
4855
4856 if (ret) {
4857 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
4858 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
4859 }
4860
4861 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
4862 a_t |= CG_R(t_l * pi->bsp / 20000);
4863 smc_state->levels[i].aT = cpu_to_be32(a_t);
4864
4865 high_bsp = (i == state->performance_level_count - 2) ?
4866 pi->pbsp : pi->bsp;
4867 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
4868 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
4869 }
4870
4871 return 0;
4872}
4873
4874static int si_disable_ulv(struct radeon_device *rdev)
4875{
4876 struct si_power_info *si_pi = si_get_pi(rdev);
4877 struct si_ulv_param *ulv = &si_pi->ulv;
4878
4879 if (ulv->supported)
4880 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
4881 0 : -EINVAL;
4882
4883 return 0;
4884}
4885
4886static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
4887 struct radeon_ps *radeon_state)
4888{
4889 const struct si_power_info *si_pi = si_get_pi(rdev);
4890 const struct si_ulv_param *ulv = &si_pi->ulv;
4891 const struct ni_ps *state = ni_get_ps(radeon_state);
4892 int i;
4893
4894 if (state->performance_levels[0].mclk != ulv->pl.mclk)
4895 return false;
4896
4897 /* XXX validate against display requirements! */
4898
4899 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
4900 if (rdev->clock.current_dispclk <=
4901 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
4902 if (ulv->pl.vddc <
4903 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
4904 return false;
4905 }
4906 }
4907
4908 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
4909 return false;
4910
4911 return true;
4912}
4913
4914static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
4915 struct radeon_ps *radeon_new_state)
4916{
4917 const struct si_power_info *si_pi = si_get_pi(rdev);
4918 const struct si_ulv_param *ulv = &si_pi->ulv;
4919
4920 if (ulv->supported) {
4921 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
4922 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
4923 0 : -EINVAL;
4924 }
4925 return 0;
4926}
4927
4928static int si_convert_power_state_to_smc(struct radeon_device *rdev,
4929 struct radeon_ps *radeon_state,
4930 SISLANDS_SMC_SWSTATE *smc_state)
4931{
4932 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4933 struct ni_power_info *ni_pi = ni_get_pi(rdev);
4934 struct si_power_info *si_pi = si_get_pi(rdev);
4935 struct ni_ps *state = ni_get_ps(radeon_state);
4936 int i, ret;
4937 u32 threshold;
4938 u32 sclk_in_sr = 1350; /* ??? */
4939
4940 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
4941 return -EINVAL;
4942
4943 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
4944
4945 if (radeon_state->vclk && radeon_state->dclk) {
4946 eg_pi->uvd_enabled = true;
4947 if (eg_pi->smu_uvd_hs)
4948 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
4949 } else {
4950 eg_pi->uvd_enabled = false;
4951 }
4952
4953 if (state->dc_compatible)
4954 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
4955
4956 smc_state->levelCount = 0;
4957 for (i = 0; i < state->performance_level_count; i++) {
4958 if (eg_pi->sclk_deep_sleep) {
4959 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
4960 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4961 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4962 else
4963 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4964 }
4965 }
4966
4967 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
4968 &smc_state->levels[i]);
4969 smc_state->levels[i].arbRefreshState =
4970 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
4971
4972 if (ret)
4973 return ret;
4974
4975 if (ni_pi->enable_power_containment)
4976 smc_state->levels[i].displayWatermark =
4977 (state->performance_levels[i].sclk < threshold) ?
4978 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
4979 else
4980 smc_state->levels[i].displayWatermark = (i < 2) ?
4981 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
4982
4983 if (eg_pi->dynamic_ac_timing)
4984 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
4985 else
4986 smc_state->levels[i].ACIndex = 0;
4987
4988 smc_state->levelCount++;
4989 }
4990
4991 si_write_smc_soft_register(rdev,
4992 SI_SMC_SOFT_REGISTER_watermark_threshold,
4993 threshold / 512);
4994
4995 si_populate_smc_sp(rdev, radeon_state, smc_state);
4996
4997 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
4998 if (ret)
4999 ni_pi->enable_power_containment = false;
5000
5001 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5002 if (ret)
5003 ni_pi->enable_sq_ramping = false;
5004
5005 return si_populate_smc_t(rdev, radeon_state, smc_state);
5006}
5007
5008static int si_upload_sw_state(struct radeon_device *rdev,
5009 struct radeon_ps *radeon_new_state)
5010{
5011 struct si_power_info *si_pi = si_get_pi(rdev);
5012 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5013 int ret;
5014 u32 address = si_pi->state_table_start +
5015 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5016 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5017 ((new_state->performance_level_count - 1) *
5018 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5019 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5020
5021 memset(smc_state, 0, state_size);
5022
5023 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5024 if (ret)
5025 return ret;
5026
5027 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5028 state_size, si_pi->sram_end);
5029
5030 return ret;
5031}
5032
5033static int si_upload_ulv_state(struct radeon_device *rdev)
5034{
5035 struct si_power_info *si_pi = si_get_pi(rdev);
5036 struct si_ulv_param *ulv = &si_pi->ulv;
5037 int ret = 0;
5038
5039 if (ulv->supported && ulv->pl.vddc) {
5040 u32 address = si_pi->state_table_start +
5041 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5042 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5043 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5044
5045 memset(smc_state, 0, state_size);
5046
5047 ret = si_populate_ulv_state(rdev, smc_state);
5048 if (!ret)
5049 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5050 state_size, si_pi->sram_end);
5051 }
5052
5053 return ret;
5054}
5055
5056static int si_upload_smc_data(struct radeon_device *rdev)
5057{
5058 struct radeon_crtc *radeon_crtc = NULL;
5059 int i;
5060
5061 if (rdev->pm.dpm.new_active_crtc_count == 0)
5062 return 0;
5063
5064 for (i = 0; i < rdev->num_crtc; i++) {
5065 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5066 radeon_crtc = rdev->mode_info.crtcs[i];
5067 break;
5068 }
5069 }
5070
5071 if (radeon_crtc == NULL)
5072 return 0;
5073
5074 if (radeon_crtc->line_time <= 0)
5075 return 0;
5076
5077 if (si_write_smc_soft_register(rdev,
5078 SI_SMC_SOFT_REGISTER_crtc_index,
5079 radeon_crtc->crtc_id) != PPSMC_Result_OK)
5080 return 0;
5081
5082 if (si_write_smc_soft_register(rdev,
5083 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5084 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5085 return 0;
5086
5087 if (si_write_smc_soft_register(rdev,
5088 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5089 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5090 return 0;
5091
5092 return 0;
5093}
5094
5095static int si_set_mc_special_registers(struct radeon_device *rdev,
5096 struct si_mc_reg_table *table)
5097{
5098 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5099 u8 i, j, k;
5100 u32 temp_reg;
5101
5102 for (i = 0, j = table->last; i < table->last; i++) {
5103 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5104 return -EINVAL;
5105 switch (table->mc_reg_address[i].s1 << 2) {
5106 case MC_SEQ_MISC1:
5107 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5108 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5109 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5110 for (k = 0; k < table->num_entries; k++)
5111 table->mc_reg_table_entry[k].mc_data[j] =
5112 ((temp_reg & 0xffff0000)) |
5113 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5114 j++;
5115 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5116 return -EINVAL;
5117
5118 temp_reg = RREG32(MC_PMG_CMD_MRS);
5119 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5120 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5121 for (k = 0; k < table->num_entries; k++) {
5122 table->mc_reg_table_entry[k].mc_data[j] =
5123 (temp_reg & 0xffff0000) |
5124 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5125 if (!pi->mem_gddr5)
5126 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5127 }
5128 j++;
5129 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5130 return -EINVAL;
5131
5132 if (!pi->mem_gddr5) {
5133 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5134 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5135 for (k = 0; k < table->num_entries; k++)
5136 table->mc_reg_table_entry[k].mc_data[j] =
5137 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5138 j++;
5139 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5140 return -EINVAL;
5141 }
5142 break;
5143 case MC_SEQ_RESERVE_M:
5144 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5145 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5146 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5147 for(k = 0; k < table->num_entries; k++)
5148 table->mc_reg_table_entry[k].mc_data[j] =
5149 (temp_reg & 0xffff0000) |
5150 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5151 j++;
5152 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5153 return -EINVAL;
5154 break;
5155 default:
5156 break;
5157 }
5158 }
5159
5160 table->last = j;
5161
5162 return 0;
5163}
5164
5165static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5166{
5167 bool result = true;
5168
5169 switch (in_reg) {
5170 case MC_SEQ_RAS_TIMING >> 2:
5171 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5172 break;
5173 case MC_SEQ_CAS_TIMING >> 2:
5174 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5175 break;
5176 case MC_SEQ_MISC_TIMING >> 2:
5177 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5178 break;
5179 case MC_SEQ_MISC_TIMING2 >> 2:
5180 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5181 break;
5182 case MC_SEQ_RD_CTL_D0 >> 2:
5183 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5184 break;
5185 case MC_SEQ_RD_CTL_D1 >> 2:
5186 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5187 break;
5188 case MC_SEQ_WR_CTL_D0 >> 2:
5189 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5190 break;
5191 case MC_SEQ_WR_CTL_D1 >> 2:
5192 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5193 break;
5194 case MC_PMG_CMD_EMRS >> 2:
5195 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5196 break;
5197 case MC_PMG_CMD_MRS >> 2:
5198 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5199 break;
5200 case MC_PMG_CMD_MRS1 >> 2:
5201 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5202 break;
5203 case MC_SEQ_PMG_TIMING >> 2:
5204 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5205 break;
5206 case MC_PMG_CMD_MRS2 >> 2:
5207 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5208 break;
5209 case MC_SEQ_WR_CTL_2 >> 2:
5210 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5211 break;
5212 default:
5213 result = false;
5214 break;
5215 }
5216
5217 return result;
5218}
5219
5220static void si_set_valid_flag(struct si_mc_reg_table *table)
5221{
5222 u8 i, j;
5223
5224 for (i = 0; i < table->last; i++) {
5225 for (j = 1; j < table->num_entries; j++) {
5226 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5227 table->valid_flag |= 1 << i;
5228 break;
5229 }
5230 }
5231 }
5232}
5233
5234static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5235{
5236 u32 i;
5237 u16 address;
5238
5239 for (i = 0; i < table->last; i++)
5240 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5241 address : table->mc_reg_address[i].s1;
5242
5243}
5244
5245static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5246 struct si_mc_reg_table *si_table)
5247{
5248 u8 i, j;
5249
5250 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5251 return -EINVAL;
5252 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5253 return -EINVAL;
5254
5255 for (i = 0; i < table->last; i++)
5256 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5257 si_table->last = table->last;
5258
5259 for (i = 0; i < table->num_entries; i++) {
5260 si_table->mc_reg_table_entry[i].mclk_max =
5261 table->mc_reg_table_entry[i].mclk_max;
5262 for (j = 0; j < table->last; j++) {
5263 si_table->mc_reg_table_entry[i].mc_data[j] =
5264 table->mc_reg_table_entry[i].mc_data[j];
5265 }
5266 }
5267 si_table->num_entries = table->num_entries;
5268
5269 return 0;
5270}
5271
5272static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5273{
5274 struct si_power_info *si_pi = si_get_pi(rdev);
5275 struct atom_mc_reg_table *table;
5276 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5277 u8 module_index = rv770_get_memory_module_index(rdev);
5278 int ret;
5279
5280 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5281 if (!table)
5282 return -ENOMEM;
5283
5284 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5285 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5286 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5287 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5288 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5289 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5290 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5291 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5292 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5293 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5294 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5295 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5296 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5297 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5298
5299 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5300 if (ret)
5301 goto init_mc_done;
5302
5303 ret = si_copy_vbios_mc_reg_table(table, si_table);
5304 if (ret)
5305 goto init_mc_done;
5306
5307 si_set_s0_mc_reg_index(si_table);
5308
5309 ret = si_set_mc_special_registers(rdev, si_table);
5310 if (ret)
5311 goto init_mc_done;
5312
5313 si_set_valid_flag(si_table);
5314
5315init_mc_done:
5316 kfree(table);
5317
5318 return ret;
5319
5320}
5321
5322static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5323 SMC_SIslands_MCRegisters *mc_reg_table)
5324{
5325 struct si_power_info *si_pi = si_get_pi(rdev);
5326 u32 i, j;
5327
5328 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5329 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5330 if (i >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
5331 break;
5332 mc_reg_table->address[i].s0 =
5333 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5334 mc_reg_table->address[i].s1 =
5335 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5336 i++;
5337 }
5338 }
5339 mc_reg_table->last = (u8)i;
5340}
5341
5342static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5343 SMC_SIslands_MCRegisterSet *data,
5344 u32 num_entries, u32 valid_flag)
5345{
5346 u32 i, j;
5347
5348 for(i = 0, j = 0; j < num_entries; j++) {
5349 if (valid_flag & (1 << j)) {
5350 data->value[i] = cpu_to_be32(entry->mc_data[j]);
5351 i++;
5352 }
5353 }
5354}
5355
5356static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5357 struct rv7xx_pl *pl,
5358 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5359{
5360 struct si_power_info *si_pi = si_get_pi(rdev);
5361 u32 i = 0;
5362
5363 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5364 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5365 break;
5366 }
5367
5368 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5369 --i;
5370
5371 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5372 mc_reg_table_data, si_pi->mc_reg_table.last,
5373 si_pi->mc_reg_table.valid_flag);
5374}
5375
5376static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5377 struct radeon_ps *radeon_state,
5378 SMC_SIslands_MCRegisters *mc_reg_table)
5379{
5380 struct ni_ps *state = ni_get_ps(radeon_state);
5381 int i;
5382
5383 for (i = 0; i < state->performance_level_count; i++) {
5384 si_convert_mc_reg_table_entry_to_smc(rdev,
5385 &state->performance_levels[i],
5386 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5387 }
5388}
5389
5390static int si_populate_mc_reg_table(struct radeon_device *rdev,
5391 struct radeon_ps *radeon_boot_state)
5392{
5393 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5394 struct si_power_info *si_pi = si_get_pi(rdev);
5395 struct si_ulv_param *ulv = &si_pi->ulv;
5396 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5397
5398 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5399
5400 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5401
5402 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5403
5404 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5405 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5406
5407 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5408 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5409 si_pi->mc_reg_table.last,
5410 si_pi->mc_reg_table.valid_flag);
5411
5412 if (ulv->supported && ulv->pl.vddc != 0)
5413 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5414 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5415 else
5416 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5417 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5418 si_pi->mc_reg_table.last,
5419 si_pi->mc_reg_table.valid_flag);
5420
5421 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5422
5423 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5424 (u8 *)smc_mc_reg_table,
5425 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5426}
5427
5428static int si_upload_mc_reg_table(struct radeon_device *rdev,
5429 struct radeon_ps *radeon_new_state)
5430{
5431 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5432 struct si_power_info *si_pi = si_get_pi(rdev);
5433 u32 address = si_pi->mc_reg_table_start +
5434 offsetof(SMC_SIslands_MCRegisters,
5435 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5436 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5437
5438 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5439
5440 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5441
5442
5443 return si_copy_bytes_to_smc(rdev, address,
5444 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5445 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5446 si_pi->sram_end);
5447
5448}
5449
5450static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5451{
5452 if (enable)
5453 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5454 else
5455 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5456}
5457
5458static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5459 struct radeon_ps *radeon_state)
5460{
5461 struct ni_ps *state = ni_get_ps(radeon_state);
5462 int i;
5463 u16 pcie_speed, max_speed = 0;
5464
5465 for (i = 0; i < state->performance_level_count; i++) {
5466 pcie_speed = state->performance_levels[i].pcie_gen;
5467 if (max_speed < pcie_speed)
5468 max_speed = pcie_speed;
5469 }
5470 return max_speed;
5471}
5472
5473static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5474{
5475 u32 speed_cntl;
5476
5477 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5478 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5479
5480 return (u16)speed_cntl;
5481}
5482
5483static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5484 struct radeon_ps *radeon_new_state,
5485 struct radeon_ps *radeon_current_state)
5486{
5487 struct si_power_info *si_pi = si_get_pi(rdev);
5488 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5489 enum radeon_pcie_gen current_link_speed;
5490
5491 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5492 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5493 else
5494 current_link_speed = si_pi->force_pcie_gen;
5495
5496 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5497 si_pi->pspp_notify_required = false;
5498 if (target_link_speed > current_link_speed) {
5499 switch (target_link_speed) {
5500#if defined(CONFIG_ACPI)
5501 case RADEON_PCIE_GEN3:
5502 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5503 break;
5504 si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5505 if (current_link_speed == RADEON_PCIE_GEN2)
5506 break;
5507 case RADEON_PCIE_GEN2:
5508 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5509 break;
5510#endif
5511 default:
5512 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5513 break;
5514 }
5515 } else {
5516 if (target_link_speed < current_link_speed)
5517 si_pi->pspp_notify_required = true;
5518 }
5519}
5520
5521static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5522 struct radeon_ps *radeon_new_state,
5523 struct radeon_ps *radeon_current_state)
5524{
5525 struct si_power_info *si_pi = si_get_pi(rdev);
5526 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5527 u8 request;
5528
5529 if (si_pi->pspp_notify_required) {
5530 if (target_link_speed == RADEON_PCIE_GEN3)
5531 request = PCIE_PERF_REQ_PECI_GEN3;
5532 else if (target_link_speed == RADEON_PCIE_GEN2)
5533 request = PCIE_PERF_REQ_PECI_GEN2;
5534 else
5535 request = PCIE_PERF_REQ_PECI_GEN1;
5536
5537 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5538 (si_get_current_pcie_speed(rdev) > 0))
5539 return;
5540
5541#if defined(CONFIG_ACPI)
5542 radeon_acpi_pcie_performance_request(rdev, request, false);
5543#endif
5544 }
5545}
5546
5547#if 0
5548static int si_ds_request(struct radeon_device *rdev,
5549 bool ds_status_on, u32 count_write)
5550{
5551 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5552
5553 if (eg_pi->sclk_deep_sleep) {
5554 if (ds_status_on)
5555 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5556 PPSMC_Result_OK) ?
5557 0 : -EINVAL;
5558 else
5559 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5560 PPSMC_Result_OK) ? 0 : -EINVAL;
5561 }
5562 return 0;
5563}
5564#endif
5565
5566static void si_set_max_cu_value(struct radeon_device *rdev)
5567{
5568 struct si_power_info *si_pi = si_get_pi(rdev);
5569
5570 if (rdev->family == CHIP_VERDE) {
5571 switch (rdev->pdev->device) {
5572 case 0x6820:
5573 case 0x6825:
5574 case 0x6821:
5575 case 0x6823:
5576 case 0x6827:
5577 si_pi->max_cu = 10;
5578 break;
5579 case 0x682D:
5580 case 0x6824:
5581 case 0x682F:
5582 case 0x6826:
5583 si_pi->max_cu = 8;
5584 break;
5585 case 0x6828:
5586 case 0x6830:
5587 case 0x6831:
5588 case 0x6838:
5589 case 0x6839:
5590 case 0x683D:
5591 si_pi->max_cu = 10;
5592 break;
5593 case 0x683B:
5594 case 0x683F:
5595 case 0x6829:
5596 si_pi->max_cu = 8;
5597 break;
5598 default:
5599 si_pi->max_cu = 0;
5600 break;
5601 }
5602 } else {
5603 si_pi->max_cu = 0;
5604 }
5605}
5606
5607static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5608 struct radeon_clock_voltage_dependency_table *table)
5609{
5610 u32 i;
5611 int j;
5612 u16 leakage_voltage;
5613
5614 if (table) {
5615 for (i = 0; i < table->count; i++) {
5616 switch (si_get_leakage_voltage_from_leakage_index(rdev,
5617 table->entries[i].v,
5618 &leakage_voltage)) {
5619 case 0:
5620 table->entries[i].v = leakage_voltage;
5621 break;
5622 case -EAGAIN:
5623 return -EINVAL;
5624 case -EINVAL:
5625 default:
5626 break;
5627 }
5628 }
5629
5630 for (j = (table->count - 2); j >= 0; j--) {
5631 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5632 table->entries[j].v : table->entries[j + 1].v;
5633 }
5634 }
5635 return 0;
5636}
5637
5638static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5639{
5640 int ret = 0;
5641
5642 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5643 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5644 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5645 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5646 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5647 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5648 return ret;
5649}
5650
5651static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5652 struct radeon_ps *radeon_new_state,
5653 struct radeon_ps *radeon_current_state)
5654{
5655 u32 lane_width;
5656 u32 new_lane_width =
5657 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5658 u32 current_lane_width =
5659 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5660
5661 if (new_lane_width != current_lane_width) {
5662 radeon_set_pcie_lanes(rdev, new_lane_width);
5663 lane_width = radeon_get_pcie_lanes(rdev);
5664 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5665 }
5666}
5667
5668void si_dpm_setup_asic(struct radeon_device *rdev)
5669{
5670 rv770_get_memory_type(rdev);
5671 si_read_clock_registers(rdev);
5672 si_enable_acpi_power_management(rdev);
5673}
5674
5675static int si_set_thermal_temperature_range(struct radeon_device *rdev,
5676 int min_temp, int max_temp)
5677{
5678 int low_temp = 0 * 1000;
5679 int high_temp = 255 * 1000;
5680
5681 if (low_temp < min_temp)
5682 low_temp = min_temp;
5683 if (high_temp > max_temp)
5684 high_temp = max_temp;
5685 if (high_temp < low_temp) {
5686 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5687 return -EINVAL;
5688 }
5689
5690 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
5691 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
5692 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
5693
5694 rdev->pm.dpm.thermal.min_temp = low_temp;
5695 rdev->pm.dpm.thermal.max_temp = high_temp;
5696
5697 return 0;
5698}
5699
5700int si_dpm_enable(struct radeon_device *rdev)
5701{
5702 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5703 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5704 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5705 int ret;
5706
5707 if (si_is_smc_running(rdev))
5708 return -EINVAL;
5709 if (pi->voltage_control)
5710 si_enable_voltage_control(rdev, true);
5711 if (pi->mvdd_control)
5712 si_get_mvdd_configuration(rdev);
5713 if (pi->voltage_control) {
5714 ret = si_construct_voltage_tables(rdev);
5715 if (ret)
5716 return ret;
5717 }
5718 if (eg_pi->dynamic_ac_timing) {
5719 ret = si_initialize_mc_reg_table(rdev);
5720 if (ret)
5721 eg_pi->dynamic_ac_timing = false;
5722 }
5723 if (pi->dynamic_ss)
5724 si_enable_spread_spectrum(rdev, true);
5725 if (pi->thermal_protection)
5726 si_enable_thermal_protection(rdev, true);
5727 si_setup_bsp(rdev);
5728 si_program_git(rdev);
5729 si_program_tp(rdev);
5730 si_program_tpp(rdev);
5731 si_program_sstp(rdev);
5732 si_enable_display_gap(rdev);
5733 si_program_vc(rdev);
5734 ret = si_upload_firmware(rdev);
5735 if (ret)
5736 return ret;
5737 ret = si_process_firmware_header(rdev);
5738 if (ret)
5739 return ret;
5740 ret = si_initial_switch_from_arb_f0_to_f1(rdev);
5741 if (ret)
5742 return ret;
5743 ret = si_init_smc_table(rdev);
5744 if (ret)
5745 return ret;
5746 ret = si_init_smc_spll_table(rdev);
5747 if (ret)
5748 return ret;
5749 ret = si_init_arb_table_index(rdev);
5750 if (ret)
5751 return ret;
5752 if (eg_pi->dynamic_ac_timing) {
5753 ret = si_populate_mc_reg_table(rdev, boot_ps);
5754 if (ret)
5755 return ret;
5756 }
5757 ret = si_initialize_smc_cac_tables(rdev);
5758 if (ret)
5759 return ret;
5760 ret = si_initialize_hardware_cac_manager(rdev);
5761 if (ret)
5762 return ret;
5763 ret = si_initialize_smc_dte_tables(rdev);
5764 if (ret)
5765 return ret;
5766 ret = si_populate_smc_tdp_limits(rdev, boot_ps);
5767 if (ret)
5768 return ret;
5769 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
5770 if (ret)
5771 return ret;
5772 si_program_response_times(rdev);
5773 si_program_ds_registers(rdev);
5774 si_dpm_start_smc(rdev);
5775 ret = si_notify_smc_display_change(rdev, false);
5776 if (ret)
5777 return ret;
5778 si_enable_sclk_control(rdev, true);
5779 si_start_dpm(rdev);
5780
5781 if (rdev->irq.installed &&
5782 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
5783 PPSMC_Result result;
5784
5785 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
5786 if (ret)
5787 return ret;
5788 rdev->irq.dpm_thermal = true;
5789 radeon_irq_set(rdev);
5790 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5791
5792 if (result != PPSMC_Result_OK)
5793 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5794 }
5795
5796 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5797
5798 ni_update_current_ps(rdev, boot_ps);
5799
5800 return 0;
5801}
5802
5803void si_dpm_disable(struct radeon_device *rdev)
5804{
5805 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5806 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5807
5808 if (!si_is_smc_running(rdev))
5809 return;
5810 si_disable_ulv(rdev);
5811 si_clear_vc(rdev);
5812 if (pi->thermal_protection)
5813 si_enable_thermal_protection(rdev, false);
5814 si_enable_power_containment(rdev, boot_ps, false);
5815 si_enable_smc_cac(rdev, boot_ps, false);
5816 si_enable_spread_spectrum(rdev, false);
5817 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5818 si_stop_dpm(rdev);
5819 si_reset_to_default(rdev);
5820 si_dpm_stop_smc(rdev);
5821 si_force_switch_to_arb_f0(rdev);
5822
5823 ni_update_current_ps(rdev, boot_ps);
5824}
5825
5826int si_dpm_pre_set_power_state(struct radeon_device *rdev)
5827{
5828 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5829 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
5830 struct radeon_ps *new_ps = &requested_ps;
5831
5832 ni_update_requested_ps(rdev, new_ps);
5833
5834 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
5835
5836 return 0;
5837}
5838
5839int si_dpm_set_power_state(struct radeon_device *rdev)
5840{
5841 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5842 struct radeon_ps *new_ps = &eg_pi->requested_rps;
5843 struct radeon_ps *old_ps = &eg_pi->current_rps;
5844 int ret;
5845
5846 ret = si_disable_ulv(rdev);
5847 if (ret)
5848 return ret;
5849 ret = si_restrict_performance_levels_before_switch(rdev);
5850 if (ret)
5851 return ret;
5852 if (eg_pi->pcie_performance_request)
5853 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
5854 rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
5855 ret = si_enable_power_containment(rdev, new_ps, false);
5856 if (ret)
5857 return ret;
5858 ret = si_enable_smc_cac(rdev, new_ps, false);
5859 if (ret)
5860 return ret;
5861 ret = si_halt_smc(rdev);
5862 if (ret)
5863 return ret;
5864 ret = si_upload_sw_state(rdev, new_ps);
5865 if (ret)
5866 return ret;
5867 ret = si_upload_smc_data(rdev);
5868 if (ret)
5869 return ret;
5870 ret = si_upload_ulv_state(rdev);
5871 if (ret)
5872 return ret;
5873 if (eg_pi->dynamic_ac_timing) {
5874 ret = si_upload_mc_reg_table(rdev, new_ps);
5875 if (ret)
5876 return ret;
5877 }
5878 ret = si_program_memory_timing_parameters(rdev, new_ps);
5879 if (ret)
5880 return ret;
5881 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
5882
5883 ret = si_populate_smc_tdp_limits(rdev, new_ps);
5884 if (ret)
5885 return ret;
5886 ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
5887 if (ret)
5888 return ret;
5889
5890 ret = si_resume_smc(rdev);
5891 if (ret)
5892 return ret;
5893 ret = si_set_sw_state(rdev);
5894 if (ret)
5895 return ret;
5896 rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
5897 if (eg_pi->pcie_performance_request)
5898 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
5899 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
5900 if (ret)
5901 return ret;
5902 ret = si_enable_smc_cac(rdev, new_ps, true);
5903 if (ret)
5904 return ret;
5905 ret = si_enable_power_containment(rdev, new_ps, true);
5906 if (ret)
5907 return ret;
5908
5909#if 0
5910 /* XXX */
5911 ret = si_unrestrict_performance_levels_after_switch(rdev);
5912 if (ret)
5913 return ret;
5914#endif
5915
5916 return 0;
5917}
5918
5919
5920int si_power_control_set_level(struct radeon_device *rdev)
5921{
5922 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
5923 int ret;
5924
5925 ret = si_restrict_performance_levels_before_switch(rdev);
5926 if (ret)
5927 return ret;
5928 ret = si_halt_smc(rdev);
5929 if (ret)
5930 return ret;
5931 ret = si_populate_smc_tdp_limits(rdev, new_ps);
5932 if (ret)
5933 return ret;
5934 ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
5935 if (ret)
5936 return ret;
5937 ret = si_resume_smc(rdev);
5938 if (ret)
5939 return ret;
5940 ret = si_set_sw_state(rdev);
5941 if (ret)
5942 return ret;
5943 return 0;
5944}
5945
5946void si_dpm_post_set_power_state(struct radeon_device *rdev)
5947{
5948 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5949 struct radeon_ps *new_ps = &eg_pi->requested_rps;
5950
5951 ni_update_current_ps(rdev, new_ps);
5952}
5953
5954
5955void si_dpm_reset_asic(struct radeon_device *rdev)
5956{
5957 si_restrict_performance_levels_before_switch(rdev);
5958 si_disable_ulv(rdev);
5959 si_set_boot_state(rdev);
5960}
5961
5962void si_dpm_display_configuration_changed(struct radeon_device *rdev)
5963{
5964 si_program_display_gap(rdev);
5965}
5966
5967union power_info {
5968 struct _ATOM_POWERPLAY_INFO info;
5969 struct _ATOM_POWERPLAY_INFO_V2 info_2;
5970 struct _ATOM_POWERPLAY_INFO_V3 info_3;
5971 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
5972 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
5973 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
5974};
5975
5976union pplib_clock_info {
5977 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
5978 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
5979 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
5980 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
5981 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
5982};
5983
5984union pplib_power_state {
5985 struct _ATOM_PPLIB_STATE v1;
5986 struct _ATOM_PPLIB_STATE_V2 v2;
5987};
5988
5989static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
5990 struct radeon_ps *rps,
5991 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
5992 u8 table_rev)
5993{
5994 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
5995 rps->class = le16_to_cpu(non_clock_info->usClassification);
5996 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
5997
5998 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
5999 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6000 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6001 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6002 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6003 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6004 } else {
6005 rps->vclk = 0;
6006 rps->dclk = 0;
6007 }
6008
6009 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6010 rdev->pm.dpm.boot_ps = rps;
6011 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6012 rdev->pm.dpm.uvd_ps = rps;
6013}
6014
6015static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6016 struct radeon_ps *rps, int index,
6017 union pplib_clock_info *clock_info)
6018{
6019 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6020 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6021 struct si_power_info *si_pi = si_get_pi(rdev);
6022 struct ni_ps *ps = ni_get_ps(rps);
6023 u16 leakage_voltage;
6024 struct rv7xx_pl *pl = &ps->performance_levels[index];
6025 int ret;
6026
6027 ps->performance_level_count = index + 1;
6028
6029 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6030 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6031 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6032 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6033
6034 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6035 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6036 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6037 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6038 si_pi->sys_pcie_mask,
6039 si_pi->boot_pcie_gen,
6040 clock_info->si.ucPCIEGen);
6041
6042 /* patch up vddc if necessary */
6043 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6044 &leakage_voltage);
6045 if (ret == 0)
6046 pl->vddc = leakage_voltage;
6047
6048 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6049 pi->acpi_vddc = pl->vddc;
6050 eg_pi->acpi_vddci = pl->vddci;
6051 si_pi->acpi_pcie_gen = pl->pcie_gen;
6052 }
6053
6054 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6055 index == 0) {
6056 /* XXX disable for A0 tahiti */
6057 si_pi->ulv.supported = true;
6058 si_pi->ulv.pl = *pl;
6059 si_pi->ulv.one_pcie_lane_in_ulv = false;
6060 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6061 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6062 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6063 }
6064
6065 if (pi->min_vddc_in_table > pl->vddc)
6066 pi->min_vddc_in_table = pl->vddc;
6067
6068 if (pi->max_vddc_in_table < pl->vddc)
6069 pi->max_vddc_in_table = pl->vddc;
6070
6071 /* patch up boot state */
6072 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6073 u16 vddc, vddci, mvdd;
6074 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6075 pl->mclk = rdev->clock.default_mclk;
6076 pl->sclk = rdev->clock.default_sclk;
6077 pl->vddc = vddc;
6078 pl->vddci = vddci;
6079 si_pi->mvdd_bootup_value = mvdd;
6080 }
6081
6082 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6083 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6084 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6085 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6086 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6087 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6088 }
6089}
6090
6091static int si_parse_power_table(struct radeon_device *rdev)
6092{
6093 struct radeon_mode_info *mode_info = &rdev->mode_info;
6094 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6095 union pplib_power_state *power_state;
6096 int i, j, k, non_clock_array_index, clock_array_index;
6097 union pplib_clock_info *clock_info;
6098 struct _StateArray *state_array;
6099 struct _ClockInfoArray *clock_info_array;
6100 struct _NonClockInfoArray *non_clock_info_array;
6101 union power_info *power_info;
6102 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6103 u16 data_offset;
6104 u8 frev, crev;
6105 u8 *power_state_offset;
6106 struct ni_ps *ps;
6107
6108 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6109 &frev, &crev, &data_offset))
6110 return -EINVAL;
6111 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6112
6113 state_array = (struct _StateArray *)
6114 (mode_info->atom_context->bios + data_offset +
6115 le16_to_cpu(power_info->pplib.usStateArrayOffset));
6116 clock_info_array = (struct _ClockInfoArray *)
6117 (mode_info->atom_context->bios + data_offset +
6118 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6119 non_clock_info_array = (struct _NonClockInfoArray *)
6120 (mode_info->atom_context->bios + data_offset +
6121 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6122
6123 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6124 state_array->ucNumEntries, GFP_KERNEL);
6125 if (!rdev->pm.dpm.ps)
6126 return -ENOMEM;
6127 power_state_offset = (u8 *)state_array->states;
6128 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
6129 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
6130 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
6131 for (i = 0; i < state_array->ucNumEntries; i++) {
6132 power_state = (union pplib_power_state *)power_state_offset;
6133 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6134 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6135 &non_clock_info_array->nonClockInfo[non_clock_array_index];
6136 if (!rdev->pm.power_state[i].clock_info)
6137 return -EINVAL;
6138 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6139 if (ps == NULL) {
6140 kfree(rdev->pm.dpm.ps);
6141 return -ENOMEM;
6142 }
6143 rdev->pm.dpm.ps[i].ps_priv = ps;
6144 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6145 non_clock_info,
6146 non_clock_info_array->ucEntrySize);
6147 k = 0;
6148 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6149 clock_array_index = power_state->v2.clockInfoIndex[j];
6150 if (clock_array_index >= clock_info_array->ucNumEntries)
6151 continue;
6152 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6153 break;
6154 clock_info = (union pplib_clock_info *)
6155 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
6156 si_parse_pplib_clock_info(rdev,
6157 &rdev->pm.dpm.ps[i], k,
6158 clock_info);
6159 k++;
6160 }
6161 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6162 }
6163 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6164 return 0;
6165}
6166
6167int si_dpm_init(struct radeon_device *rdev)
6168{
6169 struct rv7xx_power_info *pi;
6170 struct evergreen_power_info *eg_pi;
6171 struct ni_power_info *ni_pi;
6172 struct si_power_info *si_pi;
6173 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
6174 u16 data_offset, size;
6175 u8 frev, crev;
6176 struct atom_clock_dividers dividers;
6177 int ret;
6178 u32 mask;
6179
6180 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6181 if (si_pi == NULL)
6182 return -ENOMEM;
6183 rdev->pm.dpm.priv = si_pi;
6184 ni_pi = &si_pi->ni;
6185 eg_pi = &ni_pi->eg;
6186 pi = &eg_pi->rv7xx;
6187
6188 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6189 if (ret)
6190 si_pi->sys_pcie_mask = 0;
6191 else
6192 si_pi->sys_pcie_mask = mask;
6193 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6194 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6195
6196 si_set_max_cu_value(rdev);
6197
6198 rv770_get_max_vddc(rdev);
6199 si_get_leakage_vddc(rdev);
6200 si_patch_dependency_tables_based_on_leakage(rdev);
6201
6202 pi->acpi_vddc = 0;
6203 eg_pi->acpi_vddci = 0;
6204 pi->min_vddc_in_table = 0;
6205 pi->max_vddc_in_table = 0;
6206
6207 ret = si_parse_power_table(rdev);
6208 if (ret)
6209 return ret;
6210 ret = r600_parse_extended_power_table(rdev);
6211 if (ret)
6212 return ret;
6213
6214 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6215 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6216 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6217 r600_free_extended_power_table(rdev);
6218 return -ENOMEM;
6219 }
6220 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6221 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6222 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6223 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6224 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6225 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6226 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6227 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6228 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6229
6230 if (rdev->pm.dpm.voltage_response_time == 0)
6231 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6232 if (rdev->pm.dpm.backbias_response_time == 0)
6233 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6234
6235 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6236 0, false, &dividers);
6237 if (ret)
6238 pi->ref_div = dividers.ref_div + 1;
6239 else
6240 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6241
6242 eg_pi->smu_uvd_hs = false;
6243
6244 pi->mclk_strobe_mode_threshold = 40000;
6245 if (si_is_special_1gb_platform(rdev))
6246 pi->mclk_stutter_mode_threshold = 0;
6247 else
6248 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6249 pi->mclk_edc_enable_threshold = 40000;
6250 eg_pi->mclk_edc_wr_enable_threshold = 40000;
6251
6252 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6253
6254 pi->voltage_control =
6255 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_GPIO_LUT);
6256
6257 pi->mvdd_control =
6258 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, VOLTAGE_OBJ_GPIO_LUT);
6259
6260 eg_pi->vddci_control =
6261 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, VOLTAGE_OBJ_GPIO_LUT);
6262
6263 si_pi->vddc_phase_shed_control =
6264 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT);
6265
6266 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
6267 &frev, &crev, &data_offset)) {
6268 pi->sclk_ss = true;
6269 pi->mclk_ss = true;
6270 pi->dynamic_ss = true;
6271 } else {
6272 pi->sclk_ss = false;
6273 pi->mclk_ss = false;
6274 pi->dynamic_ss = true;
6275 }
6276
6277 pi->asi = RV770_ASI_DFLT;
6278 pi->pasi = CYPRESS_HASI_DFLT;
6279 pi->vrc = SISLANDS_VRC_DFLT;
6280
6281 pi->gfx_clock_gating = true;
6282
6283 eg_pi->sclk_deep_sleep = true;
6284 si_pi->sclk_deep_sleep_above_low = false;
6285
6286 if (pi->gfx_clock_gating &&
6287 (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
6288 pi->thermal_protection = true;
6289 else
6290 pi->thermal_protection = false;
6291
6292 eg_pi->dynamic_ac_timing = true;
6293
6294 eg_pi->light_sleep = true;
6295#if defined(CONFIG_ACPI)
6296 eg_pi->pcie_performance_request =
6297 radeon_acpi_is_pcie_performance_request_supported(rdev);
6298#else
6299 eg_pi->pcie_performance_request = false;
6300#endif
6301
6302 si_pi->sram_end = SMC_RAM_END;
6303
6304 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
6305 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
6306 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
6307 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
6308 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
6309 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
6310 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
6311
6312 si_initialize_powertune_defaults(rdev);
6313
6314 return 0;
6315}
6316
6317void si_dpm_fini(struct radeon_device *rdev)
6318{
6319 int i;
6320
6321 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
6322 kfree(rdev->pm.dpm.ps[i].ps_priv);
6323 }
6324 kfree(rdev->pm.dpm.ps);
6325 kfree(rdev->pm.dpm.priv);
6326 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
6327 r600_free_extended_power_table(rdev);
6328}
6329
diff --git a/drivers/gpu/drm/radeon/si_dpm.h b/drivers/gpu/drm/radeon/si_dpm.h
new file mode 100644
index 000000000000..4ce5032cdf49
--- /dev/null
+++ b/drivers/gpu/drm/radeon/si_dpm.h
@@ -0,0 +1,227 @@
1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __SI_DPM_H__
24#define __SI_DPM_H__
25
26#include "ni_dpm.h"
27#include "sislands_smc.h"
28
29enum si_cac_config_reg_type
30{
31 SISLANDS_CACCONFIG_MMR = 0,
32 SISLANDS_CACCONFIG_CGIND,
33 SISLANDS_CACCONFIG_MAX
34};
35
36struct si_cac_config_reg
37{
38 u32 offset;
39 u32 mask;
40 u32 shift;
41 u32 value;
42 enum si_cac_config_reg_type type;
43};
44
45struct si_powertune_data
46{
47 u32 cac_window;
48 u32 l2_lta_window_size_default;
49 u8 lts_truncate_default;
50 u8 shift_n_default;
51 u8 operating_temp;
52 struct ni_leakage_coeffients leakage_coefficients;
53 u32 fixed_kt;
54 u32 lkge_lut_v0_percent;
55 u8 dc_cac[NISLANDS_DCCAC_MAX_LEVELS];
56 bool enable_powertune_by_default;
57};
58
59struct si_dyn_powertune_data
60{
61 u32 cac_leakage;
62 s32 leakage_minimum_temperature;
63 u32 wintime;
64 u32 l2_lta_window_size;
65 u8 lts_truncate;
66 u8 shift_n;
67 u8 dc_pwr_value;
68 bool disable_uvd_powertune;
69};
70
71struct si_dte_data
72{
73 u32 tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
74 u32 r[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
75 u32 k;
76 u32 t0;
77 u32 max_t;
78 u8 window_size;
79 u8 temp_select;
80 u8 dte_mode;
81 u8 tdep_count;
82 u8 t_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
83 u32 tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
84 u32 tdep_r[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
85 u32 t_threshold;
86 bool enable_dte_by_default;
87};
88
89struct si_clock_registers {
90 u32 cg_spll_func_cntl;
91 u32 cg_spll_func_cntl_2;
92 u32 cg_spll_func_cntl_3;
93 u32 cg_spll_func_cntl_4;
94 u32 cg_spll_spread_spectrum;
95 u32 cg_spll_spread_spectrum_2;
96 u32 dll_cntl;
97 u32 mclk_pwrmgt_cntl;
98 u32 mpll_ad_func_cntl;
99 u32 mpll_dq_func_cntl;
100 u32 mpll_func_cntl;
101 u32 mpll_func_cntl_1;
102 u32 mpll_func_cntl_2;
103 u32 mpll_ss1;
104 u32 mpll_ss2;
105};
106
107struct si_mc_reg_entry {
108 u32 mclk_max;
109 u32 mc_data[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
110};
111
112struct si_mc_reg_table {
113 u8 last;
114 u8 num_entries;
115 u16 valid_flag;
116 struct si_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
117 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
118};
119
120#define SISLANDS_MCREGISTERTABLE_INITIAL_SLOT 0
121#define SISLANDS_MCREGISTERTABLE_ACPI_SLOT 1
122#define SISLANDS_MCREGISTERTABLE_ULV_SLOT 2
123#define SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT 3
124
125struct si_leakage_voltage_entry
126{
127 u16 voltage;
128 u16 leakage_index;
129};
130
131#define SISLANDS_LEAKAGE_INDEX0 0xff01
132#define SISLANDS_MAX_LEAKAGE_COUNT 4
133
134struct si_leakage_voltage
135{
136 u16 count;
137 struct si_leakage_voltage_entry entries[SISLANDS_MAX_LEAKAGE_COUNT];
138};
139
140#define SISLANDS_MAX_HARDWARE_POWERLEVELS 5
141
142struct si_ulv_param {
143 bool supported;
144 u32 cg_ulv_control;
145 u32 cg_ulv_parameter;
146 u32 volt_change_delay;
147 struct rv7xx_pl pl;
148 bool one_pcie_lane_in_ulv;
149};
150
151struct si_power_info {
152 /* must be first! */
153 struct ni_power_info ni;
154 struct si_clock_registers clock_registers;
155 struct si_mc_reg_table mc_reg_table;
156 struct atom_voltage_table mvdd_voltage_table;
157 struct atom_voltage_table vddc_phase_shed_table;
158 struct si_leakage_voltage leakage_voltage;
159 u16 mvdd_bootup_value;
160 struct si_ulv_param ulv;
161 u32 max_cu;
162 /* pcie gen */
163 enum radeon_pcie_gen force_pcie_gen;
164 enum radeon_pcie_gen boot_pcie_gen;
165 enum radeon_pcie_gen acpi_pcie_gen;
166 u32 sys_pcie_mask;
167 /* flags */
168 bool enable_dte;
169 bool enable_ppm;
170 bool vddc_phase_shed_control;
171 bool pspp_notify_required;
172 bool sclk_deep_sleep_above_low;
173 /* smc offsets */
174 u32 sram_end;
175 u32 state_table_start;
176 u32 soft_regs_start;
177 u32 mc_reg_table_start;
178 u32 arb_table_start;
179 u32 cac_table_start;
180 u32 dte_table_start;
181 u32 spll_table_start;
182 u32 papm_cfg_table_start;
183 /* CAC stuff */
184 const struct si_cac_config_reg *cac_weights;
185 const struct si_cac_config_reg *lcac_config;
186 const struct si_cac_config_reg *cac_override;
187 const struct si_powertune_data *powertune_data;
188 struct si_dyn_powertune_data dyn_powertune_data;
189 /* DTE stuff */
190 struct si_dte_data dte_data;
191 /* scratch structs */
192 SMC_SIslands_MCRegisters smc_mc_reg_table;
193 SISLANDS_SMC_STATETABLE smc_statetable;
194 PP_SIslands_PAPMParameters papm_parm;
195};
196
197#define SISLANDS_INITIAL_STATE_ARB_INDEX 0
198#define SISLANDS_ACPI_STATE_ARB_INDEX 1
199#define SISLANDS_ULV_STATE_ARB_INDEX 2
200#define SISLANDS_DRIVER_STATE_ARB_INDEX 3
201
202#define SISLANDS_DPM2_MAX_PULSE_SKIP 256
203
204#define SISLANDS_DPM2_NEAR_TDP_DEC 10
205#define SISLANDS_DPM2_ABOVE_SAFE_INC 5
206#define SISLANDS_DPM2_BELOW_SAFE_INC 20
207
208#define SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT 80
209
210#define SISLANDS_DPM2_MAXPS_PERCENT_H 99
211#define SISLANDS_DPM2_MAXPS_PERCENT_M 99
212
213#define SISLANDS_DPM2_SQ_RAMP_MAX_POWER 0x3FFF
214#define SISLANDS_DPM2_SQ_RAMP_MIN_POWER 0x12
215#define SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15
216#define SISLANDS_DPM2_SQ_RAMP_STI_SIZE 0x1E
217#define SISLANDS_DPM2_SQ_RAMP_LTI_RATIO 0xF
218
219#define SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN 10
220
221#define SISLANDS_VRC_DFLT 0xC000B3
222#define SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT 1687
223#define SISLANDS_CGULVPARAMETER_DFLT 0x00040035
224#define SISLANDS_CGULVCONTROL_DFLT 0x1f007550
225
226
227#endif
diff --git a/drivers/gpu/drm/radeon/si_smc.c b/drivers/gpu/drm/radeon/si_smc.c
new file mode 100644
index 000000000000..5f524c0a541e
--- /dev/null
+++ b/drivers/gpu/drm/radeon/si_smc.c
@@ -0,0 +1,284 @@
1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25#include <linux/firmware.h>
26#include "drmP.h"
27#include "radeon.h"
28#include "sid.h"
29#include "ppsmc.h"
30#include "radeon_ucode.h"
31
32int si_set_smc_sram_address(struct radeon_device *rdev,
33 u32 smc_address, u32 limit)
34{
35 if (smc_address & 3)
36 return -EINVAL;
37 if ((smc_address + 3) > limit)
38 return -EINVAL;
39
40 WREG32(SMC_IND_INDEX_0, smc_address);
41 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
42
43 return 0;
44}
45
46int si_copy_bytes_to_smc(struct radeon_device *rdev,
47 u32 smc_start_address,
48 const u8 *src, u32 byte_count, u32 limit)
49{
50 int ret;
51 u32 data, original_data, addr, extra_shift;
52
53 if (smc_start_address & 3)
54 return -EINVAL;
55 if ((smc_start_address + byte_count) > limit)
56 return -EINVAL;
57
58 addr = smc_start_address;
59
60 while (byte_count >= 4) {
61 /* SMC address space is BE */
62 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
63
64 ret = si_set_smc_sram_address(rdev, addr, limit);
65 if (ret)
66 return ret;
67
68 WREG32(SMC_IND_DATA_0, data);
69
70 src += 4;
71 byte_count -= 4;
72 addr += 4;
73 }
74
75 /* RMW for the final bytes */
76 if (byte_count > 0) {
77 data = 0;
78
79 ret = si_set_smc_sram_address(rdev, addr, limit);
80 if (ret)
81 return ret;
82
83 original_data = RREG32(SMC_IND_DATA_0);
84
85 extra_shift = 8 * (4 - byte_count);
86
87 while (byte_count > 0) {
88 /* SMC address space is BE */
89 data = (data << 8) + *src++;
90 byte_count--;
91 }
92
93 data <<= extra_shift;
94
95 data |= (original_data & ~((~0UL) << extra_shift));
96
97 ret = si_set_smc_sram_address(rdev, addr, limit);
98 if (ret)
99 return ret;
100
101 WREG32(SMC_IND_DATA_0, data);
102 }
103 return 0;
104}
105
106void si_start_smc(struct radeon_device *rdev)
107{
108 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
109
110 tmp &= ~RST_REG;
111
112 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
113}
114
115void si_reset_smc(struct radeon_device *rdev)
116{
117 u32 tmp;
118
119 RREG32(CB_CGTT_SCLK_CTRL);
120 RREG32(CB_CGTT_SCLK_CTRL);
121 RREG32(CB_CGTT_SCLK_CTRL);
122 RREG32(CB_CGTT_SCLK_CTRL);
123
124 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
125 tmp |= RST_REG;
126 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
127}
128
129int si_program_jump_on_start(struct radeon_device *rdev)
130{
131 static u8 data[] = { 0x0E, 0x00, 0x40, 0x40 };
132
133 return si_copy_bytes_to_smc(rdev, 0x0, data, 4, sizeof(data)+1);
134}
135
136void si_stop_smc_clock(struct radeon_device *rdev)
137{
138 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
139
140 tmp |= CK_DISABLE;
141
142 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
143}
144
145void si_start_smc_clock(struct radeon_device *rdev)
146{
147 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
148
149 tmp &= ~CK_DISABLE;
150
151 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
152}
153
154bool si_is_smc_running(struct radeon_device *rdev)
155{
156 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
157 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
158
159 if (!(rst & RST_REG) && !(clk & CK_DISABLE))
160 return true;
161
162 return false;
163}
164
165PPSMC_Result si_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg)
166{
167 u32 tmp;
168 int i;
169
170 if (!si_is_smc_running(rdev))
171 return PPSMC_Result_Failed;
172
173 WREG32(SMC_MESSAGE_0, msg);
174
175 for (i = 0; i < rdev->usec_timeout; i++) {
176 tmp = RREG32(SMC_RESP_0);
177 if (tmp != 0)
178 break;
179 udelay(1);
180 }
181 tmp = RREG32(SMC_RESP_0);
182
183 return (PPSMC_Result)tmp;
184}
185
186PPSMC_Result si_wait_for_smc_inactive(struct radeon_device *rdev)
187{
188 u32 tmp;
189 int i;
190
191 if (!si_is_smc_running(rdev))
192 return PPSMC_Result_OK;
193
194 for (i = 0; i < rdev->usec_timeout; i++) {
195 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
196 if ((tmp & CKEN) == 0)
197 break;
198 udelay(1);
199 }
200
201 return PPSMC_Result_OK;
202}
203
204int si_load_smc_ucode(struct radeon_device *rdev, u32 limit)
205{
206 u32 ucode_start_address;
207 u32 ucode_size;
208 const u8 *src;
209 u32 data;
210
211 if (!rdev->smc_fw)
212 return -EINVAL;
213
214 switch (rdev->family) {
215 case CHIP_TAHITI:
216 ucode_start_address = TAHITI_SMC_UCODE_START;
217 ucode_size = TAHITI_SMC_UCODE_SIZE;
218 break;
219 case CHIP_PITCAIRN:
220 ucode_start_address = PITCAIRN_SMC_UCODE_START;
221 ucode_size = PITCAIRN_SMC_UCODE_SIZE;
222 break;
223 case CHIP_VERDE:
224 ucode_start_address = VERDE_SMC_UCODE_START;
225 ucode_size = VERDE_SMC_UCODE_SIZE;
226 break;
227 case CHIP_OLAND:
228 ucode_start_address = OLAND_SMC_UCODE_START;
229 ucode_size = OLAND_SMC_UCODE_SIZE;
230 break;
231 case CHIP_HAINAN:
232 ucode_start_address = HAINAN_SMC_UCODE_START;
233 ucode_size = HAINAN_SMC_UCODE_SIZE;
234 break;
235 default:
236 DRM_ERROR("unknown asic in smc ucode loader\n");
237 BUG();
238 }
239
240 if (ucode_size & 3)
241 return -EINVAL;
242
243 src = (const u8 *)rdev->smc_fw->data;
244 WREG32(SMC_IND_INDEX_0, ucode_start_address);
245 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
246 while (ucode_size >= 4) {
247 /* SMC address space is BE */
248 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
249
250 WREG32(SMC_IND_DATA_0, data);
251
252 src += 4;
253 ucode_size -= 4;
254 }
255 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
256
257 return 0;
258}
259
260int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
261 u32 *value, u32 limit)
262{
263 int ret;
264
265 ret = si_set_smc_sram_address(rdev, smc_address, limit);
266 if (ret)
267 return ret;
268
269 *value = RREG32(SMC_IND_DATA_0);
270 return 0;
271}
272
273int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
274 u32 value, u32 limit)
275{
276 int ret;
277
278 ret = si_set_smc_sram_address(rdev, smc_address, limit);
279 if (ret)
280 return ret;
281
282 WREG32(SMC_IND_DATA_0, value);
283 return 0;
284}
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 1390073c3960..299d657d0168 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -48,12 +48,76 @@
48#define SI_MAX_TCC 16 48#define SI_MAX_TCC 16
49#define SI_MAX_TCC_MASK 0xFFFF 49#define SI_MAX_TCC_MASK 0xFFFF
50 50
51/* SMC IND accessor regs */
52#define SMC_IND_INDEX_0 0x200
53#define SMC_IND_DATA_0 0x204
54
55#define SMC_IND_ACCESS_CNTL 0x228
56# define AUTO_INCREMENT_IND_0 (1 << 0)
57#define SMC_MESSAGE_0 0x22c
58#define SMC_RESP_0 0x230
59
51/* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */ 60/* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */
52#define SMC_CG_IND_START 0xc0030000 61#define SMC_CG_IND_START 0xc0030000
62#define SMC_CG_IND_END 0xc0040000
53 63
54#define CG_CGTT_LOCAL_0 0x400 64#define CG_CGTT_LOCAL_0 0x400
55#define CG_CGTT_LOCAL_1 0x401 65#define CG_CGTT_LOCAL_1 0x401
56 66
67/* SMC IND registers */
68#define SMC_SYSCON_RESET_CNTL 0x80000000
69# define RST_REG (1 << 0)
70#define SMC_SYSCON_CLOCK_CNTL_0 0x80000004
71# define CK_DISABLE (1 << 0)
72# define CKEN (1 << 24)
73
74#define VGA_HDP_CONTROL 0x328
75#define VGA_MEMORY_DISABLE (1 << 4)
76
77#define DCCG_DISP_SLOW_SELECT_REG 0x4fc
78#define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0)
79#define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0)
80#define DCCG_DISP1_SLOW_SELECT_SHIFT 0
81#define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4)
82#define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4)
83#define DCCG_DISP2_SLOW_SELECT_SHIFT 4
84
85#define CG_SPLL_FUNC_CNTL 0x600
86#define SPLL_RESET (1 << 0)
87#define SPLL_SLEEP (1 << 1)
88#define SPLL_BYPASS_EN (1 << 3)
89#define SPLL_REF_DIV(x) ((x) << 4)
90#define SPLL_REF_DIV_MASK (0x3f << 4)
91#define SPLL_PDIV_A(x) ((x) << 20)
92#define SPLL_PDIV_A_MASK (0x7f << 20)
93#define SPLL_PDIV_A_SHIFT 20
94#define CG_SPLL_FUNC_CNTL_2 0x604
95#define SCLK_MUX_SEL(x) ((x) << 0)
96#define SCLK_MUX_SEL_MASK (0x1ff << 0)
97#define CG_SPLL_FUNC_CNTL_3 0x608
98#define SPLL_FB_DIV(x) ((x) << 0)
99#define SPLL_FB_DIV_MASK (0x3ffffff << 0)
100#define SPLL_FB_DIV_SHIFT 0
101#define SPLL_DITHEN (1 << 28)
102#define CG_SPLL_FUNC_CNTL_4 0x60c
103
104#define SPLL_CNTL_MODE 0x618
105# define SPLL_REFCLK_SEL(x) ((x) << 8)
106# define SPLL_REFCLK_SEL_MASK 0xFF00
107
108#define CG_SPLL_SPREAD_SPECTRUM 0x620
109#define SSEN (1 << 0)
110#define CLK_S(x) ((x) << 4)
111#define CLK_S_MASK (0xfff << 4)
112#define CLK_S_SHIFT 4
113#define CG_SPLL_SPREAD_SPECTRUM_2 0x624
114#define CLK_V(x) ((x) << 0)
115#define CLK_V_MASK (0x3ffffff << 0)
116#define CLK_V_SHIFT 0
117
118#define CG_SPLL_AUTOSCALE_CNTL 0x62c
119# define AUTOSCALE_ON_SS_CLEAR (1 << 9)
120
57/* discrete uvd clocks */ 121/* discrete uvd clocks */
58#define CG_UPLL_FUNC_CNTL 0x634 122#define CG_UPLL_FUNC_CNTL 0x634
59# define UPLL_RESET_MASK 0x00000001 123# define UPLL_RESET_MASK 0x00000001
@@ -83,21 +147,6 @@
83#define CG_UPLL_SPREAD_SPECTRUM 0x650 147#define CG_UPLL_SPREAD_SPECTRUM 0x650
84# define SSEN_MASK 0x00000001 148# define SSEN_MASK 0x00000001
85 149
86#define CG_MULT_THERMAL_STATUS 0x714
87#define ASIC_MAX_TEMP(x) ((x) << 0)
88#define ASIC_MAX_TEMP_MASK 0x000001ff
89#define ASIC_MAX_TEMP_SHIFT 0
90#define CTF_TEMP(x) ((x) << 9)
91#define CTF_TEMP_MASK 0x0003fe00
92#define CTF_TEMP_SHIFT 9
93
94#define VGA_HDP_CONTROL 0x328
95#define VGA_MEMORY_DISABLE (1 << 4)
96
97#define SPLL_CNTL_MODE 0x618
98# define SPLL_REFCLK_SEL(x) ((x) << 8)
99# define SPLL_REFCLK_SEL_MASK 0xFF00
100
101#define MPLL_BYPASSCLK_SEL 0x65c 150#define MPLL_BYPASSCLK_SEL 0x65c
102# define MPLL_CLKOUT_SEL(x) ((x) << 8) 151# define MPLL_CLKOUT_SEL(x) ((x) << 8)
103# define MPLL_CLKOUT_SEL_MASK 0xFF00 152# define MPLL_CLKOUT_SEL_MASK 0xFF00
@@ -120,6 +169,111 @@
120# define ZCLK_SEL(x) ((x) << 8) 169# define ZCLK_SEL(x) ((x) << 8)
121# define ZCLK_SEL_MASK 0xFF00 170# define ZCLK_SEL_MASK 0xFF00
122 171
172#define CG_THERMAL_CTRL 0x700
173#define DPM_EVENT_SRC(x) ((x) << 0)
174#define DPM_EVENT_SRC_MASK (7 << 0)
175#define DIG_THERM_DPM(x) ((x) << 14)
176#define DIG_THERM_DPM_MASK 0x003FC000
177#define DIG_THERM_DPM_SHIFT 14
178
179#define CG_THERMAL_INT 0x708
180#define DIG_THERM_INTH(x) ((x) << 8)
181#define DIG_THERM_INTH_MASK 0x0000FF00
182#define DIG_THERM_INTH_SHIFT 8
183#define DIG_THERM_INTL(x) ((x) << 16)
184#define DIG_THERM_INTL_MASK 0x00FF0000
185#define DIG_THERM_INTL_SHIFT 16
186#define THERM_INT_MASK_HIGH (1 << 24)
187#define THERM_INT_MASK_LOW (1 << 25)
188
189#define CG_MULT_THERMAL_STATUS 0x714
190#define ASIC_MAX_TEMP(x) ((x) << 0)
191#define ASIC_MAX_TEMP_MASK 0x000001ff
192#define ASIC_MAX_TEMP_SHIFT 0
193#define CTF_TEMP(x) ((x) << 9)
194#define CTF_TEMP_MASK 0x0003fe00
195#define CTF_TEMP_SHIFT 9
196
197#define GENERAL_PWRMGT 0x780
198# define GLOBAL_PWRMGT_EN (1 << 0)
199# define STATIC_PM_EN (1 << 1)
200# define THERMAL_PROTECTION_DIS (1 << 2)
201# define THERMAL_PROTECTION_TYPE (1 << 3)
202# define SW_SMIO_INDEX(x) ((x) << 6)
203# define SW_SMIO_INDEX_MASK (1 << 6)
204# define SW_SMIO_INDEX_SHIFT 6
205# define VOLT_PWRMGT_EN (1 << 10)
206# define DYN_SPREAD_SPECTRUM_EN (1 << 23)
207#define CG_TPC 0x784
208#define SCLK_PWRMGT_CNTL 0x788
209# define SCLK_PWRMGT_OFF (1 << 0)
210# define SCLK_LOW_D1 (1 << 1)
211# define FIR_RESET (1 << 4)
212# define FIR_FORCE_TREND_SEL (1 << 5)
213# define FIR_TREND_MODE (1 << 6)
214# define DYN_GFX_CLK_OFF_EN (1 << 7)
215# define GFX_CLK_FORCE_ON (1 << 8)
216# define GFX_CLK_REQUEST_OFF (1 << 9)
217# define GFX_CLK_FORCE_OFF (1 << 10)
218# define GFX_CLK_OFF_ACPI_D1 (1 << 11)
219# define GFX_CLK_OFF_ACPI_D2 (1 << 12)
220# define GFX_CLK_OFF_ACPI_D3 (1 << 13)
221# define DYN_LIGHT_SLEEP_EN (1 << 14)
222
223#define CG_FTV 0x7bc
224
225#define CG_FFCT_0 0x7c0
226# define UTC_0(x) ((x) << 0)
227# define UTC_0_MASK (0x3ff << 0)
228# define DTC_0(x) ((x) << 10)
229# define DTC_0_MASK (0x3ff << 10)
230
231#define CG_BSP 0x7fc
232# define BSP(x) ((x) << 0)
233# define BSP_MASK (0xffff << 0)
234# define BSU(x) ((x) << 16)
235# define BSU_MASK (0xf << 16)
236#define CG_AT 0x800
237# define CG_R(x) ((x) << 0)
238# define CG_R_MASK (0xffff << 0)
239# define CG_L(x) ((x) << 16)
240# define CG_L_MASK (0xffff << 16)
241
242#define CG_GIT 0x804
243# define CG_GICST(x) ((x) << 0)
244# define CG_GICST_MASK (0xffff << 0)
245# define CG_GIPOT(x) ((x) << 16)
246# define CG_GIPOT_MASK (0xffff << 16)
247
248#define CG_SSP 0x80c
249# define SST(x) ((x) << 0)
250# define SST_MASK (0xffff << 0)
251# define SSTU(x) ((x) << 16)
252# define SSTU_MASK (0xf << 16)
253
254#define CG_DISPLAY_GAP_CNTL 0x828
255# define DISP1_GAP(x) ((x) << 0)
256# define DISP1_GAP_MASK (3 << 0)
257# define DISP2_GAP(x) ((x) << 2)
258# define DISP2_GAP_MASK (3 << 2)
259# define VBI_TIMER_COUNT(x) ((x) << 4)
260# define VBI_TIMER_COUNT_MASK (0x3fff << 4)
261# define VBI_TIMER_UNIT(x) ((x) << 20)
262# define VBI_TIMER_UNIT_MASK (7 << 20)
263# define DISP1_GAP_MCHG(x) ((x) << 24)
264# define DISP1_GAP_MCHG_MASK (3 << 24)
265# define DISP2_GAP_MCHG(x) ((x) << 26)
266# define DISP2_GAP_MCHG_MASK (3 << 26)
267
268#define CG_ULV_CONTROL 0x878
269#define CG_ULV_PARAMETER 0x87c
270
271#define SMC_SCRATCH0 0x884
272
273#define CG_CAC_CTRL 0x8b8
274# define CAC_WINDOW(x) ((x) << 0)
275# define CAC_WINDOW_MASK 0x00ffffff
276
123#define DMIF_ADDR_CONFIG 0xBD4 277#define DMIF_ADDR_CONFIG 0xBD4
124 278
125#define DMIF_ADDR_CALC 0xC00 279#define DMIF_ADDR_CALC 0xC00
@@ -285,6 +439,23 @@
285#define NOOFGROUPS_SHIFT 12 439#define NOOFGROUPS_SHIFT 12
286#define NOOFGROUPS_MASK 0x00001000 440#define NOOFGROUPS_MASK 0x00001000
287 441
442#define MC_ARB_DRAM_TIMING 0x2774
443#define MC_ARB_DRAM_TIMING2 0x2778
444
445#define MC_ARB_BURST_TIME 0x2808
446#define STATE0(x) ((x) << 0)
447#define STATE0_MASK (0x1f << 0)
448#define STATE0_SHIFT 0
449#define STATE1(x) ((x) << 5)
450#define STATE1_MASK (0x1f << 5)
451#define STATE1_SHIFT 5
452#define STATE2(x) ((x) << 10)
453#define STATE2_MASK (0x1f << 10)
454#define STATE2_SHIFT 10
455#define STATE3(x) ((x) << 15)
456#define STATE3_MASK (0x1f << 15)
457#define STATE3_SHIFT 15
458
288#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808 459#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808
289#define TRAIN_DONE_D0 (1 << 30) 460#define TRAIN_DONE_D0 (1 << 30)
290#define TRAIN_DONE_D1 (1 << 31) 461#define TRAIN_DONE_D1 (1 << 31)
@@ -292,15 +463,105 @@
292#define MC_SEQ_SUP_CNTL 0x28c8 463#define MC_SEQ_SUP_CNTL 0x28c8
293#define RUN_MASK (1 << 0) 464#define RUN_MASK (1 << 0)
294#define MC_SEQ_SUP_PGM 0x28cc 465#define MC_SEQ_SUP_PGM 0x28cc
466#define MC_PMG_AUTO_CMD 0x28d0
295 467
296#define MC_IO_PAD_CNTL_D0 0x29d0 468#define MC_IO_PAD_CNTL_D0 0x29d0
297#define MEM_FALL_OUT_CMD (1 << 8) 469#define MEM_FALL_OUT_CMD (1 << 8)
298 470
471#define MC_SEQ_RAS_TIMING 0x28a0
472#define MC_SEQ_CAS_TIMING 0x28a4
473#define MC_SEQ_MISC_TIMING 0x28a8
474#define MC_SEQ_MISC_TIMING2 0x28ac
475#define MC_SEQ_PMG_TIMING 0x28b0
476#define MC_SEQ_RD_CTL_D0 0x28b4
477#define MC_SEQ_RD_CTL_D1 0x28b8
478#define MC_SEQ_WR_CTL_D0 0x28bc
479#define MC_SEQ_WR_CTL_D1 0x28c0
480
299#define MC_SEQ_MISC0 0x2a00 481#define MC_SEQ_MISC0 0x2a00
482#define MC_SEQ_MISC0_VEN_ID_SHIFT 8
483#define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00
484#define MC_SEQ_MISC0_VEN_ID_VALUE 3
485#define MC_SEQ_MISC0_REV_ID_SHIFT 12
486#define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000
487#define MC_SEQ_MISC0_REV_ID_VALUE 1
488#define MC_SEQ_MISC0_GDDR5_SHIFT 28
489#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
490#define MC_SEQ_MISC0_GDDR5_VALUE 5
491#define MC_SEQ_MISC1 0x2a04
492#define MC_SEQ_RESERVE_M 0x2a08
493#define MC_PMG_CMD_EMRS 0x2a0c
300 494
301#define MC_SEQ_IO_DEBUG_INDEX 0x2a44 495#define MC_SEQ_IO_DEBUG_INDEX 0x2a44
302#define MC_SEQ_IO_DEBUG_DATA 0x2a48 496#define MC_SEQ_IO_DEBUG_DATA 0x2a48
303 497
498#define MC_SEQ_MISC5 0x2a54
499#define MC_SEQ_MISC6 0x2a58
500
501#define MC_SEQ_MISC7 0x2a64
502
503#define MC_SEQ_RAS_TIMING_LP 0x2a6c
504#define MC_SEQ_CAS_TIMING_LP 0x2a70
505#define MC_SEQ_MISC_TIMING_LP 0x2a74
506#define MC_SEQ_MISC_TIMING2_LP 0x2a78
507#define MC_SEQ_WR_CTL_D0_LP 0x2a7c
508#define MC_SEQ_WR_CTL_D1_LP 0x2a80
509#define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
510#define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
511
512#define MC_PMG_CMD_MRS 0x2aac
513
514#define MC_SEQ_RD_CTL_D0_LP 0x2b1c
515#define MC_SEQ_RD_CTL_D1_LP 0x2b20
516
517#define MC_PMG_CMD_MRS1 0x2b44
518#define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
519#define MC_SEQ_PMG_TIMING_LP 0x2b4c
520
521#define MC_SEQ_WR_CTL_2 0x2b54
522#define MC_SEQ_WR_CTL_2_LP 0x2b58
523#define MC_PMG_CMD_MRS2 0x2b5c
524#define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60
525
526#define MCLK_PWRMGT_CNTL 0x2ba0
527# define DLL_SPEED(x) ((x) << 0)
528# define DLL_SPEED_MASK (0x1f << 0)
529# define DLL_READY (1 << 6)
530# define MC_INT_CNTL (1 << 7)
531# define MRDCK0_PDNB (1 << 8)
532# define MRDCK1_PDNB (1 << 9)
533# define MRDCK0_RESET (1 << 16)
534# define MRDCK1_RESET (1 << 17)
535# define DLL_READY_READ (1 << 24)
536#define DLL_CNTL 0x2ba4
537# define MRDCK0_BYPASS (1 << 24)
538# define MRDCK1_BYPASS (1 << 25)
539
540#define MPLL_FUNC_CNTL 0x2bb4
541#define BWCTRL(x) ((x) << 20)
542#define BWCTRL_MASK (0xff << 20)
543#define MPLL_FUNC_CNTL_1 0x2bb8
544#define VCO_MODE(x) ((x) << 0)
545#define VCO_MODE_MASK (3 << 0)
546#define CLKFRAC(x) ((x) << 4)
547#define CLKFRAC_MASK (0xfff << 4)
548#define CLKF(x) ((x) << 16)
549#define CLKF_MASK (0xfff << 16)
550#define MPLL_FUNC_CNTL_2 0x2bbc
551#define MPLL_AD_FUNC_CNTL 0x2bc0
552#define YCLK_POST_DIV(x) ((x) << 0)
553#define YCLK_POST_DIV_MASK (7 << 0)
554#define MPLL_DQ_FUNC_CNTL 0x2bc4
555#define YCLK_SEL(x) ((x) << 4)
556#define YCLK_SEL_MASK (1 << 4)
557
558#define MPLL_SS1 0x2bcc
559#define CLKV(x) ((x) << 0)
560#define CLKV_MASK (0x3ffffff << 0)
561#define MPLL_SS2 0x2bd0
562#define CLKS(x) ((x) << 0)
563#define CLKS_MASK (0xfff << 0)
564
304#define HDP_HOST_PATH_CNTL 0x2C00 565#define HDP_HOST_PATH_CNTL 0x2C00
305#define HDP_NONSURFACE_BASE 0x2C04 566#define HDP_NONSURFACE_BASE 0x2C04
306#define HDP_NONSURFACE_INFO 0x2C08 567#define HDP_NONSURFACE_INFO 0x2C08
@@ -470,6 +731,9 @@
470# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 731# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
471# define DC_HPDx_EN (1 << 28) 732# define DC_HPDx_EN (1 << 28)
472 733
734#define DPG_PIPE_STUTTER_CONTROL 0x6cd4
735# define STUTTER_ENABLE (1 << 0)
736
473/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 737/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
474#define CRTC_STATUS_FRAME_COUNT 0x6e98 738#define CRTC_STATUS_FRAME_COUNT 0x6e98
475 739
@@ -645,6 +909,24 @@
645 909
646#define SQC_CACHES 0x8C08 910#define SQC_CACHES 0x8C08
647 911
912#define SQ_POWER_THROTTLE 0x8e58
913#define MIN_POWER(x) ((x) << 0)
914#define MIN_POWER_MASK (0x3fff << 0)
915#define MIN_POWER_SHIFT 0
916#define MAX_POWER(x) ((x) << 16)
917#define MAX_POWER_MASK (0x3fff << 16)
918#define MAX_POWER_SHIFT 0
919#define SQ_POWER_THROTTLE2 0x8e5c
920#define MAX_POWER_DELTA(x) ((x) << 0)
921#define MAX_POWER_DELTA_MASK (0x3fff << 0)
922#define MAX_POWER_DELTA_SHIFT 0
923#define STI_SIZE(x) ((x) << 16)
924#define STI_SIZE_MASK (0x3ff << 16)
925#define STI_SIZE_SHIFT 16
926#define LTI_RATIO(x) ((x) << 27)
927#define LTI_RATIO_MASK (0xf << 27)
928#define LTI_RATIO_SHIFT 27
929
648#define SX_DEBUG_1 0x9060 930#define SX_DEBUG_1 0x9060
649 931
650#define SPI_STATIC_THREAD_MGMT_1 0x90E0 932#define SPI_STATIC_THREAD_MGMT_1 0x90E0
diff --git a/drivers/gpu/drm/radeon/sislands_smc.h b/drivers/gpu/drm/radeon/sislands_smc.h
new file mode 100644
index 000000000000..5578e9837026
--- /dev/null
+++ b/drivers/gpu/drm/radeon/sislands_smc.h
@@ -0,0 +1,397 @@
1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef PP_SISLANDS_SMC_H
24#define PP_SISLANDS_SMC_H
25
26#include "ppsmc.h"
27
28#pragma pack(push, 1)
29
30#define SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16
31
32struct PP_SIslands_Dpm2PerfLevel
33{
34 uint8_t MaxPS;
35 uint8_t TgtAct;
36 uint8_t MaxPS_StepInc;
37 uint8_t MaxPS_StepDec;
38 uint8_t PSSamplingTime;
39 uint8_t NearTDPDec;
40 uint8_t AboveSafeInc;
41 uint8_t BelowSafeInc;
42 uint8_t PSDeltaLimit;
43 uint8_t PSDeltaWin;
44 uint16_t PwrEfficiencyRatio;
45 uint8_t Reserved[4];
46};
47
48typedef struct PP_SIslands_Dpm2PerfLevel PP_SIslands_Dpm2PerfLevel;
49
50struct PP_SIslands_DPM2Status
51{
52 uint32_t dpm2Flags;
53 uint8_t CurrPSkip;
54 uint8_t CurrPSkipPowerShift;
55 uint8_t CurrPSkipTDP;
56 uint8_t CurrPSkipOCP;
57 uint8_t MaxSPLLIndex;
58 uint8_t MinSPLLIndex;
59 uint8_t CurrSPLLIndex;
60 uint8_t InfSweepMode;
61 uint8_t InfSweepDir;
62 uint8_t TDPexceeded;
63 uint8_t reserved;
64 uint8_t SwitchDownThreshold;
65 uint32_t SwitchDownCounter;
66 uint32_t SysScalingFactor;
67};
68
69typedef struct PP_SIslands_DPM2Status PP_SIslands_DPM2Status;
70
71struct PP_SIslands_DPM2Parameters
72{
73 uint32_t TDPLimit;
74 uint32_t NearTDPLimit;
75 uint32_t SafePowerLimit;
76 uint32_t PowerBoostLimit;
77 uint32_t MinLimitDelta;
78};
79typedef struct PP_SIslands_DPM2Parameters PP_SIslands_DPM2Parameters;
80
81struct PP_SIslands_PAPMStatus
82{
83 uint32_t EstimatedDGPU_T;
84 uint32_t EstimatedDGPU_P;
85 uint32_t EstimatedAPU_T;
86 uint32_t EstimatedAPU_P;
87 uint8_t dGPU_T_Limit_Exceeded;
88 uint8_t reserved[3];
89};
90typedef struct PP_SIslands_PAPMStatus PP_SIslands_PAPMStatus;
91
92struct PP_SIslands_PAPMParameters
93{
94 uint32_t NearTDPLimitTherm;
95 uint32_t NearTDPLimitPAPM;
96 uint32_t PlatformPowerLimit;
97 uint32_t dGPU_T_Limit;
98 uint32_t dGPU_T_Warning;
99 uint32_t dGPU_T_Hysteresis;
100};
101typedef struct PP_SIslands_PAPMParameters PP_SIslands_PAPMParameters;
102
103struct SISLANDS_SMC_SCLK_VALUE
104{
105 uint32_t vCG_SPLL_FUNC_CNTL;
106 uint32_t vCG_SPLL_FUNC_CNTL_2;
107 uint32_t vCG_SPLL_FUNC_CNTL_3;
108 uint32_t vCG_SPLL_FUNC_CNTL_4;
109 uint32_t vCG_SPLL_SPREAD_SPECTRUM;
110 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;
111 uint32_t sclk_value;
112};
113
114typedef struct SISLANDS_SMC_SCLK_VALUE SISLANDS_SMC_SCLK_VALUE;
115
116struct SISLANDS_SMC_MCLK_VALUE
117{
118 uint32_t vMPLL_FUNC_CNTL;
119 uint32_t vMPLL_FUNC_CNTL_1;
120 uint32_t vMPLL_FUNC_CNTL_2;
121 uint32_t vMPLL_AD_FUNC_CNTL;
122 uint32_t vMPLL_DQ_FUNC_CNTL;
123 uint32_t vMCLK_PWRMGT_CNTL;
124 uint32_t vDLL_CNTL;
125 uint32_t vMPLL_SS;
126 uint32_t vMPLL_SS2;
127 uint32_t mclk_value;
128};
129
130typedef struct SISLANDS_SMC_MCLK_VALUE SISLANDS_SMC_MCLK_VALUE;
131
132struct SISLANDS_SMC_VOLTAGE_VALUE
133{
134 uint16_t value;
135 uint8_t index;
136 uint8_t phase_settings;
137};
138
139typedef struct SISLANDS_SMC_VOLTAGE_VALUE SISLANDS_SMC_VOLTAGE_VALUE;
140
141struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL
142{
143 uint8_t ACIndex;
144 uint8_t displayWatermark;
145 uint8_t gen2PCIE;
146 uint8_t UVDWatermark;
147 uint8_t VCEWatermark;
148 uint8_t strobeMode;
149 uint8_t mcFlags;
150 uint8_t padding;
151 uint32_t aT;
152 uint32_t bSP;
153 SISLANDS_SMC_SCLK_VALUE sclk;
154 SISLANDS_SMC_MCLK_VALUE mclk;
155 SISLANDS_SMC_VOLTAGE_VALUE vddc;
156 SISLANDS_SMC_VOLTAGE_VALUE mvdd;
157 SISLANDS_SMC_VOLTAGE_VALUE vddci;
158 SISLANDS_SMC_VOLTAGE_VALUE std_vddc;
159 uint8_t hysteresisUp;
160 uint8_t hysteresisDown;
161 uint8_t stateFlags;
162 uint8_t arbRefreshState;
163 uint32_t SQPowerThrottle;
164 uint32_t SQPowerThrottle_2;
165 uint32_t MaxPoweredUpCU;
166 SISLANDS_SMC_VOLTAGE_VALUE high_temp_vddc;
167 SISLANDS_SMC_VOLTAGE_VALUE low_temp_vddc;
168 uint32_t reserved[2];
169 PP_SIslands_Dpm2PerfLevel dpm2;
170};
171
172#define SISLANDS_SMC_STROBE_RATIO 0x0F
173#define SISLANDS_SMC_STROBE_ENABLE 0x10
174
175#define SISLANDS_SMC_MC_EDC_RD_FLAG 0x01
176#define SISLANDS_SMC_MC_EDC_WR_FLAG 0x02
177#define SISLANDS_SMC_MC_RTT_ENABLE 0x04
178#define SISLANDS_SMC_MC_STUTTER_EN 0x08
179#define SISLANDS_SMC_MC_PG_EN 0x10
180
181typedef struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL SISLANDS_SMC_HW_PERFORMANCE_LEVEL;
182
183struct SISLANDS_SMC_SWSTATE
184{
185 uint8_t flags;
186 uint8_t levelCount;
187 uint8_t padding2;
188 uint8_t padding3;
189 SISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[1];
190};
191
192typedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE;
193
194#define SISLANDS_SMC_VOLTAGEMASK_VDDC 0
195#define SISLANDS_SMC_VOLTAGEMASK_MVDD 1
196#define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2
197#define SISLANDS_SMC_VOLTAGEMASK_MAX 4
198
199struct SISLANDS_SMC_VOLTAGEMASKTABLE
200{
201 uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX];
202};
203
204typedef struct SISLANDS_SMC_VOLTAGEMASKTABLE SISLANDS_SMC_VOLTAGEMASKTABLE;
205
206#define SISLANDS_MAX_NO_VREG_STEPS 32
207
208struct SISLANDS_SMC_STATETABLE
209{
210 uint8_t thermalProtectType;
211 uint8_t systemFlags;
212 uint8_t maxVDDCIndexInPPTable;
213 uint8_t extraFlags;
214 uint32_t lowSMIO[SISLANDS_MAX_NO_VREG_STEPS];
215 SISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable;
216 SISLANDS_SMC_VOLTAGEMASKTABLE phaseMaskTable;
217 PP_SIslands_DPM2Parameters dpm2Params;
218 SISLANDS_SMC_SWSTATE initialState;
219 SISLANDS_SMC_SWSTATE ACPIState;
220 SISLANDS_SMC_SWSTATE ULVState;
221 SISLANDS_SMC_SWSTATE driverState;
222 SISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1];
223};
224
225typedef struct SISLANDS_SMC_STATETABLE SISLANDS_SMC_STATETABLE;
226
227#define SI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0
228#define SI_SMC_SOFT_REGISTER_delay_vreg 0xC
229#define SI_SMC_SOFT_REGISTER_delay_acpi 0x28
230#define SI_SMC_SOFT_REGISTER_seq_index 0x5C
231#define SI_SMC_SOFT_REGISTER_mvdd_chg_time 0x60
232#define SI_SMC_SOFT_REGISTER_mclk_switch_lim 0x70
233#define SI_SMC_SOFT_REGISTER_watermark_threshold 0x78
234#define SI_SMC_SOFT_REGISTER_phase_shedding_delay 0x88
235#define SI_SMC_SOFT_REGISTER_ulv_volt_change_delay 0x8C
236#define SI_SMC_SOFT_REGISTER_mc_block_delay 0x98
237#define SI_SMC_SOFT_REGISTER_ticks_per_us 0xA8
238#define SI_SMC_SOFT_REGISTER_crtc_index 0xC4
239#define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min 0xC8
240#define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max 0xCC
241#define SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width 0xF4
242#define SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen 0xFC
243#define SI_SMC_SOFT_REGISTER_vr_hot_gpio 0x100
244
245#define SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
246#define SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 32
247
248#define SMC_SISLANDS_SCALE_I 7
249#define SMC_SISLANDS_SCALE_R 12
250
251struct PP_SIslands_CacConfig
252{
253 uint16_t cac_lkge_lut[SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES];
254 uint32_t lkge_lut_V0;
255 uint32_t lkge_lut_Vstep;
256 uint32_t WinTime;
257 uint32_t R_LL;
258 uint32_t calculation_repeats;
259 uint32_t l2numWin_TDP;
260 uint32_t dc_cac;
261 uint8_t lts_truncate_n;
262 uint8_t SHIFT_N;
263 uint8_t log2_PG_LKG_SCALE;
264 uint8_t cac_temp;
265 uint32_t lkge_lut_T0;
266 uint32_t lkge_lut_Tstep;
267};
268
269typedef struct PP_SIslands_CacConfig PP_SIslands_CacConfig;
270
271#define SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE 16
272#define SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20
273
274struct SMC_SIslands_MCRegisterAddress
275{
276 uint16_t s0;
277 uint16_t s1;
278};
279
280typedef struct SMC_SIslands_MCRegisterAddress SMC_SIslands_MCRegisterAddress;
281
282struct SMC_SIslands_MCRegisterSet
283{
284 uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
285};
286
287typedef struct SMC_SIslands_MCRegisterSet SMC_SIslands_MCRegisterSet;
288
289struct SMC_SIslands_MCRegisters
290{
291 uint8_t last;
292 uint8_t reserved[3];
293 SMC_SIslands_MCRegisterAddress address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
294 SMC_SIslands_MCRegisterSet data[SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT];
295};
296
297typedef struct SMC_SIslands_MCRegisters SMC_SIslands_MCRegisters;
298
299struct SMC_SIslands_MCArbDramTimingRegisterSet
300{
301 uint32_t mc_arb_dram_timing;
302 uint32_t mc_arb_dram_timing2;
303 uint8_t mc_arb_rfsh_rate;
304 uint8_t mc_arb_burst_time;
305 uint8_t padding[2];
306};
307
308typedef struct SMC_SIslands_MCArbDramTimingRegisterSet SMC_SIslands_MCArbDramTimingRegisterSet;
309
310struct SMC_SIslands_MCArbDramTimingRegisters
311{
312 uint8_t arb_current;
313 uint8_t reserved[3];
314 SMC_SIslands_MCArbDramTimingRegisterSet data[16];
315};
316
317typedef struct SMC_SIslands_MCArbDramTimingRegisters SMC_SIslands_MCArbDramTimingRegisters;
318
319struct SMC_SISLANDS_SPLL_DIV_TABLE
320{
321 uint32_t freq[256];
322 uint32_t ss[256];
323};
324
325#define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK 0x01ffffff
326#define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0
327#define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK 0xfe000000
328#define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT 25
329#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK 0x000fffff
330#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT 0
331#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK 0xfff00000
332#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT 20
333
334typedef struct SMC_SISLANDS_SPLL_DIV_TABLE SMC_SISLANDS_SPLL_DIV_TABLE;
335
336#define SMC_SISLANDS_DTE_MAX_FILTER_STAGES 5
337
338#define SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE 16
339
340struct Smc_SIslands_DTE_Configuration
341{
342 uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
343 uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
344 uint32_t K;
345 uint32_t T0;
346 uint32_t MaxT;
347 uint8_t WindowSize;
348 uint8_t Tdep_count;
349 uint8_t temp_select;
350 uint8_t DTE_mode;
351 uint8_t T_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
352 uint32_t Tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
353 uint32_t Tdep_R[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
354 uint32_t Tthreshold;
355};
356
357typedef struct Smc_SIslands_DTE_Configuration Smc_SIslands_DTE_Configuration;
358
359#define SMC_SISLANDS_DTE_STATUS_FLAG_DTE_ON 1
360
361#define SISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x10000
362
363#define SISLANDS_SMC_FIRMWARE_HEADER_version 0x0
364#define SISLANDS_SMC_FIRMWARE_HEADER_flags 0x4
365#define SISLANDS_SMC_FIRMWARE_HEADER_softRegisters 0xC
366#define SISLANDS_SMC_FIRMWARE_HEADER_stateTable 0x10
367#define SISLANDS_SMC_FIRMWARE_HEADER_fanTable 0x14
368#define SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable 0x18
369#define SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable 0x24
370#define SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x30
371#define SISLANDS_SMC_FIRMWARE_HEADER_spllTable 0x38
372#define SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration 0x40
373#define SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters 0x48
374
375#pragma pack(pop)
376
377int si_set_smc_sram_address(struct radeon_device *rdev,
378 u32 smc_address, u32 limit);
379int si_copy_bytes_to_smc(struct radeon_device *rdev,
380 u32 smc_start_address,
381 const u8 *src, u32 byte_count, u32 limit);
382void si_start_smc(struct radeon_device *rdev);
383void si_reset_smc(struct radeon_device *rdev);
384int si_program_jump_on_start(struct radeon_device *rdev);
385void si_stop_smc_clock(struct radeon_device *rdev);
386void si_start_smc_clock(struct radeon_device *rdev);
387bool si_is_smc_running(struct radeon_device *rdev);
388PPSMC_Result si_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg);
389PPSMC_Result si_wait_for_smc_inactive(struct radeon_device *rdev);
390int si_load_smc_ucode(struct radeon_device *rdev, u32 limit);
391int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
392 u32 *value, u32 limit);
393int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
394 u32 value, u32 limit);
395
396#endif
397
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-10 16:47:02 -0500