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authorIngo Molnar <mingo@elte.hu>2011-04-14 02:50:37 -0400
committerIngo Molnar <mingo@elte.hu>2011-04-14 02:51:07 -0400
commita4c98f8bbeafee12c979c90743f6fda94f7515c7 (patch)
tree3dda24b8a2ec42ab7b42845cb68c8b6e1b0d501f /drivers/gpu/drm
parentf4ad9bd208c98f32a6f9136618e0b8bebe3fb370 (diff)
parent85f2e689a5c8fb6ed8fdbee00109e7f6e5fefcb6 (diff)
Merge branch 'linus' into sched/locking
Merge reason: Pick up this upstream commit: 6631e635c65d: block: don't flush plugged IO on forced preemtion scheduling As it modifies the scheduler and we'll queue up dependent patches. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/Kconfig1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.c53
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_mem.c76
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_perf.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c12
-rw-r--r--drivers/gpu/drm/nouveau/nv04_dfp.c13
-rw-r--r--drivers/gpu/drm/nouveau/nv50_crtc.c3
-rw-r--r--drivers/gpu/drm/nouveau/nv50_evo.c1
-rw-r--r--drivers/gpu/drm/nouveau/nv50_graph.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_vm.c24
-rw-r--r--drivers/gpu/drm/radeon/atom.c6
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c6
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c17
-rw-r--r--drivers/gpu/drm/radeon/r600.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon.h12
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c30
-rw-r--r--drivers/gpu/drm/radeon/radeon_fence.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_gart.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_i2c.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_encoders.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c11
-rw-r--r--drivers/gpu/drm/radeon/radeon_ring.c2
-rw-r--r--drivers/gpu/drm/radeon/rs600.c2
-rw-r--r--drivers/gpu/drm/radeon/rv770.c6
-rw-r--r--drivers/gpu/drm/ttm/ttm_page_alloc.c26
27 files changed, 200 insertions, 125 deletions
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index a6feb78c404c..c58f691ec3ce 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -96,6 +96,7 @@ config DRM_I915
96 # i915 depends on ACPI_VIDEO when ACPI is enabled 96 # i915 depends on ACPI_VIDEO when ACPI is enabled
97 # but for select to work, need to select ACPI_VIDEO's dependencies, ick 97 # but for select to work, need to select ACPI_VIDEO's dependencies, ick
98 select BACKLIGHT_CLASS_DEVICE if ACPI 98 select BACKLIGHT_CLASS_DEVICE if ACPI
99 select VIDEO_OUTPUT_CONTROL if ACPI
99 select INPUT if ACPI 100 select INPUT if ACPI
100 select ACPI_VIDEO if ACPI 101 select ACPI_VIDEO if ACPI
101 select ACPI_BUTTON if ACPI 102 select ACPI_BUTTON if ACPI
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 8314a49b6b9a..90aef64b76f2 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -269,7 +269,7 @@ struct init_tbl_entry {
269 int (*handler)(struct nvbios *, uint16_t, struct init_exec *); 269 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
270}; 270};
271 271
272static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *); 272static int parse_init_table(struct nvbios *, uint16_t, struct init_exec *);
273 273
274#define MACRO_INDEX_SIZE 2 274#define MACRO_INDEX_SIZE 2
275#define MACRO_SIZE 8 275#define MACRO_SIZE 8
@@ -2011,6 +2011,27 @@ init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2011} 2011}
2012 2012
2013static int 2013static int
2014init_jump(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2015{
2016 /*
2017 * INIT_JUMP opcode: 0x5C ('\')
2018 *
2019 * offset (8 bit): opcode
2020 * offset + 1 (16 bit): offset (in bios)
2021 *
2022 * Continue execution of init table from 'offset'
2023 */
2024
2025 uint16_t jmp_offset = ROM16(bios->data[offset + 1]);
2026
2027 if (!iexec->execute)
2028 return 3;
2029
2030 BIOSLOG(bios, "0x%04X: Jump to 0x%04X\n", offset, jmp_offset);
2031 return jmp_offset - offset;
2032}
2033
2034static int
2014init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2035init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2015{ 2036{
2016 /* 2037 /*
@@ -3659,6 +3680,7 @@ static struct init_tbl_entry itbl_entry[] = {
3659 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence }, 3680 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
3660 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */ 3681 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
3661 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct }, 3682 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
3683 { "INIT_JUMP" , 0x5C, init_jump },
3662 { "INIT_I2C_IF" , 0x5E, init_i2c_if }, 3684 { "INIT_I2C_IF" , 0x5E, init_i2c_if },
3663 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg }, 3685 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3664 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io }, 3686 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
@@ -3700,8 +3722,7 @@ static struct init_tbl_entry itbl_entry[] = {
3700#define MAX_TABLE_OPS 1000 3722#define MAX_TABLE_OPS 1000
3701 3723
3702static int 3724static int
3703parse_init_table(struct nvbios *bios, unsigned int offset, 3725parse_init_table(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3704 struct init_exec *iexec)
3705{ 3726{
3706 /* 3727 /*
3707 * Parses all commands in an init table. 3728 * Parses all commands in an init table.
@@ -6333,6 +6354,32 @@ apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
6333 } 6354 }
6334 } 6355 }
6335 6356
6357 /* XFX GT-240X-YA
6358 *
6359 * So many things wrong here, replace the entire encoder table..
6360 */
6361 if (nv_match_device(dev, 0x0ca3, 0x1682, 0x3003)) {
6362 if (idx == 0) {
6363 *conn = 0x02001300; /* VGA, connector 1 */
6364 *conf = 0x00000028;
6365 } else
6366 if (idx == 1) {
6367 *conn = 0x01010312; /* DVI, connector 0 */
6368 *conf = 0x00020030;
6369 } else
6370 if (idx == 2) {
6371 *conn = 0x01010310; /* VGA, connector 0 */
6372 *conf = 0x00000028;
6373 } else
6374 if (idx == 3) {
6375 *conn = 0x02022362; /* HDMI, connector 2 */
6376 *conf = 0x00020010;
6377 } else {
6378 *conn = 0x0000000e; /* EOL */
6379 *conf = 0x00000000;
6380 }
6381 }
6382
6336 return true; 6383 return true;
6337} 6384}
6338 6385
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 57e5302503db..856d56a98d1e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -1190,7 +1190,7 @@ extern int nv50_graph_load_context(struct nouveau_channel *);
1190extern int nv50_graph_unload_context(struct drm_device *); 1190extern int nv50_graph_unload_context(struct drm_device *);
1191extern int nv50_grctx_init(struct nouveau_grctx *); 1191extern int nv50_grctx_init(struct nouveau_grctx *);
1192extern void nv50_graph_tlb_flush(struct drm_device *dev); 1192extern void nv50_graph_tlb_flush(struct drm_device *dev);
1193extern void nv86_graph_tlb_flush(struct drm_device *dev); 1193extern void nv84_graph_tlb_flush(struct drm_device *dev);
1194extern struct nouveau_enum nv50_data_error_names[]; 1194extern struct nouveau_enum nv50_data_error_names[];
1195 1195
1196/* nvc0_graph.c */ 1196/* nvc0_graph.c */
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 2683377f4131..78f467fe30be 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -552,6 +552,7 @@ nouveau_mem_timing_init(struct drm_device *dev)
552 u8 tRC; /* Byte 9 */ 552 u8 tRC; /* Byte 9 */
553 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14; 553 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14;
554 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21; 554 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21;
555 u8 magic_number = 0; /* Yeah... sorry*/
555 u8 *mem = NULL, *entry; 556 u8 *mem = NULL, *entry;
556 int i, recordlen, entries; 557 int i, recordlen, entries;
557 558
@@ -596,6 +597,12 @@ nouveau_mem_timing_init(struct drm_device *dev)
596 if (!memtimings->timing) 597 if (!memtimings->timing)
597 return; 598 return;
598 599
600 /* Get "some number" from the timing reg for NV_40
601 * Used in calculations later */
602 if(dev_priv->card_type == NV_40) {
603 magic_number = (nv_rd32(dev,0x100228) & 0x0f000000) >> 24;
604 }
605
599 entry = mem + mem[1]; 606 entry = mem + mem[1];
600 for (i = 0; i < entries; i++, entry += recordlen) { 607 for (i = 0; i < entries; i++, entry += recordlen) {
601 struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i]; 608 struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i];
@@ -635,36 +642,51 @@ nouveau_mem_timing_init(struct drm_device *dev)
635 642
636 /* XXX: I don't trust the -1's and +1's... they must come 643 /* XXX: I don't trust the -1's and +1's... they must come
637 * from somewhere! */ 644 * from somewhere! */
638 timing->reg_100224 = ((tUNK_0 + tUNK_19 + 1) << 24 | 645 timing->reg_100224 = (tUNK_0 + tUNK_19 + 1 + magic_number) << 24 |
639 tUNK_18 << 16 | 646 tUNK_18 << 16 |
640 (tUNK_1 + tUNK_19 + 1) << 8 | 647 (tUNK_1 + tUNK_19 + 1 + magic_number) << 8;
641 (tUNK_2 - 1)); 648 if(dev_priv->chipset == 0xa8) {
649 timing->reg_100224 |= (tUNK_2 - 1);
650 } else {
651 timing->reg_100224 |= (tUNK_2 + 2 - magic_number);
652 }
642 653
643 timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10); 654 timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10);
644 if(recordlen > 19) { 655 if(dev_priv->chipset >= 0xa3 && dev_priv->chipset < 0xaa) {
645 timing->reg_100228 += (tUNK_19 - 1) << 24; 656 timing->reg_100228 |= (tUNK_19 - 1) << 24;
646 }/* I cannot back-up this else-statement right now 657 }
647 else { 658
648 timing->reg_100228 += tUNK_12 << 24; 659 if(dev_priv->card_type == NV_40) {
649 }*/ 660 /* NV40: don't know what the rest of the regs are..
650 661 * And don't need to know either */
651 /* XXX: reg_10022c */ 662 timing->reg_100228 |= 0x20200000 | magic_number << 24;
652 timing->reg_10022c = tUNK_2 - 1; 663 } else if(dev_priv->card_type >= NV_50) {
653 664 /* XXX: reg_10022c */
654 timing->reg_100230 = (tUNK_20 << 24 | tUNK_21 << 16 | 665 timing->reg_10022c = tUNK_2 - 1;
655 tUNK_13 << 8 | tUNK_13); 666
656 667 timing->reg_100230 = (tUNK_20 << 24 | tUNK_21 << 16 |
657 /* XXX: +6? */ 668 tUNK_13 << 8 | tUNK_13);
658 timing->reg_100234 = (tRAS << 24 | (tUNK_19 + 6) << 8 | tRC); 669
659 timing->reg_100234 += max(tUNK_10,tUNK_11) << 16; 670 timing->reg_100234 = (tRAS << 24 | tRC);
660 671 timing->reg_100234 += max(tUNK_10,tUNK_11) << 16;
661 /* XXX; reg_100238, reg_10023c 672
662 * reg: 0x00?????? 673 if(dev_priv->chipset < 0xa3) {
663 * reg_10023c: 674 timing->reg_100234 |= (tUNK_2 + 2) << 8;
664 * 0 for pre-NV50 cards 675 } else {
665 * 0x????0202 for NV50+ cards (empirical evidence) */ 676 /* XXX: +6? */
666 if(dev_priv->card_type >= NV_50) { 677 timing->reg_100234 |= (tUNK_19 + 6) << 8;
678 }
679
680 /* XXX; reg_100238, reg_10023c
681 * reg_100238: 0x00??????
682 * reg_10023c: 0x!!??0202 for NV50+ cards (empirical evidence) */
667 timing->reg_10023c = 0x202; 683 timing->reg_10023c = 0x202;
684 if(dev_priv->chipset < 0xa3) {
685 timing->reg_10023c |= 0x4000000 | (tUNK_2 - 1) << 16;
686 } else {
687 /* currently unknown
688 * 10023c seen as 06xxxxxx, 0bxxxxxx or 0fxxxxxx */
689 }
668 } 690 }
669 691
670 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", i, 692 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", i,
@@ -675,7 +697,7 @@ nouveau_mem_timing_init(struct drm_device *dev)
675 timing->reg_100238, timing->reg_10023c); 697 timing->reg_100238, timing->reg_10023c);
676 } 698 }
677 699
678 memtimings->nr_timing = entries; 700 memtimings->nr_timing = entries;
679 memtimings->supported = true; 701 memtimings->supported = true;
680} 702}
681 703
diff --git a/drivers/gpu/drm/nouveau/nouveau_perf.c b/drivers/gpu/drm/nouveau/nouveau_perf.c
index ac62a1b8c4fc..670e3cb697ec 100644
--- a/drivers/gpu/drm/nouveau/nouveau_perf.c
+++ b/drivers/gpu/drm/nouveau/nouveau_perf.c
@@ -134,7 +134,7 @@ nouveau_perf_init(struct drm_device *dev)
134 case 0x13: 134 case 0x13:
135 case 0x15: 135 case 0x15:
136 perflvl->fanspeed = entry[55]; 136 perflvl->fanspeed = entry[55];
137 perflvl->voltage = entry[56]; 137 perflvl->voltage = (recordlen > 56) ? entry[56] : 0;
138 perflvl->core = ROM32(entry[1]) * 10; 138 perflvl->core = ROM32(entry[1]) * 10;
139 perflvl->memory = ROM32(entry[5]) * 20; 139 perflvl->memory = ROM32(entry[5]) * 20;
140 break; 140 break;
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 5bb2859001e2..6e2b1a6caa2d 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -376,15 +376,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
376 engine->graph.destroy_context = nv50_graph_destroy_context; 376 engine->graph.destroy_context = nv50_graph_destroy_context;
377 engine->graph.load_context = nv50_graph_load_context; 377 engine->graph.load_context = nv50_graph_load_context;
378 engine->graph.unload_context = nv50_graph_unload_context; 378 engine->graph.unload_context = nv50_graph_unload_context;
379 if (dev_priv->chipset != 0x86) 379 if (dev_priv->chipset == 0x50 ||
380 dev_priv->chipset == 0xac)
380 engine->graph.tlb_flush = nv50_graph_tlb_flush; 381 engine->graph.tlb_flush = nv50_graph_tlb_flush;
381 else { 382 else
382 /* from what i can see nvidia do this on every 383 engine->graph.tlb_flush = nv84_graph_tlb_flush;
383 * pre-NVA3 board except NVAC, but, we've only
384 * ever seen problems on NV86
385 */
386 engine->graph.tlb_flush = nv86_graph_tlb_flush;
387 }
388 engine->fifo.channels = 128; 384 engine->fifo.channels = 128;
389 engine->fifo.init = nv50_fifo_init; 385 engine->fifo.init = nv50_fifo_init;
390 engine->fifo.takedown = nv50_fifo_takedown; 386 engine->fifo.takedown = nv50_fifo_takedown;
diff --git a/drivers/gpu/drm/nouveau/nv04_dfp.c b/drivers/gpu/drm/nouveau/nv04_dfp.c
index c82db37d9f41..12098bf839c4 100644
--- a/drivers/gpu/drm/nouveau/nv04_dfp.c
+++ b/drivers/gpu/drm/nouveau/nv04_dfp.c
@@ -581,12 +581,13 @@ static void nv04_dfp_restore(struct drm_encoder *encoder)
581 int head = nv_encoder->restore.head; 581 int head = nv_encoder->restore.head;
582 582
583 if (nv_encoder->dcb->type == OUTPUT_LVDS) { 583 if (nv_encoder->dcb->type == OUTPUT_LVDS) {
584 struct drm_display_mode *native_mode = nouveau_encoder_connector_get(nv_encoder)->native_mode; 584 struct nouveau_connector *connector =
585 if (native_mode) 585 nouveau_encoder_connector_get(nv_encoder);
586 call_lvds_script(dev, nv_encoder->dcb, head, LVDS_PANEL_ON, 586
587 native_mode->clock); 587 if (connector && connector->native_mode)
588 else 588 call_lvds_script(dev, nv_encoder->dcb, head,
589 NV_ERROR(dev, "Not restoring LVDS without native mode\n"); 589 LVDS_PANEL_ON,
590 connector->native_mode->clock);
590 591
591 } else if (nv_encoder->dcb->type == OUTPUT_TMDS) { 592 } else if (nv_encoder->dcb->type == OUTPUT_TMDS) {
592 int clock = nouveau_hw_pllvals_to_clk 593 int clock = nouveau_hw_pllvals_to_clk
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c
index 2b9984027f41..a19ccaa025b3 100644
--- a/drivers/gpu/drm/nouveau/nv50_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c
@@ -469,9 +469,6 @@ nv50_crtc_wait_complete(struct drm_crtc *crtc)
469 469
470 start = ptimer->read(dev); 470 start = ptimer->read(dev);
471 do { 471 do {
472 nv_wr32(dev, 0x61002c, 0x370);
473 nv_wr32(dev, 0x000140, 1);
474
475 if (nv_ro32(disp->ntfy, 0x000)) 472 if (nv_ro32(disp->ntfy, 0x000))
476 return 0; 473 return 0;
477 } while (ptimer->read(dev) - start < 2000000000ULL); 474 } while (ptimer->read(dev) - start < 2000000000ULL);
diff --git a/drivers/gpu/drm/nouveau/nv50_evo.c b/drivers/gpu/drm/nouveau/nv50_evo.c
index a2cfaa691e9b..c8e83c1a4de8 100644
--- a/drivers/gpu/drm/nouveau/nv50_evo.c
+++ b/drivers/gpu/drm/nouveau/nv50_evo.c
@@ -186,6 +186,7 @@ nv50_evo_channel_init(struct nouveau_channel *evo)
186 nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << id); 186 nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << id);
187 187
188 evo->dma.max = (4096/4) - 2; 188 evo->dma.max = (4096/4) - 2;
189 evo->dma.max &= ~7;
189 evo->dma.put = 0; 190 evo->dma.put = 0;
190 evo->dma.cur = evo->dma.put; 191 evo->dma.cur = evo->dma.put;
191 evo->dma.free = evo->dma.max - evo->dma.cur; 192 evo->dma.free = evo->dma.max - evo->dma.cur;
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c
index 8675b00caf18..b02a5b1e7d37 100644
--- a/drivers/gpu/drm/nouveau/nv50_graph.c
+++ b/drivers/gpu/drm/nouveau/nv50_graph.c
@@ -503,7 +503,7 @@ nv50_graph_tlb_flush(struct drm_device *dev)
503} 503}
504 504
505void 505void
506nv86_graph_tlb_flush(struct drm_device *dev) 506nv84_graph_tlb_flush(struct drm_device *dev)
507{ 507{
508 struct drm_nouveau_private *dev_priv = dev->dev_private; 508 struct drm_nouveau_private *dev_priv = dev->dev_private;
509 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; 509 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
diff --git a/drivers/gpu/drm/nouveau/nvc0_vm.c b/drivers/gpu/drm/nouveau/nvc0_vm.c
index 69af0ba7edd3..a0a2a0277f73 100644
--- a/drivers/gpu/drm/nouveau/nvc0_vm.c
+++ b/drivers/gpu/drm/nouveau/nvc0_vm.c
@@ -104,20 +104,26 @@ nvc0_vm_flush(struct nouveau_vm *vm)
104 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem; 104 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
105 struct drm_device *dev = vm->dev; 105 struct drm_device *dev = vm->dev;
106 struct nouveau_vm_pgd *vpgd; 106 struct nouveau_vm_pgd *vpgd;
107 u32 r100c80, engine; 107 u32 engine = (dev_priv->chan_vm == vm) ? 1 : 5;
108 108
109 pinstmem->flush(vm->dev); 109 pinstmem->flush(vm->dev);
110 110
111 if (vm == dev_priv->chan_vm) 111 spin_lock(&dev_priv->ramin_lock);
112 engine = 1;
113 else
114 engine = 5;
115
116 list_for_each_entry(vpgd, &vm->pgd_list, head) { 112 list_for_each_entry(vpgd, &vm->pgd_list, head) {
117 r100c80 = nv_rd32(dev, 0x100c80); 113 /* looks like maybe a "free flush slots" counter, the
114 * faster you write to 0x100cbc to more it decreases
115 */
116 if (!nv_wait_ne(dev, 0x100c80, 0x00ff0000, 0x00000000)) {
117 NV_ERROR(dev, "vm timeout 0: 0x%08x %d\n",
118 nv_rd32(dev, 0x100c80), engine);
119 }
118 nv_wr32(dev, 0x100cb8, vpgd->obj->vinst >> 8); 120 nv_wr32(dev, 0x100cb8, vpgd->obj->vinst >> 8);
119 nv_wr32(dev, 0x100cbc, 0x80000000 | engine); 121 nv_wr32(dev, 0x100cbc, 0x80000000 | engine);
120 if (!nv_wait(dev, 0x100c80, 0xffffffff, r100c80)) 122 /* wait for flush to be queued? */
121 NV_ERROR(dev, "vm flush timeout eng %d\n", engine); 123 if (!nv_wait(dev, 0x100c80, 0x00008000, 0x00008000)) {
124 NV_ERROR(dev, "vm timeout 1: 0x%08x %d\n",
125 nv_rd32(dev, 0x100c80), engine);
126 }
122 } 127 }
128 spin_unlock(&dev_priv->ramin_lock);
123} 129}
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index 258fa5e7a2d9..d71d375149f8 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -32,6 +32,7 @@
32#include "atom.h" 32#include "atom.h"
33#include "atom-names.h" 33#include "atom-names.h"
34#include "atom-bits.h" 34#include "atom-bits.h"
35#include "radeon.h"
35 36
36#define ATOM_COND_ABOVE 0 37#define ATOM_COND_ABOVE 0
37#define ATOM_COND_ABOVEOREQUAL 1 38#define ATOM_COND_ABOVEOREQUAL 1
@@ -101,7 +102,9 @@ static void debug_print_spaces(int n)
101static uint32_t atom_iio_execute(struct atom_context *ctx, int base, 102static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
102 uint32_t index, uint32_t data) 103 uint32_t index, uint32_t data)
103{ 104{
105 struct radeon_device *rdev = ctx->card->dev->dev_private;
104 uint32_t temp = 0xCDCDCDCD; 106 uint32_t temp = 0xCDCDCDCD;
107
105 while (1) 108 while (1)
106 switch (CU8(base)) { 109 switch (CU8(base)) {
107 case ATOM_IIO_NOP: 110 case ATOM_IIO_NOP:
@@ -112,7 +115,8 @@ static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
112 base += 3; 115 base += 3;
113 break; 116 break;
114 case ATOM_IIO_WRITE: 117 case ATOM_IIO_WRITE:
115 (void)ctx->card->ioreg_read(ctx->card, CU16(base + 1)); 118 if (rdev->family == CHIP_RV515)
119 (void)ctx->card->ioreg_read(ctx->card, CU16(base + 1));
116 ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp); 120 ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp);
117 base += 3; 121 base += 3;
118 break; 122 break;
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index b41ec59c7100..9d516a8c4dfa 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -531,6 +531,12 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
531 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 531 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
532 else 532 else
533 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 533 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
534
535 if ((rdev->family == CHIP_R600) ||
536 (rdev->family == CHIP_RV610) ||
537 (rdev->family == CHIP_RV630) ||
538 (rdev->family == CHIP_RV670))
539 pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
534 } else { 540 } else {
535 pll->flags |= RADEON_PLL_LEGACY; 541 pll->flags |= RADEON_PLL_LEGACY;
536 542
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 0b0cc74c08c0..3453910ee0f3 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -120,11 +120,16 @@ void evergreen_pm_misc(struct radeon_device *rdev)
120 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 120 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
121 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 121 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
122 122
123 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 123 if (voltage->type == VOLTAGE_SW) {
124 if (voltage->voltage != rdev->pm.current_vddc) { 124 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
125 radeon_atom_set_voltage(rdev, voltage->voltage); 125 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
126 rdev->pm.current_vddc = voltage->voltage; 126 rdev->pm.current_vddc = voltage->voltage;
127 DRM_DEBUG("Setting: v: %d\n", voltage->voltage); 127 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
128 }
129 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
130 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
131 rdev->pm.current_vddci = voltage->vddci;
132 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
128 } 133 }
129 } 134 }
130} 135}
@@ -3036,9 +3041,6 @@ int evergreen_init(struct radeon_device *rdev)
3036{ 3041{
3037 int r; 3042 int r;
3038 3043
3039 r = radeon_dummy_page_init(rdev);
3040 if (r)
3041 return r;
3042 /* This don't do much */ 3044 /* This don't do much */
3043 r = radeon_gem_init(rdev); 3045 r = radeon_gem_init(rdev);
3044 if (r) 3046 if (r)
@@ -3150,7 +3152,6 @@ void evergreen_fini(struct radeon_device *rdev)
3150 radeon_atombios_fini(rdev); 3152 radeon_atombios_fini(rdev);
3151 kfree(rdev->bios); 3153 kfree(rdev->bios);
3152 rdev->bios = NULL; 3154 rdev->bios = NULL;
3153 radeon_dummy_page_fini(rdev);
3154} 3155}
3155 3156
3156static void evergreen_pcie_gen2_enable(struct radeon_device *rdev) 3157static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index be271c42de4d..15d58292677a 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -587,7 +587,7 @@ void r600_pm_misc(struct radeon_device *rdev)
587 587
588 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 588 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
589 if (voltage->voltage != rdev->pm.current_vddc) { 589 if (voltage->voltage != rdev->pm.current_vddc) {
590 radeon_atom_set_voltage(rdev, voltage->voltage); 590 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
591 rdev->pm.current_vddc = voltage->voltage; 591 rdev->pm.current_vddc = voltage->voltage;
592 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); 592 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
593 } 593 }
@@ -2509,9 +2509,6 @@ int r600_init(struct radeon_device *rdev)
2509{ 2509{
2510 int r; 2510 int r;
2511 2511
2512 r = radeon_dummy_page_init(rdev);
2513 if (r)
2514 return r;
2515 if (r600_debugfs_mc_info_init(rdev)) { 2512 if (r600_debugfs_mc_info_init(rdev)) {
2516 DRM_ERROR("Failed to register debugfs file for mc !\n"); 2513 DRM_ERROR("Failed to register debugfs file for mc !\n");
2517 } 2514 }
@@ -2625,7 +2622,6 @@ void r600_fini(struct radeon_device *rdev)
2625 radeon_atombios_fini(rdev); 2622 radeon_atombios_fini(rdev);
2626 kfree(rdev->bios); 2623 kfree(rdev->bios);
2627 rdev->bios = NULL; 2624 rdev->bios = NULL;
2628 radeon_dummy_page_fini(rdev);
2629} 2625}
2630 2626
2631 2627
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 93f536594c73..ba643b576054 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -177,7 +177,7 @@ void radeon_pm_suspend(struct radeon_device *rdev);
177void radeon_pm_resume(struct radeon_device *rdev); 177void radeon_pm_resume(struct radeon_device *rdev);
178void radeon_combios_get_power_modes(struct radeon_device *rdev); 178void radeon_combios_get_power_modes(struct radeon_device *rdev);
179void radeon_atombios_get_power_modes(struct radeon_device *rdev); 179void radeon_atombios_get_power_modes(struct radeon_device *rdev);
180void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level); 180void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
181void rs690_pm_info(struct radeon_device *rdev); 181void rs690_pm_info(struct radeon_device *rdev);
182extern int rv6xx_get_temp(struct radeon_device *rdev); 182extern int rv6xx_get_temp(struct radeon_device *rdev);
183extern int rv770_get_temp(struct radeon_device *rdev); 183extern int rv770_get_temp(struct radeon_device *rdev);
@@ -767,7 +767,9 @@ struct radeon_voltage {
767 u8 vddci_id; /* index into vddci voltage table */ 767 u8 vddci_id; /* index into vddci voltage table */
768 bool vddci_enabled; 768 bool vddci_enabled;
769 /* r6xx+ sw */ 769 /* r6xx+ sw */
770 u32 voltage; 770 u16 voltage;
771 /* evergreen+ vddci */
772 u16 vddci;
771}; 773};
772 774
773/* clock mode flags */ 775/* clock mode flags */
@@ -835,10 +837,12 @@ struct radeon_pm {
835 int default_power_state_index; 837 int default_power_state_index;
836 u32 current_sclk; 838 u32 current_sclk;
837 u32 current_mclk; 839 u32 current_mclk;
838 u32 current_vddc; 840 u16 current_vddc;
841 u16 current_vddci;
839 u32 default_sclk; 842 u32 default_sclk;
840 u32 default_mclk; 843 u32 default_mclk;
841 u32 default_vddc; 844 u16 default_vddc;
845 u16 default_vddci;
842 struct radeon_i2c_chan *i2c_bus; 846 struct radeon_i2c_chan *i2c_bus;
843 /* selected pm method */ 847 /* selected pm method */
844 enum radeon_pm_method pm_method; 848 enum radeon_pm_method pm_method;
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index eb888ee5f674..ca576191d058 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -94,7 +94,7 @@ static void radeon_register_accessor_init(struct radeon_device *rdev)
94 rdev->mc_rreg = &rs600_mc_rreg; 94 rdev->mc_rreg = &rs600_mc_rreg;
95 rdev->mc_wreg = &rs600_mc_wreg; 95 rdev->mc_wreg = &rs600_mc_wreg;
96 } 96 }
97 if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_HEMLOCK)) { 97 if (rdev->family >= CHIP_R600) {
98 rdev->pciep_rreg = &r600_pciep_rreg; 98 rdev->pciep_rreg = &r600_pciep_rreg;
99 rdev->pciep_wreg = &r600_pciep_wreg; 99 rdev->pciep_wreg = &r600_pciep_wreg;
100 } 100 }
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 99768d9d91da..f5d12fb103fa 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -2176,24 +2176,27 @@ static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *r
2176 } 2176 }
2177} 2177}
2178 2178
2179static u16 radeon_atombios_get_default_vddc(struct radeon_device *rdev) 2179static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2180 u16 *vddc, u16 *vddci)
2180{ 2181{
2181 struct radeon_mode_info *mode_info = &rdev->mode_info; 2182 struct radeon_mode_info *mode_info = &rdev->mode_info;
2182 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 2183 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2183 u8 frev, crev; 2184 u8 frev, crev;
2184 u16 data_offset; 2185 u16 data_offset;
2185 union firmware_info *firmware_info; 2186 union firmware_info *firmware_info;
2186 u16 vddc = 0; 2187
2188 *vddc = 0;
2189 *vddci = 0;
2187 2190
2188 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2191 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2189 &frev, &crev, &data_offset)) { 2192 &frev, &crev, &data_offset)) {
2190 firmware_info = 2193 firmware_info =
2191 (union firmware_info *)(mode_info->atom_context->bios + 2194 (union firmware_info *)(mode_info->atom_context->bios +
2192 data_offset); 2195 data_offset);
2193 vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); 2196 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2197 if ((frev == 2) && (crev >= 2))
2198 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2194 } 2199 }
2195
2196 return vddc;
2197} 2200}
2198 2201
2199static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev, 2202static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
@@ -2203,7 +2206,9 @@ static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rde
2203 int j; 2206 int j;
2204 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); 2207 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2205 u32 misc2 = le16_to_cpu(non_clock_info->usClassification); 2208 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2206 u16 vddc = radeon_atombios_get_default_vddc(rdev); 2209 u16 vddc, vddci;
2210
2211 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2207 2212
2208 rdev->pm.power_state[state_index].misc = misc; 2213 rdev->pm.power_state[state_index].misc = misc;
2209 rdev->pm.power_state[state_index].misc2 = misc2; 2214 rdev->pm.power_state[state_index].misc2 = misc2;
@@ -2244,6 +2249,7 @@ static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rde
2244 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; 2249 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2245 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; 2250 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2246 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage; 2251 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2252 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2247 } else { 2253 } else {
2248 /* patch the table values with the default slck/mclk from firmware info */ 2254 /* patch the table values with the default slck/mclk from firmware info */
2249 for (j = 0; j < mode_index; j++) { 2255 for (j = 0; j < mode_index; j++) {
@@ -2286,6 +2292,8 @@ static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2286 VOLTAGE_SW; 2292 VOLTAGE_SW;
2287 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2293 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2288 le16_to_cpu(clock_info->evergreen.usVDDC); 2294 le16_to_cpu(clock_info->evergreen.usVDDC);
2295 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2296 le16_to_cpu(clock_info->evergreen.usVDDCI);
2289 } else { 2297 } else {
2290 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); 2298 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2291 sclk |= clock_info->r600.ucEngineClockHigh << 16; 2299 sclk |= clock_info->r600.ucEngineClockHigh << 16;
@@ -2577,25 +2585,25 @@ union set_voltage {
2577 struct _SET_VOLTAGE_PARAMETERS_V2 v2; 2585 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2578}; 2586};
2579 2587
2580void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level) 2588void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2581{ 2589{
2582 union set_voltage args; 2590 union set_voltage args;
2583 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 2591 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2584 u8 frev, crev, volt_index = level; 2592 u8 frev, crev, volt_index = voltage_level;
2585 2593
2586 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2594 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2587 return; 2595 return;
2588 2596
2589 switch (crev) { 2597 switch (crev) {
2590 case 1: 2598 case 1:
2591 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC; 2599 args.v1.ucVoltageType = voltage_type;
2592 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; 2600 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2593 args.v1.ucVoltageIndex = volt_index; 2601 args.v1.ucVoltageIndex = volt_index;
2594 break; 2602 break;
2595 case 2: 2603 case 2:
2596 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC; 2604 args.v2.ucVoltageType = voltage_type;
2597 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; 2605 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2598 args.v2.usVoltageLevel = cpu_to_le16(level); 2606 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2599 break; 2607 break;
2600 default: 2608 default:
2601 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 2609 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 9e59868d354e..bbcd1dd7bac0 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -79,7 +79,7 @@ static bool radeon_fence_poll_locked(struct radeon_device *rdev)
79 scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base; 79 scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
80 else 80 else
81 scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base; 81 scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
82 seq = rdev->wb.wb[scratch_index/4]; 82 seq = le32_to_cpu(rdev->wb.wb[scratch_index/4]);
83 } else 83 } else
84 seq = RREG32(rdev->fence_drv.scratch_reg); 84 seq = RREG32(rdev->fence_drv.scratch_reg);
85 if (seq != rdev->fence_drv.last_seq) { 85 if (seq != rdev->fence_drv.last_seq) {
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
index f0534ef2f331..8a955bbdb608 100644
--- a/drivers/gpu/drm/radeon/radeon_gart.c
+++ b/drivers/gpu/drm/radeon/radeon_gart.c
@@ -285,4 +285,6 @@ void radeon_gart_fini(struct radeon_device *rdev)
285 rdev->gart.pages = NULL; 285 rdev->gart.pages = NULL;
286 rdev->gart.pages_addr = NULL; 286 rdev->gart.pages_addr = NULL;
287 rdev->gart.ttm_alloced = NULL; 287 rdev->gart.ttm_alloced = NULL;
288
289 radeon_dummy_page_fini(rdev);
288} 290}
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
index ded2a45bc95c..ccbabf734a61 100644
--- a/drivers/gpu/drm/radeon/radeon_i2c.c
+++ b/drivers/gpu/drm/radeon/radeon_i2c.c
@@ -1062,7 +1062,7 @@ void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1062 *val = in_buf[0]; 1062 *val = in_buf[0];
1063 DRM_DEBUG("val = 0x%02x\n", *val); 1063 DRM_DEBUG("val = 0x%02x\n", *val);
1064 } else { 1064 } else {
1065 DRM_ERROR("i2c 0x%02x 0x%02x read failed\n", 1065 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
1066 addr, *val); 1066 addr, *val);
1067 } 1067 }
1068} 1068}
@@ -1084,7 +1084,7 @@ void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1084 out_buf[1] = val; 1084 out_buf[1] = val;
1085 1085
1086 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) 1086 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1087 DRM_ERROR("i2c 0x%02x 0x%02x write failed\n", 1087 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
1088 addr, val); 1088 addr, val);
1089} 1089}
1090 1090
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index 5b54268ed6b2..2f46e0c8df53 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -269,7 +269,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
269 .disable = radeon_legacy_encoder_disable, 269 .disable = radeon_legacy_encoder_disable,
270}; 270};
271 271
272#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 272#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
273 273
274#define MAX_RADEON_LEVEL 0xFF 274#define MAX_RADEON_LEVEL 0xFF
275 275
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 08de669e025a..86eda1ea94df 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -23,6 +23,7 @@
23#include "drmP.h" 23#include "drmP.h"
24#include "radeon.h" 24#include "radeon.h"
25#include "avivod.h" 25#include "avivod.h"
26#include "atom.h"
26#ifdef CONFIG_ACPI 27#ifdef CONFIG_ACPI
27#include <linux/acpi.h> 28#include <linux/acpi.h>
28#endif 29#endif
@@ -535,7 +536,11 @@ void radeon_pm_resume(struct radeon_device *rdev)
535 /* set up the default clocks if the MC ucode is loaded */ 536 /* set up the default clocks if the MC ucode is loaded */
536 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) { 537 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
537 if (rdev->pm.default_vddc) 538 if (rdev->pm.default_vddc)
538 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc); 539 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
540 SET_VOLTAGE_TYPE_ASIC_VDDC);
541 if (rdev->pm.default_vddci)
542 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
543 SET_VOLTAGE_TYPE_ASIC_VDDCI);
539 if (rdev->pm.default_sclk) 544 if (rdev->pm.default_sclk)
540 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 545 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
541 if (rdev->pm.default_mclk) 546 if (rdev->pm.default_mclk)
@@ -548,6 +553,7 @@ void radeon_pm_resume(struct radeon_device *rdev)
548 rdev->pm.current_sclk = rdev->pm.default_sclk; 553 rdev->pm.current_sclk = rdev->pm.default_sclk;
549 rdev->pm.current_mclk = rdev->pm.default_mclk; 554 rdev->pm.current_mclk = rdev->pm.default_mclk;
550 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 555 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
556 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
551 if (rdev->pm.pm_method == PM_METHOD_DYNPM 557 if (rdev->pm.pm_method == PM_METHOD_DYNPM
552 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { 558 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
553 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 559 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
@@ -585,7 +591,8 @@ int radeon_pm_init(struct radeon_device *rdev)
585 /* set up the default clocks if the MC ucode is loaded */ 591 /* set up the default clocks if the MC ucode is loaded */
586 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) { 592 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
587 if (rdev->pm.default_vddc) 593 if (rdev->pm.default_vddc)
588 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc); 594 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
595 SET_VOLTAGE_TYPE_ASIC_VDDC);
589 if (rdev->pm.default_sclk) 596 if (rdev->pm.default_sclk)
590 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 597 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
591 if (rdev->pm.default_mclk) 598 if (rdev->pm.default_mclk)
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index bbc9cd823334..c6776e48fdde 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -248,7 +248,7 @@ void radeon_ib_pool_fini(struct radeon_device *rdev)
248void radeon_ring_free_size(struct radeon_device *rdev) 248void radeon_ring_free_size(struct radeon_device *rdev)
249{ 249{
250 if (rdev->wb.enabled) 250 if (rdev->wb.enabled)
251 rdev->cp.rptr = rdev->wb.wb[RADEON_WB_CP_RPTR_OFFSET/4]; 251 rdev->cp.rptr = le32_to_cpu(rdev->wb.wb[RADEON_WB_CP_RPTR_OFFSET/4]);
252 else { 252 else {
253 if (rdev->family >= CHIP_R600) 253 if (rdev->family >= CHIP_R600)
254 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR); 254 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 876cebc4b8ba..6e3b11e5abbe 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -114,7 +114,7 @@ void rs600_pm_misc(struct radeon_device *rdev)
114 udelay(voltage->delay); 114 udelay(voltage->delay);
115 } 115 }
116 } else if (voltage->type == VOLTAGE_VDDC) 116 } else if (voltage->type == VOLTAGE_VDDC)
117 radeon_atom_set_voltage(rdev, voltage->vddc_id); 117 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
118 118
119 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH); 119 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
120 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf); 120 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index b974ac7df8df..ef8a5babe9f7 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -106,7 +106,7 @@ void rv770_pm_misc(struct radeon_device *rdev)
106 106
107 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 107 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
108 if (voltage->voltage != rdev->pm.current_vddc) { 108 if (voltage->voltage != rdev->pm.current_vddc) {
109 radeon_atom_set_voltage(rdev, voltage->voltage); 109 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
110 rdev->pm.current_vddc = voltage->voltage; 110 rdev->pm.current_vddc = voltage->voltage;
111 DRM_DEBUG("Setting: v: %d\n", voltage->voltage); 111 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
112 } 112 }
@@ -1255,9 +1255,6 @@ int rv770_init(struct radeon_device *rdev)
1255{ 1255{
1256 int r; 1256 int r;
1257 1257
1258 r = radeon_dummy_page_init(rdev);
1259 if (r)
1260 return r;
1261 /* This don't do much */ 1258 /* This don't do much */
1262 r = radeon_gem_init(rdev); 1259 r = radeon_gem_init(rdev);
1263 if (r) 1260 if (r)
@@ -1372,7 +1369,6 @@ void rv770_fini(struct radeon_device *rdev)
1372 radeon_atombios_fini(rdev); 1369 radeon_atombios_fini(rdev);
1373 kfree(rdev->bios); 1370 kfree(rdev->bios);
1374 rdev->bios = NULL; 1371 rdev->bios = NULL;
1375 radeon_dummy_page_fini(rdev);
1376} 1372}
1377 1373
1378static void rv770_pcie_gen2_enable(struct radeon_device *rdev) 1374static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index 737a2a2e46a5..9d9d92945f8c 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -683,22 +683,14 @@ int ttm_get_pages(struct list_head *pages, int flags,
683 gfp_flags |= GFP_HIGHUSER; 683 gfp_flags |= GFP_HIGHUSER;
684 684
685 for (r = 0; r < count; ++r) { 685 for (r = 0; r < count; ++r) {
686 if ((flags & TTM_PAGE_FLAG_DMA32) && dma_address) { 686 p = alloc_page(gfp_flags);
687 void *addr;
688 addr = dma_alloc_coherent(NULL, PAGE_SIZE,
689 &dma_address[r],
690 gfp_flags);
691 if (addr == NULL)
692 return -ENOMEM;
693 p = virt_to_page(addr);
694 } else
695 p = alloc_page(gfp_flags);
696 if (!p) { 687 if (!p) {
697 688
698 printk(KERN_ERR TTM_PFX 689 printk(KERN_ERR TTM_PFX
699 "Unable to allocate page."); 690 "Unable to allocate page.");
700 return -ENOMEM; 691 return -ENOMEM;
701 } 692 }
693
702 list_add(&p->lru, pages); 694 list_add(&p->lru, pages);
703 } 695 }
704 return 0; 696 return 0;
@@ -746,24 +738,12 @@ void ttm_put_pages(struct list_head *pages, unsigned page_count, int flags,
746 unsigned long irq_flags; 738 unsigned long irq_flags;
747 struct ttm_page_pool *pool = ttm_get_pool(flags, cstate); 739 struct ttm_page_pool *pool = ttm_get_pool(flags, cstate);
748 struct page *p, *tmp; 740 struct page *p, *tmp;
749 unsigned r;
750 741
751 if (pool == NULL) { 742 if (pool == NULL) {
752 /* No pool for this memory type so free the pages */ 743 /* No pool for this memory type so free the pages */
753 744
754 r = page_count-1;
755 list_for_each_entry_safe(p, tmp, pages, lru) { 745 list_for_each_entry_safe(p, tmp, pages, lru) {
756 if ((flags & TTM_PAGE_FLAG_DMA32) && dma_address) { 746 __free_page(p);
757 void *addr = page_address(p);
758 WARN_ON(!addr || !dma_address[r]);
759 if (addr)
760 dma_free_coherent(NULL, PAGE_SIZE,
761 addr,
762 dma_address[r]);
763 dma_address[r] = 0;
764 } else
765 __free_page(p);
766 r--;
767 } 747 }
768 /* Make the pages list empty */ 748 /* Make the pages list empty */
769 INIT_LIST_HEAD(pages); 749 INIT_LIST_HEAD(pages);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-31 11:25:12 -0500